JPH044796B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a sampling clock supply circuit for converting a video signal from analog to digital, such as when digitizing and transmitting a video signal.
In particular, it relates to improvements in sampling clock supply circuits for digitizing poor quality video signals from VTRs and the like.

In order to sample a video signal, a high-quality image can be reproduced by sampling with a sampling clock based on a signal synchronized with the horizontal synchronization signal of the video signal, but in the case of a VTR, etc., the precision of the head is poor, The synchronization signal may waver or drop out, or it may appear as noise similar to the horizontal synchronization signal in the image signal.

Even in such a case, it is desired to be able to supply a sampling clock that can reproduce an image of as high quality as possible.

[Conventional technology]

FIG. 3 is a block diagram showing the configuration of a conventional video signal transmission device.

In the figure, 1 is a clamp circuit, 2 is an A/D converter, and 3
is a coder, 4 is a line interface, 5 is an oscillator, 6 is a frequency divider, 7 is a PLL circuit, 8 is a signal quality judgment circuit, 9 is a synchronization signal detection circuit, 10 is a vertical synchronization signal removal circuit, 11 is a protection circuit , 20 is a sampling clock supply circuit, and SW is a switch.

In FIG. 3, an input video signal is clamped by a clamp circuit 1, converted into an analog-to-digital signal by an A/D converter 2 using a sampling clock, and is coded by a coder 3 and sent to a line interface 4. It is sent out to the transmission path via.

On the other hand, a horizontal synchronization signal and a vertical synchronization signal are detected by the synchronization signal detection circuit 9 from the video signal clamped by the clamp circuit 1, and the vertical synchronization signal is removed by the vertical synchronization signal removal circuit 10, leaving only the horizontal synchronization signal for protection. input to circuit 11;

The protection circuit 11 has a window that allows only horizontal synchronization signals with normal timing to pass through, and the horizontal synchronization signals with normal timing that pass through this window are passed through the PLL.
The signal is input to the circuit 7 and also to the signal quality determination circuit 8.

The PLL circuit 7 generates a sampling clock synchronized with this horizontal synchronizing signal and supplies it to the A/D converter 2 via the switch SW.

However, with low-quality video signals such as those from VTRs, the horizontal synchronization signal may waver or drop out, and in this case, a normal horizontal synchronization signal will not be input to the PLL circuit 7, and the output frequency will be greatly disturbed. Since the sampling clock is also greatly disturbed, the image quality is also significantly degraded. Therefore, the signal quality judgment circuit 8 judges the sampling clock, and the switch SW switches the sampling clock to an asynchronous sampling clock with a frequency of 5 and a frequency divider 6. We provide tools to help reproduce the highest quality images possible.

[Problem that the invention seeks to solve]

However, there are cases where noise similar to the horizontal synchronization signal is added to the image signal section. In such cases, the signal quality is poor and the sampling clock should be switched to the asynchronous side. Since the sampling clock is blocked and is not input to the signal quality determination circuit 8, accurate determination cannot be made, and the sampling clock remains supplied from the PLL circuit synchronized with the horizontal synchronization signal, resulting in a significant quality deterioration.

[Means for solving problems]

The above problem is that the input horizontal synchronization signal is supplied as is to the signal quality judgment circuit, but other input signals are prohibited except for the predetermined horizontal synchronization signal base part for the horizontal synchronization signal supplied to the clock recovery circuit. This problem is solved by the sampling clock supply circuit of the present invention, which is provided with protection means and means for inserting a pseudo horizontal synchronization signal when the horizontal synchronization signal is missing.

[Effect]

According to the present invention, when the horizontal synchronization signal input to the PLL circuit is lost, it is replenished, so the PLL circuit that generates the sampling clock synchronized with the horizontal synchronization signal is not disturbed and stabilized, and the image signal period is stabilized. If noise similar to the horizontal synchronization signal appears, the signal quality determination circuit has no protection circuit, so it can be detected and a sampling clock can be supplied from the asynchronous side.

〔Example〕

FIG. 1 is a block diagram showing the configuration of a video signal transmission device according to an embodiment of the present invention, and FIG. 2 is a time chart of waveforms of each part of the sampling clock supply circuit 20-1 shown in FIG. This corresponds to points a to f in Figure 1.

In the figure, 8-1 is a signal quality determination circuit, 12 is a protection and pseudo horizontal synchronization signal generation circuit, 13 is a differentiation circuit,
14 and 15 are AND circuits, 16 is a NAND circuit, 2
0-1 indicates a sampling clock supply circuit,
The same reference numerals throughout the drawings indicate the same functions.

The difference between FIG. 1 and FIG. 3 is the sampling clock supply circuit 20-1, and this portion will be explained below.

In the case of FIG. 1, the synchronizing signal shown in FIG. 2A detected by the synchronizing signal detection circuit 9 is differentiated by the differentiating circuit 13 and generates a pulse as shown in FIG. 2B. Enter.

Further, the NAND circuit 16 is provided with a protection period in which the protection and pseudo-horizontal synchronization signal generation circuit 12 blocks the vertical synchronization signal period as shown in FIG. Normally, from the output of the NAND circuit 16, a signal having pulses obtained by differentiating the horizontal synchronizing signal as shown in FIG. 2D is input to the signal quality determination circuit 8-1.

In addition, a protection signal is sent to the AND circuit 15 from the protection and pseudo-horizontal synchronization signal generation circuit 12 as shown in FIG. A signal is output and input to the PLL circuit 7.

If the horizontal synchronizing signal shown in A of FIG. 2A is missing, the protection and pseudo horizontal synchronizing signal generating circuit 12 recognizes this from the output of the AND circuit 14, and generates a pseudo horizontal synchronizing signal as shown in FIG. 2E. A horizontal synchronizing signal is generated and supplied to the PLL circuit 7.

This is because even when the horizontal synchronizing signal fluctuates and enters the protection period shown in FIG. 2F and is not output from the AND circuit 15, the pseudo horizontal synchronizing signal is similarly output.

Therefore, there is no disturbance in the output of the PLL circuit 7, and a stable sampling clock can be supplied.

If noise similar to the horizontal synchronization signal appears within the image signal period, the signal quality judgment circuit 8-1 recognizes this, switches the switch SW to the dotted line side, and switches on the asynchronous sampling clock from the frequency divider 6. Switch to the supply side.

Therefore, even if the horizontal synchronizing signal fluctuates or drops or noise similar to the horizontal synchronizing signal appears in the image signal, a high quality image can be reproduced.

〔Effect of the invention〕

As explained in detail above, according to the present invention, a stable sampling clock can be supplied even if the horizontal synchronization signal fluctuates or is dropped, and if noise close to the horizontal synchronization signal appears within the image signal period, the signal The quality judgment circuit recognizes this and switches to the side that supplies an asynchronous sampling clock, so even if the horizontal synchronization signal fluctuates or is missing, or noise similar to the horizontal synchronization signal appears in the image signal, it will still produce a high-quality signal. It has the effect of reproducing images.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a video signal transmission device according to an embodiment of the present invention, FIG. 2 is a time chart of waveforms of various parts of the sampling clock supply circuit 20-1 in FIG. 1, and FIG. 3 is a conventional circuit. 1 is a block diagram showing the configuration of an example video signal transmission device. FIG. In the figure, 1 is a clamp circuit, 2 is an A/D converter, 3 is a coder, 4 is a line interface, 5 is an oscillator, 6 is a frequency divider, 7 is a PLL circuit,
8, 8-1 is a signal quality determination circuit, 9 is a synchronization signal detection circuit, 10 is a vertical synchronization signal removal circuit, 11 is a protection circuit, 12 is a protection and pseudo horizontal synchronization signal generation circuit, 13 is a differentiation circuit, 14, 15 is an and circuit,
16 is a NAND circuit, SW is a switch, 20, 20
-1 indicates a sampling clock supply circuit.

Claims (1)

[Claims] 1. When supplying a sampling clock for converting a video signal from analog to digital,
A signal quality judgment circuit judges the quality of the horizontal synchronization signal extracted from the video signal, and depending on the judgment result, either a clock from a phase synchronization pull-in circuit synchronized with the horizontal synchronization signal is supplied, or an asynchronous clock from a fixed clock generator is supplied. In a sampling clock supply circuit that switches whether or not to supply a sampling clock, the input horizontal synchronization signal is supplied as is to the signal quality determination circuit, but the horizontal synchronization signal supplied to the clock regeneration circuit has a predetermined horizontal synchronization signal base part. A sampling clock supply circuit characterized in that it is provided with a protection means for inhibiting input signals as they are except for input signals, and a means for inserting a pseudo horizontal synchronization signal when a horizontal synchronization signal is missing.