JPH0447970Y2 - - Google Patents
Info
- Publication number
- JPH0447970Y2 JPH0447970Y2 JP1985127410U JP12741085U JPH0447970Y2 JP H0447970 Y2 JPH0447970 Y2 JP H0447970Y2 JP 1985127410 U JP1985127410 U JP 1985127410U JP 12741085 U JP12741085 U JP 12741085U JP H0447970 Y2 JPH0447970 Y2 JP H0447970Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- flat package
- board
- terminals
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
〔技術分野〕
本考案は、集積回路の外に任意の回路の構成さ
れている基板を接続してなる混成回路において、
その厚みを薄くするために好適な構造に関する。[Detailed description of the invention] [Technical field] The present invention relates to a hybrid circuit formed by connecting a substrate on which an arbitrary circuit is configured in addition to an integrated circuit.
The present invention relates to a structure suitable for reducing its thickness.
ほとんどの電子回路が集積回路化される現状に
おいて、インダクタンスを含む回路、例えばコイ
ルとコンデンサを組合せて構成される遅延線の回
路のように集積回路化が困難なものもあり、全体
の回路にこのような回路を含む場合には集積回路
の外部に接続する必要がある。TTL素子を用い
た飽和型論理回路に遅延線を組合せてバツフアー
ドデイレーラインを構成する場合もこのような例
に相当する。
In the current situation where most electronic circuits are integrated circuits, there are some circuits that include inductance, such as delay line circuits made up of a combination of coils and capacitors, which are difficult to integrate. If such a circuit is included, it must be connected to the outside of the integrated circuit. Such an example also corresponds to the case where a buffered delay line is constructed by combining a delay line with a saturation type logic circuit using TTL elements.
そして基板上にコイルやコンデンサを配置して
遅延線の回路を構成し、集積回路のフラツトパツ
ケージと重ね合わせ、フラツトパツケージの端子
を介して両方の回路を接続し、外部端子をデユア
ルインラインパツケージ(以下DIPという)の外
部に露呈させた混成回路は実開昭58−89953号公
報等により公知である。 Then, configure a delay line circuit by arranging coils and capacitors on the board, stacking it on the integrated circuit's flat package, connecting both circuits via the flat package's terminals, and connecting the external terminals to the dual in-line package. A hybrid circuit exposed to the outside (hereinafter referred to as DIP) is known from Japanese Utility Model Application Laid-Open No. 58-89953.
しかし従来の混成回路は第5図の説明図に示す
ように、コイル1やコンデンサ2がいずれも基板
上にあり、フラツトパツケージ4とは反対側に位
置する。又フラツトパツケージ4と基板の幅はほ
ぼ同じであり、両方の回路の接続は基板3の側辺
でフラツトパツケージ4の上側に屈曲させてある
端子5で行われる。又外部端子7の接続も基板3
の側辺、又はフラツトパツケージ4の側面に突出
している端子6によつて行われる。従つて基板3
の側辺近傍では、外部端子7と端子6、基板3と
外部端子7、基板3と端子5の夫々相互の接続を
行う必要があり、接続構造が錯雑しており、短絡
事故も生じ易い。又接続構造が錯雑しているフラ
ツトパツケージ4の側には、回路素子を配置しに
くいので、フラツトパツケージ4、基板3、遅延
線を構成する回路素子が同じ方向に順次重ね合わ
さることになり、1点鎖線で示してあるDIPの厚
みTを薄くすることが難しい。そして他の回路部
品と共に混成回路を別の回路基板に取付ける時
に、厚みTが他の回路部品に比較して厚くなり、
回路基板全体の薄形化を達成する上で望ましくな
い。 However, in the conventional hybrid circuit, as shown in the explanatory diagram of FIG. 5, the coil 1 and the capacitor 2 are both located on the substrate, on the opposite side from the flat package 4. Further, the widths of the flat package 4 and the board are approximately the same, and connection between both circuits is made by terminals 5 bent upwards of the flat package 4 on the sides of the board 3. Also, the external terminal 7 is connected to the board 3.
This is done by means of terminals 6 protruding from the sides of the flat package 4 or from the sides of the flat package 4. Therefore, the substrate 3
In the vicinity of the sides, it is necessary to connect the external terminals 7 and the terminals 6, the board 3 and the external terminals 7, and the board 3 and the terminals 5, respectively, and the connection structure is complicated and short-circuit accidents are likely to occur. Furthermore, since it is difficult to place circuit elements on the side of the flat package 4 where the connection structure is complicated, the circuit elements constituting the flat package 4, the board 3, and the delay line are stacked one after another in the same direction. , it is difficult to reduce the thickness T of the DIP, which is indicated by the dashed line. When the hybrid circuit is attached to another circuit board together with other circuit components, the thickness T becomes thicker than the other circuit components.
This is undesirable in terms of reducing the overall thickness of the circuit board.
本考案の目的は、外部端子とフラツトパツケー
ジの端子の接続を基板とは反対側のフラツトパツ
ケージの外面で行うことにより、端子間相互の接
続構造を簡潔にして薄形化を可能にする混成回路
の提供にある。
The object of this invention is to provide a hybrid circuit which enables a thinner design by simplifying the connection structure between the terminals by connecting the external terminals and the terminals of the flat package on the outer surface of the flat package opposite the substrate.
本考案はコイルを含む回路が構成されている基
板と、該基板より平面積の狭い集積回路のフラツ
トパツケージを重ね合わせてあり、両方の回路の
接続をフラツトパツケージの端子を介して行い、
少くともいずれかの回路に接続する外部端子をを
露呈させた状態で全体を樹脂封止してある混成回
路であり、集積回路に接続する外部端子はその先
端を、フラツトパツケージの外面に沿つて折り曲
げられ基板と反対側の外面に延在する該フラツト
パツケージの端子に、該基板と反対側の外面で接
続されていることを特徴とする。
In the present invention, a board on which a circuit including a coil is configured and a flat package of an integrated circuit having a smaller plane area than the board are superimposed, and both circuits are connected through terminals of the flat package.
It is a hybrid circuit that is entirely sealed in resin with at least one of the external terminals connected to the integrated circuit exposed, and the tip of the external terminal connected to the integrated circuit is placed along the outer surface of the flat package. The terminal of the flat package is bent and extends to the outer surface opposite to the substrate, and is connected to the terminal of the flat package on the outer surface opposite to the substrate.
以下第4図のバツフアードデイレーラインの回
路図を例にとり、本考案の混成回路の実施例を示
す第1図乃至第3図を参照しながら説明する。
Taking the circuit diagram of a buffered delay line shown in FIG. 4 as an example, an explanation will be given below with reference to FIGS. 1 to 3 showing embodiments of the hybrid circuit of the present invention.
第1図は組立説明図、第2図は分解斜視図、第
3図aと第3図bは外部端子とフラツトパツケー
ジの端子の接続部分の平面図である。 FIG. 1 is an explanatory view of assembly, FIG. 2 is an exploded perspective view, and FIGS. 3a and 3b are plan views of the connection portion between the external terminal and the terminal of the flat package.
第4図において、10はTTL素子、11は入
力端子、12はアース端子、13から17までは
出力端子、18は電源端子、19はコイル、20
はコンデンサ、21は抵抗である。そして6個の
TTL素子10が第1図、第2図の集積回路のフ
ラツトパツケージ30内に構成され、点線で囲ま
れた部分の遅延線は基板31に構成されている。 In Figure 4, 10 is a TTL element, 11 is an input terminal, 12 is a ground terminal, 13 to 17 are output terminals, 18 is a power supply terminal, 19 is a coil, 20
is a capacitor, and 21 is a resistor. and six
The TTL element 10 is constructed in a flat package 30 of the integrated circuit shown in FIGS.
基板31にはその面を貫通する孔32、孔34
を設けてあり、側辺には溝33を設けてある。孔
34と溝33に下側からフラツトパツケージ30
の上側に曲げてある端子35を嵌め込むことによ
り、基板31とフラツトパツケージ30が重ね合
わされる。基板31は主にその幅をフラツトパツ
ケージ30の幅Wよりも広げることにより、フラ
ツトパツケージ30の平面積よりも広くしてあ
る。孔32はコイル19を嵌め込むためのもので
あり、ドラムコアに巻線を行つてあるコイル19
を立設する場合を考慮して、ドラムコアの鍔とほ
ぼ同じ大きさの円形にしてある。そして孔32は
基板31とフラツトパツケージ30の重ならない
位置にあり、下側から孔32に嵌め込まれたコイ
ル19は第1図のようにフラツトパツケージ30
の横の位置にある。コイル19は基板31の上側
から孔32の底を塞ぐ接着テープ41の接着面に
固定される。 The substrate 31 has holes 32 and 34 penetrating its surface.
are provided, and grooves 33 are provided on the sides. Insert the flat package 30 into the hole 34 and groove 33 from below.
By fitting the terminals 35 bent upward, the board 31 and the flat package 30 are overlapped. The substrate 31 is made wider than the plane area of the flat package 30 mainly by making its width wider than the width W of the flat package 30. The hole 32 is for fitting the coil 19, and the coil 19 is wound around the drum core.
In consideration of the case where the drum core is installed upright, it is made into a circular shape that is approximately the same size as the tsuba of the drum core. The hole 32 is located at a position where the substrate 31 and the flat package 30 do not overlap, and the coil 19 fitted into the hole 32 from below is inserted into the flat package 30 as shown in FIG.
located next to. The coil 19 is fixed from the upper side of the substrate 31 to the adhesive surface of an adhesive tape 41 that closes the bottom of the hole 32.
なお第2図の基板31には、第4図の点線内に
対応する回路素子を取付ける様子を図示してある
が、それらの回路素子間の接続や、集積回路と基
板31の回路を接続するために孔34や溝33の
周辺に形成してある導体パターンは図示を省略し
てある。 Note that the board 31 in FIG. 2 is illustrated with circuit elements corresponding to the dotted lines in FIG. For this reason, the conductor patterns formed around the holes 34 and grooves 33 are not shown.
フラツトパツケージ30は、対向する両側辺に
夫々7個ずつの端子を露呈している14ピンタイ
プのものであるが、基板31の回路と接続するた
めに上側に曲げてある端子35以外の端子36
は、その外面に沿つて折り曲げられ基板31と反
対側の外面42まで延在する。そして外面42で
端子36は外部端子37に接続する。外部端子3
7の先端は第2図に図示されているように2つに
割れたものと、細長くしてあるものの2種類ある
が、外面42で第3図aのように端子36を先端
38で挟んだり、第3図bのように細長い先端3
9を端子36に添わせて半田付けしてその面を広
くして半田付の信頼性を得る。先端39の細長い
形状は、フラツトパツケージ30の端子が第2図
で図示してある部分のように1個おきに上下に曲
げられるのではなく、連続して下側に曲げられる
端子36がある場合、外部端子37が近接して生
ずる先端における短絡事故を防ぐ役割をする。 The flat package 30 is of a 14-pin type with seven terminals exposed on each side of the opposite side, except for the terminal 35 which is bent upward for connection to the circuit on the board 31. 36
is bent along its outer surface and extends to the outer surface 42 on the opposite side from the substrate 31. Terminal 36 then connects to external terminal 37 on outer surface 42 . External terminal 3
There are two types of tip 7: one that is split into two as shown in Figure 2, and one that is elongated. , the elongated tip 3 as shown in Figure 3b.
9 is soldered along with the terminal 36 to widen its surface to obtain soldering reliability. The elongated shape of the tip 39 allows the terminals 36 of the flat package 30 to be bent downward continuously, rather than being bent up and down every other terminal as shown in FIG. In this case, the external terminal 37 serves to prevent a short-circuit accident at the tip that occurs when the external terminal 37 is close to each other.
上側に曲げてある端子35は孔34と溝33の
周辺の導体パターンに半田付けされる。6個の端
子35は、第4図における13から17までの5
個の出力端子に接続するTTL素子10の入力側
の端子と、入力端子11に接続するTTL素子1
0の出力側の端子に夫々対応する。又下側に折り
曲げられている8個の端子36は、13から17
までの出力端子、入力端子11、電源端子18、
アース端子12に夫々対応する。そして全体が第
1図で1点鎖線で示すように樹脂封止され、DIP
の外側に外部端子37によつて内部の回路が引き
出される。 The upwardly bent terminal 35 is soldered to the conductor pattern around the hole 34 and groove 33. The six terminals 35 are numbered 5 from 13 to 17 in FIG.
The input side terminal of TTL element 10 connected to the output terminal of , and the TTL element 1 connected to input terminal 11
They correspond to the output side terminals of 0, respectively. Also, the eight terminals 36 bent downward are 13 to 17.
Output terminal up to, input terminal 11, power terminal 18,
They correspond to the ground terminals 12, respectively. The whole is then sealed with resin as shown by the dashed line in Figure 1, and DIP
The internal circuit is drawn out to the outside by an external terminal 37.
外部端子37はDIPの外面に沿つて折り曲げら
れて底面40まで延在しており、他の回路部品と
共に別の回路基板に取付ける時にその導体パータ
ンに直接面接続できるようにしてある。 The external terminal 37 is bent along the outer surface of the DIP and extends to the bottom surface 40, so that when it is attached to another circuit board together with other circuit components, it can be connected directly to the conductor pattern of the other circuit board.
なお実施例において、外部端子37はいずれも
フラツトパツケージ30の端子36に接続してい
るが、基板31の側辺から1部の外部端子を引き
出すことも設計変更によつて可能であり、その場
合基板31の対向する側辺に溝33を設けるとよ
い。又外部端子37を片側から引き出すようにし
て、DIP以外に用いることもできる。フラツトパ
ツケージ30と基板31の上下関係は逆であつて
もよい。 In the embodiment, all of the external terminals 37 are connected to the terminals 36 of the flat package 30, but it is also possible to pull out some of the external terminals from the sides of the board 31 by changing the design. In this case, grooves 33 may be provided on opposite sides of the substrate 31. Moreover, the external terminal 37 can be pulled out from one side and used for purposes other than DIP. The vertical relationship between the flat package 30 and the substrate 31 may be reversed.
以上述べたように本考案の混成回路は、フラツ
トパツケージと基板を重ね合わせて構成される
が、外部端子とフラツトパツケージの端子の接続
を基板とは反対側のフラツトパツケージの外面で
行うようにしてあり、他の端子の接続位置とは分
けてある。従つて全体の端子間相互の接続構造が
簡潔になり、基板の側辺近傍での短絡事故が防が
れる。又接続構造が簡潔化されると共に、外部端
子を接続位置から水平に引き出す場合に外部端子
と平面積を広くしてある基板間にはフラツトパツ
ケージの厚みだけ間隔が生じ、その間に基板の回
路を構成する回路素子を配置することができる。
そしてフラツトパツケージと同じ側に回路素子を
配置して反対側の回路素子を少くすることによ
り、混成回路の厚みを薄くすることができる。
As mentioned above, the hybrid circuit of the present invention is constructed by overlapping a flat package and a board, but the connection between the external terminal and the terminal of the flat package is made on the outer surface of the flat package on the opposite side from the board. It is separated from the connection position of other terminals. Therefore, the overall connection structure between the terminals becomes simple, and short-circuit accidents near the sides of the board can be prevented. In addition, the connection structure is simplified, and when the external terminal is pulled out horizontally from the connection position, a gap equal to the thickness of the flat package is created between the external terminal and the board with a wide planar area, and the circuit board's circuit is The circuit elements constituting the can be arranged.
By arranging circuit elements on the same side as the flat package and reducing the number of circuit elements on the opposite side, the thickness of the hybrid circuit can be reduced.
第1図は本考案の混成回路の実施例を示す組立
説明図、第2図は分解斜視図、第3図aと第3図
bは外部端子とフラツトパツケージの端子の接続
部分を示す平面図、第4図はバツフアードデイレ
ーラインの回路図、第5図は従来の混成回路の説
明図である。
30……フラツトパツケージ、31……基板、
32,34……孔、33……溝、35,36……
端子、37……外部端子、38,39……先端、
40……底面。
Fig. 1 is an explanatory assembly diagram showing an embodiment of the hybrid circuit of the present invention, Fig. 2 is an exploded perspective view, and Figs. 3a and 3b are plan views showing the connection portion between the external terminal and the terminal of the flat package. 4 are circuit diagrams of a buffered delay line, and FIG. 5 is an explanatory diagram of a conventional hybrid circuit. 30... Flat package, 31... Board,
32, 34... hole, 33... groove, 35, 36...
Terminal, 37...External terminal, 38, 39...Tip,
40...Bottom surface.
Claims (1)
基板より平面積の狭い集積回路のフラツトパツケ
ージを重ね合わせてあり、両方の回路の接続をフ
ラツトパツケージの端子を介して行い、少くとも
いずれかの回路に接続する外部端子をを露呈させ
た状態で全体を樹脂封止してある混成回路であ
り、前記両方の回路の接続は、基板の側辺と、重
なり合わない位置の基板面を貫通して設けてある
孔に嵌め込んだフラツトパツケージの端子を介し
て行われ、該フラツトパツケージの横の位置には
該基板の回路を構成する回路素子が固定してあ
り、集積回路に接続する外部端子はその先端が、
フラツトパツケージの外面に沿つて折り曲げられ
基板と反対側の外面に延在する該フラツトパツケ
ージの端子に、該基板と反対側の外面で接続され
ていることを特徴とする混成回路。 A board on which a circuit including a coil is configured and a flat package of an integrated circuit having a narrower surface area than the board are stacked on top of each other, and connections between both circuits are made through terminals of the flat package, and at least one It is a hybrid circuit in which the entire circuit is sealed in resin with the external terminals connected to the circuit exposed, and the connections between the two circuits are made by connecting the sides of the board and the board surface at positions that do not overlap. This is done through the terminals of a flat package fitted into holes provided through the board, and the circuit elements constituting the circuit of the board are fixed to the side of the flat package. The tip of the external terminal to be connected is
A hybrid circuit characterized in that the hybrid circuit is connected to a terminal of the flat package which is bent along the outer surface of the flat package and extends to the outer surface opposite to the substrate, at the outer surface opposite to the substrate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985127410U JPH0447970Y2 (en) | 1985-08-21 | 1985-08-21 | |
| US06/893,141 US4722027A (en) | 1985-08-09 | 1986-08-05 | Hybrid circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985127410U JPH0447970Y2 (en) | 1985-08-21 | 1985-08-21 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6236554U JPS6236554U (en) | 1987-03-04 |
| JPH0447970Y2 true JPH0447970Y2 (en) | 1992-11-12 |
Family
ID=31022134
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985127410U Expired JPH0447970Y2 (en) | 1985-08-09 | 1985-08-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0447970Y2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5780836U (en) * | 1980-10-31 | 1982-05-19 |
-
1985
- 1985-08-21 JP JP1985127410U patent/JPH0447970Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6236554U (en) | 1987-03-04 |
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