JPH0448398B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display device that displays characters including characters using a cathode ray tube (hereinafter referred to as CRT).

[Conventional technology]

Conventionally, in order to be able to change the horizontal magnification and vertical magnification of displayed characters, some display devices of this type have used, for example, a large number of character generators corresponding to each magnification. In addition, as devices that do not use a large number of character generators, there is a character display device described in JP-A-53-13838,
There is a character display device described in 120538. However, in the former case, display character data (corresponding to a character code) and control data (corresponding to a control code) must be stored separately in a storage device. Furthermore, the latter method extracts codes that are not assigned as character codes from among certain codes and uses them as control codes, and the range of control code settings is limited.

[Problem to be solved by the invention]

The above-mentioned conventional methods each have the following drawbacks.

1. Using a large number of character generators increases the cost and complicates the circuit.

2. The method described in Japanese Unexamined Patent Publication No. 13838/1983 requires careful attention to classifying each data area within the storage device, which is complicated. Furthermore, it is necessary to add a "display format conversion bit" to the display character data to specify the timing to change the display format, and the "display format conversion bit" may be added to any display character data. , the memory configuration of the storage device for display character data must be changed, and the memory capacity must also be increased.

3. The method described in JP-A-54-120538 has a limit to the range of forced code setting, and as the number of required character codes increases, the limit becomes even narrower.

In view of the above drawbacks, the present invention provides a display device that does not require an increase in the number of character generators, does not need to be concerned about dividing data areas, and is capable of setting control codes within a range comparable to the entire code, regardless of the character code. The purpose is to provide a control method for

[Means to solve the problem]

The display control method of the display device of the present invention includes:
A display that can output a general-purpose attribute signal indicating that data at the control data position has been accessed when data at a position specified as a control data position is accessed among data written in the memory and including character data. controller and CPU
and a character generator which inputs a character code outputted via the display controller and outputs a corresponding dot pattern. The first step is to write control data that instructs the content of the change immediately before the character data, and to specify the written position as the control data position.
When the control data location in the memory is accessed after the first step and a general-purpose attribute signal is output, the data at the accessed control data location is input as control data from the display controller and held in a register. a second step of outputting a blank code from the suppression circuit to the character generator in place of the output control data; and sequentially outputting the control data held in the register via the display controller. a third step of inputting the character data to the character generator, and controlling the output state of the dot pattern via the dot pattern output control circuit using the control data held in the register to set the display state; and has.

[Effect]

When the general-purpose attribute signal is output, it is recognized that the output of the display controller is a control code, and according to the change content indicated by the control code output from the display controller, the control code is outputted following the control code. The display state of characters corresponding to one or more consecutive character codes is changed and displayed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a display circuit to which the display control method for a display device of the present invention is applied; FIGS. 2 and 3 are explanatory diagrams showing the operation of the embodiment of FIG. 1; 4, 5, 8, and 8 are time charts showing the operation of the embodiment shown in FIG. 1, respectively, and FIG. 9 is an explanatory diagram showing the operation of the embodiment shown in FIG.

The CRT 1 is a raster scan type display device, and for example, as shown in FIG. 2, the raster of the CRT 1 is sequentially scanned using the scanning line SL based on the video signal VDS, so that, for example, display characters "A" and "B" are displayed. ,
Display “C” etc. The horizontal chain line in FIG. 2 is a horizontal retrace line HL that returns the scanning line SL to its original position in the horizontal direction, and is not displayed on the CRT 1. The horizontal retrace line HL is controlled by the horizontal retrace signal hrs shown in FIG. Furthermore, the slightly vertical chain line in FIG. 2 is a vertical retrace line VL that returns the scanning line SL to its original vertical position, and is not displayed on the CRT 1. The vertical retrace line VL is controlled by the vertical retrace signal vrs shown in FIG. Furthermore,
As is clear from FIG. 2, for example, one character is displayed in a matrix configuration of 8 dots horizontally and 12 dots vertically, a total of 96 dots. The pulse generator 2 is
As shown in FIG. 4, a clock pulse DOTCK is generated that defines one dot period of a displayed character, for example, periods T ₀ , T ₁ , .about.T ₇ . Counter 3 inputs and counts the clock pulse DOTCK to determine the display period of one character, that is, the horizontal 8-bit period _T0 to _T7.
A first timing signal t ₆ indicating the period T ₆ of the seventh bit of the horizontal 8-bit period T ₀ to _{T 7} ,
Also, a second timing signal t7 indicating the 8th bit period _T7 of the horizontal 8-bit period _{T0 to T7} is output (not shown in FIG. 4). The character generator 4 usually uses a ROM, and as shown in FIG. 4, it receives an 8-bit parallel character code signal CC'
and 4-bit parallel line count signal LC'
are input, and the character data at the address designated by these signals, that is, the 8-bit parallel dot pattern signal dtp, is output as shown in FIG. Specifically, based on Figure 2,
The character generator 4 specifies, for example, the start address where the data of character "A" is stored with the character code signal CC', and then specifies the start address where the data of character "A" is stored, for example, with the line count signal LC'. Line number LN0, LN1～
Line number LN0 of LN11 is designated, and dot data "00011000" at this address is output as an 8-bit parallel dot pattern signal dtp (see FIG. 5).

The parallel/serial converter 5 comprises a shift register or the like, inputs and converts the parallel dot pattern signal dtp from the character generator 4, and outputs the serial dot pattern signal dtp/s as shown in FIG. This series dot pattern signal dtp/s is
Via the driver 6, it becomes a video signal vds that instructs the scanning line SL of the CRT 1 to blink. In addition, parallel/
The serial converter 5 loads the parallel dot pattern signal dtp with the timing signal _t7 ', as shown in FIG. 5, and performs bit shifting with the aforementioned dot clock DOTCK. The CRT controller 7 is composed of a high-density integrated circuit LSI, etc., and exchanges various signals with a CPU, which is a signal processing circuit including memory, processes these signals, and controls the CRT1.
Outputs various signals for use. That is, the CRT controller 7 inputs data from a signal processing circuit such as the CPU, and also receives a driving character clock signal CCLK from the counter 3 that defines the display period T ₀ to _{T 7} of one character. It outputs an 8-bit parallel character code signal CC, a 4-bit parallel line count signal LC, and a control signal GPA called a general-purpose attribute signal, which is an attribute signal output regarding the attribute of the output CC of the CRT controller.

Here, storage of display data in a memory (not shown) will be explained. First, in normal 1x mode,
For example, as shown in Figure 9, 1 is placed at address 1 in memory.
Display data is stored.

Next, the case of horizontal enlargement is shown in FIG. 92. Place a special control code specifying the horizontal magnification signal MH immediately before the character to be enlarged.

The case of vertical enlargement is shown in FIG. 9. What must be noted here is that the first of the special control codes specifying a set of vertical magnifications MV (for example, "0" shown in the first column from the left and second from the top in Figure 9) The clear signal LCCLR must be set to 1 in the double-hatched area directly below the . This is for resetting an external line counter 19 which will be described later.
Then, the display state of the character code stored in the memory following the set of special control codes is changed according to the contents of the set of special control codes (hereinafter, an example of changing to portrait is used). ), displayed on CRT1.

Also, although not shown, it is of course possible to expand both horizontally and vertically by the combination of 2 and 3 in FIG.

On the other hand, the CRT controller 7, as shown in FIG.
Horizontal retrace signals corresponding to the horizontal retrace signal hrs and vertical retrace signal vrs for CRT1, respectively.
Outputs HRT and vertical retrace signal VRT, respectively.

In addition, the 4-bit parallel line count signal LC
is the horizontal retrace signal HRT in the CRT controller 7.
is obtained by counting. In this case, as shown in Figures 2 and 4, the scanning line SL is line number LN0, LN1 of 12.
~The count of the scanning line SL, that is, the horizontal retrace signal HRT, is repeated every 12 to correspond to LN11, and the count value is the character clock signal.
It is output to the outside of the CRT controller 7 by CCLK.

Also, 8-bit parallel character code signal
As shown in FIG. 6, CC includes original character code signals CC1, CC2, CC3 and a display control code signal DP mixed in advance between these character code signals CC1, CC2, CC3. . The contents of this display control code signal DP include, for example, a horizontal magnification MH, a vertical magnification signal MV, and a clear signal LCCLR, a selection signal MPX, etc., as shown in the letter B shown in FIG. .

Incidentally, the display control code signal may be mixed into the character code signal by making it, for example, with punch tape and feeding it into the CRT controller 7 at high speed.

Furthermore, the CRT controller 7, as shown in FIG.
Generic attribute signal corresponding to display control code signal DP
Output GPA as timing signal GPA. The suppression circuit 11 that suppresses the character code includes a sixth
Input the character code signal CC as shown in the figure,
When the timing signal GPA is being output, the display control code signal DP is replaced with a blank code and output as a character code signal CC'.
AND gate 12 has two timing signals GPA,
t ₇ is input, and a timing signal t ₇ '' is output (see FIG. 6).

The latch circuit 13 inputs the character code signal CC and holds and outputs the display control code signal DP at the timing signal _t7 '' as shown in FIG.
The latch circuit 14 inputs the display control code signal DP and holds and outputs each of the contents of the display control code signal DP at the timing signal _t6 as shown in FIG. That is, it outputs a horizontal magnification signal MH, a vertical magnification signal MV, and a clear signal LCCLR selection signal MPX, respectively. and gate 15
inputs the clock pulse DOTCK and the second timing signal _t7 , respectively, and outputs the clock signal _t7.
''' is output as shown in Figure 7.

The horizontal magnification counter 16 receives the clock signal t ₇ ''' as well as the horizontal magnification signal MH, and thins out the clock signal t ₇ ''' according to the contents of the magnification signal MH. and outputs the load signal _t7 °. For example, as shown in Figure 3, 2
In case of double character enlargement, as shown in FIG. ₇ , one row load signal t7' is output for every two clock signals _t7 '''. and gate 17
inputs the load signal t ₇ ° and the second timing signal t ₇ , and outputs the load timing signal t ₇ to the parallel/serial converter 5 as shown in FIG.
' is output. Counter 18 for horizontal magnification
inputs the clock pulse DOTCK and
A horizontal magnification signal MH is input, the clock pulse DOTCK is thinned out according to the content of this magnification signal MH, and an inhibition signal INH is output. For example, when enlarging the area twice as shown in Figure 3, the 7th
As shown in the figure, this inhibition signal INH is sent to the parallel/serial converter 5 for every two clock pulses DOTCK.
Output to. Note that this inhibition signal INH is
Clock pulse input to serial converter 5
Used to thin out DOTCK. As a result,
Clock pulse in parallel/serial converter 5
DOTCK' is thinned out and becomes as shown in FIG.
The counter 19 is used to specify line numbers LN0 to LN11 of displayed characters when expanding in the vertical direction. In other words, the special control code is
When MPX=1, the line number of the displayed character is specified instead of the line counter (not shown) in the CRT controller 7. This counter is
The horizontal retrace signal HRT for the CRT1 and the vertical magnification signal MV are input, and each time HRT inputs the number of MV values, it counts up. As shown in FIG. For example, as shown in FIG. 3, if the displayed characters are to be enlarged twice in the vertical direction, the count is increased every time HRT is input twice. That is, the same display is made on the CRT 1 every two scanning lines, and the display is enlarged twice in the vertical direction. The multiplexer 20 normally receives the 4-bit parallel line count signal LC from the CRT controller 7 and outputs it as the line count signal LC' of the character generator 4; signal mpx
When =1 is input, a 4-bit parallel line count signal LC'' from the line counter 19 is input and outputted to the character generator 4 as a line count signal LC'. If the line counter 19 is left alone, it will only count up based on the MV value and HRT input. A pulse for resetting this to 0 at an appropriate timing is obtained by the reset pulse generator 21. As shown in FIG. 8, the line count signal LC from the CRT controller 7 is 0, that is, the scanning line is at the position LN0 in the 1x mode, and GPA・t ₇ =1 (in this case (a special control code for specifying the vertical magnification is output) and the reset pulse clp is generated under the condition that LCCLR=1.

As mentioned in the storage of display data memory, this reset pulse is used to set LCCLR = 1 in the first special control code of the memory area with the same vertical magnification (excluding 1x).
reset to 0 prior to the first scan of the

As a result, the output of the line counter 19 becomes a line count signal LC'' in which the count of the horizontal retrace signal HRT is thinned out, and is inputted to the character generator 4 via the multiplexer 20, for example, as shown in FIG. Like line numbers LN0' and LN1', the upper line number LN0' and the lower line number LN1' repeat the same dot pattern.

As is clear from this example, only one character generator is used, and the added circuit is simple, compared to the conventional system that uses multiple character generators. It is structured as follows. In addition, in this embodiment, AND circuits 12, 15, 17, counter 1
6, 18, a line counter 19, a multiplexer 20, and a reset pulse generator 21 constitute a dot pattern output control circuit that controls the output state of the dot pattern.

Furthermore, since the horizontal magnification and vertical magnification can be set individually, there is an advantage that the magnification can be set for each character in the horizontal direction and for each line in the vertical direction.

The content of the display control code signal DP in Figure 6 may be changed to, for example, use blank spaces in the 8-bit parallel data to control the color, brightness, or reduction of displayed characters. Of course, it can be controlled.

〔Effect of the invention〕

The display control method of the present invention as described above mixes a control code for display control into a character code for display, instructs the output of the control code using a general-purpose attribute signal, and performs the instructed control code for display control. With the code,
By processing the character code for display above and displaying it on the display device,
Display equipment, especially for displaying characters
When applied to a CRT display device, any code can be set as a control code without considering data area divisions or character codes, and the control contents of the dot pattern output control circuit set corresponding to the control code can be changed. can be changed by changing the contents of the control code, which has the effect of allowing highly flexible control.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a display circuit to which the display control method for a display device of the present invention is applied; FIGS. 2 and 3 are explanatory diagrams showing the operation of the embodiment of FIG. 1; Figure 4, Figure 5, Figure 6, Figure 7
8 are time charts showing the operation of the embodiment of FIG. 1, and FIG. 9 is an explanatory diagram showing the operation of the embodiment of FIG. 1. 1...CRT, 2...Pulse generator, 3...Counter, 4...Character generator, 5...
Parallel/serial converter, 6...driver, 7...
CRT controller, 11... Suppression circuit, 12,
15, 17...AND circuit, 13, 14...Latch, 16, 18...Counter, 19...Line counter, 20...Multiplexer, CC, CC'...
...Character code signal, LC, LC', LC''...
Line count signal, DP...display control code signal.

Claims (1)

[Claims] 1. When data at a position specified as a control data position is accessed among data written in the memory and including character data, it is indicated that the data at the control data position has been accessed. a display controller that can output general-purpose attribute signals;
In a display device comprising a character generator which inputs a character code outputted by a CPU via the display controller and outputs a corresponding dot pattern, the memory Write control data that instructs the content of the change immediately before the character data, and specify the written position as the control data position.
When the control data location in the memory is accessed after the first step and a general-purpose attribute signal is output, the data at the accessed control data location is input as control data from the display controller and held in a register. a second step of outputting a blank code from the suppression circuit to the character generator in place of the output control data; and sequentially outputting the control data held in the register via the display controller. a third step of inputting the character data to the character generator, and controlling the output state of the dot pattern via the dot pattern output control circuit using the control data held in the register to set the display state; A display control method for a display device, comprising: