JPH0448726U - - Google Patents
Info
- Publication number
- JPH0448726U JPH0448726U JP9063590U JP9063590U JPH0448726U JP H0448726 U JPH0448726 U JP H0448726U JP 9063590 U JP9063590 U JP 9063590U JP 9063590 U JP9063590 U JP 9063590U JP H0448726 U JPH0448726 U JP H0448726U
- Authority
- JP
- Japan
- Prior art keywords
- current
- switch means
- power
- terminal
- cmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Description
第１図は、本考案のＣＭＯＳ型ＩＣをラツチア
ツプより保護する回路の基本構成を示すブロツク
図。第２図は、ＣＭＯＳ型マイクロコンピユータ
を保護するための本考案に基づく回路を示す図。
第３図は、第３図の回路における動作を示すタイ
ムチヤート。
図において、１……スイツチ手段、２……電流
検出手段、３……遅延制御手段、４……ＣＭＯＳ
型ＩＣ、５……電源。
FIG. 1 is a block diagram showing the basic configuration of a circuit that protects a CMOS type IC of the present invention from latch-up. FIG. 2 shows a circuit according to the invention for protecting a CMOS microcomputer.
FIG. 3 is a time chart showing the operation of the circuit of FIG. In the figure, 1... switch means, 2... current detection means, 3... delay control means, 4... CMOS
Type IC, 5...Power supply.
Claims (1)
電流を供給する電源５との間に設けられたスイツ
チ手段１、 該電源端子に供給される、電流量を検出し電流
量が所定値以上の時に、過大電流信号を発生する
電流検出手段２、及び 該過大電流信号の発生直後に、該スイツチ手段
１を開放して該電源端子への電流の供給を停止し
、一定時間後再びスイツチ手段１を閉じて該電源
端子への電流の供給を再開させる遅延制御手段３
を備え、ＣＭＯＳ型ＩＣをラツチアツプによる過
大電流から保護するようにしたＣＭＯＳ型ＩＣの
保護回路。[Claims for Utility Model Registration] Switch means 1 provided between a power terminal of a CMOS IC 4 and a power source 5 that supplies current to the power terminal; current detection means 2 that generates an overcurrent signal when the amount of current is greater than a predetermined value; and immediately after the generation of the overcurrent signal, the switch means 1 is opened to stop the supply of current to the power supply terminal; delay control means 3 for closing the switch means 1 again after a certain period of time and restarting the supply of current to the power supply terminal;
A protection circuit for CMOS ICs that protects CMOS ICs from excessive current caused by latch-up.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9063590U JPH0448726U (en) | 1990-08-31 | 1990-08-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9063590U JPH0448726U (en) | 1990-08-31 | 1990-08-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0448726U true JPH0448726U (en) | 1992-04-24 |
Family
ID=31825563
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9063590U Pending JPH0448726U (en) | 1990-08-31 | 1990-08-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0448726U (en) |
-
1990
- 1990-08-31 JP JP9063590U patent/JPH0448726U/ja active Pending
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