JPH0448740U - - Google Patents
Info
- Publication number
- JPH0448740U JPH0448740U JP9148490U JP9148490U JPH0448740U JP H0448740 U JPH0448740 U JP H0448740U JP 9148490 U JP9148490 U JP 9148490U JP 9148490 U JP9148490 U JP 9148490U JP H0448740 U JPH0448740 U JP H0448740U
- Authority
- JP
- Japan
- Prior art keywords
- alarm
- bit
- output
- alarm signal
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000926 separation method Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Landscapes
- Dc Digital Transmission (AREA)
- Selective Calling Equipment (AREA)
Description
第１図は、本考案の一実施例を示す回路図、第
２図は、アラーム収集方式の一例を示す図である
。
１１〜１７……Ｒ−Ｓフリツプフロツプ、２…
…ＯＲゲート、３１〜３７……書き込み判断ゲー
ト、４１〜４７……ＯＲゲート。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing an example of an alarm collection method. 1 1 to 1 7 ...R-S flip-flop, 2...
...OR gate, 3 1 to 3 7 ... write judgment gate, 4 1 to 4 7 ... OR gate.
Claims (1)
トのアラーム信号を入力とし、出力をアラーム収
集回路へ送るアラーム収集装置であつて、 前記アラーム信号を保持する保持部と、 前記アラーム信号の論理和の演算を行う演算部
と、 前記演算部の出力に基づいて、前記保持部への
書き込みを判断する判断部とを有することを特徴
とするアラーム収集装置。 (2) 中継装置アラーム分離回路からの８ビツト
のアラーム信号を入力とし、８ビツトの出力をア
ラーム収集回路へ送るアラーム収集装置であつて
、 前記８ビツトのアラーム信号を保持するセツト
−リセツトフリツプフロツプと、 前記８ビツトのアラーム信号の論理和の演算を
行うオアゲートと、 前記オアゲートの出力でセツト−リセツトフリ
ツプフロツプへの書き込みを判断するゲートとを
有することを特徴とするアラーム収集装置。[Claims for Utility Model Registration] (1) An alarm collection device that receives a predetermined bit of alarm signal from a repeater alarm separation circuit as input and sends an output to an alarm collection circuit, comprising: a holding section that holds the alarm signal; An alarm collection device comprising: a calculation unit that performs a logical OR calculation of the alarm signals; and a determination unit that determines writing to the holding unit based on an output of the calculation unit. (2) An alarm collection device that receives an 8-bit alarm signal from a repeater alarm separation circuit and sends an 8-bit output to an alarm collection circuit, the set-reset flip-flop holding the 8-bit alarm signal. an OR gate that performs a logical sum operation on the 8-bit alarm signal; and a gate that determines writing to a set-reset flip-flop based on the output of the OR gate. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9148490U JPH0448740U (en) | 1990-08-30 | 1990-08-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9148490U JPH0448740U (en) | 1990-08-30 | 1990-08-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0448740U true JPH0448740U (en) | 1992-04-24 |
Family
ID=31827160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9148490U Pending JPH0448740U (en) | 1990-08-30 | 1990-08-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0448740U (en) |
-
1990
- 1990-08-30 JP JP9148490U patent/JPH0448740U/ja active Pending
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