JPH0449431A - Interface circuit with testing function - Google Patents

Abstract

PURPOSE:To confirm the normality of all bits on a data bus by providing the interface circuit with a response means for returning data to be inverted by a previously determined length for a test command and a response checking means for deciding whether data received after transmitting the test command are data inverted by a previously determined length or not. CONSTITUTION:When the transmission of a previously reserved test command is executed through a master device interface means 1, the response confirming means 6 is started and the means 6 monitors whether previously reserved 2-byte inverted data to be sent from a peripheral device after receiving the test command are sent or not. At the time of confirming that the inverted data are sent in correct order, the means 6 can confirm the correct connection of the master device interface to a peripheral device interface 2 through a data exchanging data bus line 3, a data control line 4 and a data discriminating signal line 5 and returns an answer to the means 8. Consequently, the normality of all bits in the data line between both the interface means 1, 2 can be confirmed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an interface circuit with a test function,
In particular, the present invention relates to an interface circuit with a test function that controls peripheral devices and is used for peripheral input/output.

[Conventional technology]

Conventionally, in this type of peripheral I10 interface circuit, when the transmitted and received data has a variable length, a parity line is provided separately from the data bus line, and on the transmitting side, the odd or even parity of the transmitted data on the data bus is placed on the parity line. The receiving side checks whether the received data is correct using the received parity data.

[Problem to be solved by the invention]

The above-mentioned conventional interface circuit having a parity line has a drawback in that a bit error on the data bus due to incorrect wiring of the data signal line cannot be detected from the data and parity received on the receiving side.

[Means to solve the problem]

The interface circuit with a test function of the present invention includes a bidirectional data bus line, a data identification signal line that indicates whether data present on the data bus line is a command or data, and a data identification signal line that indicates whether the data present on the data bus line is a command or data. interface means comprising a data control line for controlling transmission and reception; command identification means for determining whether a command received by the interface means is a test command for a previously reserved interface; a response means for replying with data to be inverted at the same time;
and response confirmation means for determining whether data received after transmitting the test command is data inverted with a predetermined length.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

Referring to FIG. 1, one embodiment of the present invention includes a host device interface means 1, a peripheral device interface means 2, a data bus line 3, a data control line 4, a data identification signal line 5, and a response confirmation means. 6, command identification means 7,
Response means 8, data 1jtlO1, and command line 10
2, response activation line 103, and response line 104
It is composed of.

The host device interface means 1 and the peripheral device interface means 2 are connected by a data bus line 3, a data control line 4, and a data identification signal line 5. The response confirmation means 6 is connected to the host device interface means 1 via a data line 101. The command identifying means 7 is a command line 10.
2 is connected to the peripheral device interface means 2, and a response activation line 103 is connected to the response means 8. The response means 8 are also connected to the peripheral device interface means 1 via a response line 104.

This embodiment will be explained step by step. The upper device interface means 1 and the peripheral device interface means 2 are:
Commands and data values are exchanged between the host device and the peripheral device on the data bus line 3. At this time, data bus line 3
The data identification signal line 5 indicates whether the value present in is a command or data. Also, data bus line 3
Timing control of data exchange of the above commands and data is performed by the data control line 4, and the host device interface means 1 and peripheral device interface means 2 can freely exchange commands and data.

At this time, the upper C
When the transmission of the test command reserved in advance is executed from the PU, the response confirmation means 6 is activated, and the peripheral device transmits the reserved 2-byte inverted data (DATA and 1's complement of DATA) after receiving the test command. It monitors whether DATA (for example, (55)□8 and (AA) HHX) is sent. If the response confirmation means 6 can confirm that the inverted data has arrived in the correct order, the data bus line 3, data control line 4, and data identification signal line 5 for data exchange are connected to the host device interface means 1 and the peripheral device interface means 2. You can check that it is connected correctly.

The command identification means 7 present on the peripheral device side monitors whether the command received by the peripheral device interface means 2 from the command line 102 is a test command, and when a test command is detected, the command identification means 7 is activated by the response activation line 103. to start.

The activated response means 8 passes 2 bytes of inverted data (DATA1DATA) from the response line 104 to the peripheral device interface means 2. The peripheral device interface means 2 sends the passed 2-byte inverted data to the host device interface means 1.

〔Effect of the invention〕

As explained above, the present invention provides a function that allows the receiving side to return fixed-length and inverted data when the peripheral side receives a test command sent from the host side.
The upper side has a function to check whether the inverted data is returned as expected. As a result, since the data used at this time is inverted data, data check,
If it is normal, it is possible to confirm the normality of all bits of the data line of the interface circuit between the upper host and the peripheral device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Host device interface means, 2... Peripheral device interface means, 3... Data bus line, 4...
・Data control line, 5...Data identification signal line, 6...
Response confirmation means, 7... Command identification means, 8... Response means, 101... Data line, 102... Command line, 103... Response activation line, 104... Response line.

Claims (1)

[Claims] Consists of a bidirectional data bus line, a data identification signal line that indicates whether the data on the data bus line is a command or data, and a data control line that controls the transmission and reception of commands and data on the data bus. an interface means, a command identification means for determining whether a command received by the interface means is a pre-reserved interface test command, and a response means for replying with inverted data of a predetermined length in response to the test command. and response confirmation means for determining whether data received after transmitting the test command is inverted data with a predetermined length.