JPH0449808B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an amplifier circuit, and more particularly to a large load capacity broadband amplifier circuit using insulated gate field effect transistors.

[Background of the invention]

Insulated gate field effect transistor (description is
Analog integrated circuits using Metal Oxide Semiconductor transistors (MOS transistors as an example) require a wideband amplifier circuit that can drive a large load capacitance and has a gain close to 1 in order to output high-speed analog signals. It may become. In such an amplifier circuit, a voltage follower using multi-stage amplification cannot be used because it becomes a high-speed and large-capacity load, and the phase rotation of the feedback becomes large, causing oscillation. Therefore, conventionally,
A voltage follower using a one-stage differential amplifier shown in FIG. 1 was used.

In the amplifier circuit shown in FIG. 1, an N-channel MOS transistor 2 whose gate is connected to the signal input terminal 1 and an N-channel MOS transistor whose gate is connected to the signal output terminal 3
MOS transistors 4 form a common source differential pair. The common sources of the transistors 2 and 4 are connected to the drain of an N-channel MOS current source transistor 7 whose gate is connected to a bias power supply 5 and whose source is connected to a negative power supply 6. The drains of the common source differential pair transistors 2 and 4 are respectively connected to the respective drains of two P-channel MOS transistors 8 and 9 forming a current mirror. transistor 8
The gates of and 9 are connected to the drain of the transistor 2, and the sources are connected to the positive power supply 10. The connection point between the drains of the transistors 4 and 9 serves as the output of the one-stage differential amplifier 11 composed of the transistors 2, 4, 7, 8, and 9, that is, the signal output terminal 3. Note that the negative input terminal of the single-stage differential gear 11 is the gate of the transistor 4. Therefore, the output of the one-stage differential amplifier 11 is directly connected to the negative input terminal, and the amplifier circuit shown in FIG. 1 functions as a voltage follower.

In the amplifier circuit shown in FIG. 1, since the open loop gain of the one-stage differential amplifier 11 is small, the input terminal 1
There is a problem in that the gain from the output terminal 3 to the output terminal 3 becomes considerably smaller than 1. To solve this problem, a resistive voltage divider circuit is inserted between the signal output terminal 3 and the negative input terminal of the single-stage differential amplifier 11, that is, the gate of the transistor 4, to reduce the amount of negative feedback and adjust the gain to 1. It is possible that However, with this method, there is a problem in that the resistive voltage divider circuit acts as a load on the single-stage differential amplifier 11, lowering its gain, and lowering the overall gain stability. Furthermore, due to fluctuations in manufacturing process and temperature,
Even if the gain of the stage differential amplifier 11 changes, the voltage division ratio of the resistive voltage divider circuit does not change, so there is also the problem that the overall gain changes.

[Purpose of the invention]

Therefore, an object of the present invention is to provide a high-speed, large-capacity load amplifier circuit that can solve the above-mentioned problems.

[Summary of the invention]

In order to achieve the above object, the present invention provides feedback from the output terminal of the single-stage differential amplifier to the negative input terminal of the single-stage differential amplifier using a feedback circuit via a source follower, and returns the feedback using the gain reduction by the source follower. By reducing the amount, the effect of amplifier gain variation is canceled. According to this configuration, the gain of the source follower also changes in response to the gain change of the one-stage differential amplifier, so that the overall gain stability is improved.

Outline of typical examples among the examples disclosed in this application is as follows.

That is, 1 constituted by insulated gate type MOS field effect transistors 2, 4, 7, 8, and 9.
The positive polarity input terminal of the stage differential amplifier 11 is used as the signal input terminal 1, the output terminal of the one-stage differential amplifier 11 is used as the signal output terminal 3, and the signal of the signal output terminal 3 is the negative polarity input of the one-stage differential amplifier 11. The amplifier circuit operates as a voltage follower by being fed back to a terminal, and includes an insulated gate MOS field effect transistor 20,
27, the input and output of the source follower circuit are connected to the signal output terminal 3 and the negative input terminal, respectively, so that the gain of the voltage follower is increased from 1 to 1. It is characterized by reduced deviation.

Specific embodiments and other features of the present invention include:
It will become clear from the examples below.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using the drawings.
FIG. 2 is a circuit diagram showing the configuration of one embodiment of the present invention. The amplifier circuit shown in FIG. 2 has a source follower formed by an N-channel MOS transistor 20 inserted between the signal output terminal 3 of the amplifier circuit shown in FIG. 1 and the negative input terminal of the one-stage differential amplifier 11. The gate of the transistor 20 is connected to the signal output terminal 3, that is, the output terminal of the one-stage differential amplifier 11, the drain is connected to the positive power supply 10, and the source is connected to the drain of the constant current source transistor 27 and the negative input terminal of the one-stage differential amplifier 11, that is, the transistor Connected to gate 4. Constant current source transistor 27
is an N channel whose source is connected to the negative side power supply 6 and whose gate is connected to the bias power supply 25. The bias power supply 25 and the bias power supply 5 can also be shared.

The gain of the amplifier circuit of FIG. 2 can be made equal to 1 by choosing the following constants for each transistor to satisfy the conditions: First, the deviation (decrease) ΔG1 of the gain of the amplifier circuit in Figure 1 from 1 is:
Assuming that the mutual conductances of transistors 2 and 4 are equal GM4, and the output conductance of transistor 9 is G9, it is determined by the output conductance seen from signal output terminal 3, that is, G9, and the mutual conductance GM4 of transistor 4, and this ΔG1
is ΔG1G9/GM4...(1). This is true when determining the output impedance seen from the signal output terminal 3 in an open loop state before the gate of the transistor 4, which is the negative input terminal of the one-stage differential amplifier 11, is connected to the signal output terminal 3. This is because the impedance of the connected differential transistor 4 and current source transistor 7 becomes much larger than the impedance of the current mirror load transistor 9. This is because in this open-loop state, the two series-connected transistors 4 and 7 operate as a cascode-connected circuit with their respective gates biased to different DC potentials, so the output impedance of this cascode-connected circuit is extremely high. This is due to the fact that it is large. On the other hand, the gain of the source follower in FIG. 2, that is, the deviation ΔGE of the gain from output terminal 3 to the gate of transistor 4 from 1, is
The mutual conductance of the transistor 20 is GMF,
If the output conductance of the transistor 27 is GC, then ΔGEGC/GMF (2) is obtained. This is because the output voltage of the source follower depends on the mutual conductance GMF of the transistor 20 and the output conductance GC of the transistor 27. Therefore, the condition for making the gain of the amplifier circuit in FIG. 2 1 by compensating for the deviation of the gain of the amplifier circuit in FIG. 1 from 1 by the decrease in the amount of feedback due to the source follower in FIG. ...(3). In order to almost satisfy condition (3), the mutual conductance of transistor 4 must be
Mutual conductance of GM4 and transistor 20
GMF may be made equal, and the output conductance G9 of the transistor 9 and the output conductance GC of the transistor 27 may be made equal.

In FIG. 2, common source differential pair transistors 2 and 4 and source follower transistor 2 are shown.
0 is formed in a well, and the well is connected to each source to reduce the influence of the substrate effect. In order to increase the speed, it is also possible to connect the well to the negative side power supply 6, but in that case, in order to match ΔG1 and ΔGE,
It is desirable to connect all wells of transistors 2, 4, and 20 to the negative power supply.

Note that since the input impedance seen from the gate of the source follower transistor 20 is extremely large, the problem that would occur when a resistive voltage divider circuit as described in the Background of the Invention is connected is avoided.

In addition, the gate of the source follower transistor 20 is not used as the signal output terminal 3, and this transistor 2
It should be noted that it is not possible to connect a low impedance load (for example, a large capacitance load) to the signal output terminal of this source by using a zero source as a signal output terminal. If you do it like this,
The deviation of the gain of the source follower circuit from 1 is shown in (2) above.
This is because it deviates from the equation and becomes unable to satisfy the condition of equation (3) above.

Next, FIG. 3 is a circuit diagram of another embodiment of the present invention, in which the buffering effect on input signals is enhanced. The amplifier circuit of FIG. 3 has P channel MOS transistors 30 and 4 connected to the positive and negative input terminals of the one-stage differential amplifier 11 of the amplifier circuit of FIG.
A source follower of 0 is inserted. The transistors 37 and 47 are constant current source transistors for source follower loads, and have drains connected to the sources of the source follower transistors 30 and 40, respectively, sources connected to the positive power supply 10, and gates connected to the bias power supply 35. ing.

According to the configuration shown in FIG. 3, since the input signal is buffered by the P channel source follower, a larger load capacitance can be connected to the signal output terminal 3. The gain reduction due to the substrate effect of the P channel source follower on the signal input terminal 1 side is offset by the gain reduction due to the P channel source follower on the return path side.

In addition, in order to prevent oscillation due to phase rotation in the two-stage source follower on the return path side, output terminals 3 and 1 are
It is also possible to connect a capacitor 50 between the negative input terminals of the stage differential amplifier to short-circuit the feedback path at high frequencies.

Although the present invention has been specifically explained above, it is clear that the present invention can be expanded as follows.
So far, we have explained using an N-channel differential pair in a CMOS circuit as an example, but a circuit with the same effect can be constructed by swapping the N-channel and P- channel and reversing the polarity of the power supply. Also, CMOS
To construct a similar circuit using a single channel N-channel or P -channel transistor circuit instead of a circuit. In this case, the constant current source is a depletion MOS transistor, and the current mirror part is a level shift circuit and a depletion MOS transistor.
This can be realized with a known configuration that also uses MOS transistors. Furthermore, in the explanation so far, the gain of the amplifier circuit of the present invention has been assumed to be 1, but it can be made to have a gain of 1 or more by inserting a resistive voltage divider circuit to the output of the source follower in the feedback path.

As explained in detail above, according to the present invention,
A high-speed, large-capacity load amplifier circuit with high gain stability can be realized, and in particular, the performance of an insulated gate field effect transistor integrated circuit can be improved.

[Brief explanation of drawings]

FIG. 1 is a drawing showing the configuration of a conventional amplifier circuit,
FIGS. 2 and 3 are drawings showing the configuration of the amplifier circuit of the present invention. 1...Signal input terminal, 3...Signal output terminal, 1
1...1 stage differential amplifier, 20, 30, 40... source follower transistor.

Claims (1)

[Claims] 1. A positive input terminal of a one-stage differential amplifier constituted by insulated gate MOS field effect transistors is used as a signal input terminal, an output terminal of the one-stage differential amplifier is used as a signal output terminal, An amplifier circuit that operates as a voltage follower by feeding back a signal at a signal output terminal to a negative input terminal of the one-stage differential amplifier, the source follower being configured by an insulated gate MOS field effect transistor. Further comprising a circuit, the input and output of the source follower circuit are connected to the signal output terminal and the negative input terminal, respectively, thereby reducing the deviation from the gain of the voltage follower of 1. Amplification circuit. 2 The differential amplifier includes first and second insulated gate type MOS field effect transistors of a differential pair whose gates are connected to the positive input terminal and the negative input terminal, and whose drains are different from each other. third and fourth insulated gate type MOS field effect transistors constituting a current mirror connected to the drains of the first and second insulated gate type MOS field effect transistors of the active pair;
A MOS field effect transistor whose drains are the first and second insulated gate MOS of the differential pair.
The source follower circuit includes a fifth insulated gate MOS field effect transistor as a current source connected to the source of the field effect transistor, and the source follower circuit has its gate and source connected to the signal output terminal and the negative input terminal, respectively. a sixth insulated gate type MOS connected to
Claims comprising a field effect transistor and a seventh insulated gate MOS field effect transistor to which a bias voltage is applied to its gate and whose drain is connected to the negative input terminal. The amplifier circuit according to item 1. 3 The third and fourth insulated gate type MOS field effect transistors constituting the current mirror are connected to the first and second insulated gate type MOS field effect transistors of the differential pair and the fifth insulated gate type MOS field effect transistor as the current source. 3. The amplifier circuit according to claim 2, wherein the amplifier circuit has a conductivity type opposite to that of the gate type MOS field effect transistor. 4 The sixth insulated gate MOS field effect transistor and the seventh insulated gate MOS field effect transistor of the source follower circuit are connected to the first and second insulated gate MOS field effect transistors of the differential pair and the seventh insulated gate MOS field effect transistor. Fifth as current source
4. The amplifier circuit according to claim 3, wherein the amplifier circuit has the same conductivity type as that of the insulated gate MOS field effect transistor.