JPH0449826B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an optical scanning device, and more particularly to a highly accurate scanning light position detection method with extremely low probability of malfunction due to electrical noise.

(b) Prior Art and Problems A laser printer will be described as an example of a device that performs recording using scanned light, which is a prior art of the present invention. FIG. 1 shows a configuration diagram of a laser printer 11. As shown in FIG. In the figure, 12 is a laser light source, which uses a semiconductor laser. The light beam M emitted from this laser light source 12 passes through a collimator 13, and after being made into a required beam diameter by the collimator 13, it is scanned in the direction of arrow X by a light beam scanning means (rotating polygon mirror) 14 to form an image. The light is focused onto a photoconductor drum 16 by an optical system 15 and scanned with a light beam M _S having a constant spot diameter. The photoconductor drum 16 is rotated in the direction of the arrow Y perpendicular to the scanning direction arrow X of the light beam M _S so that a recorded pattern of dots can be exposed onto the photoconductor drum 16, which is created by the electrophotographic process. A dot pattern can be recorded on plain paper.

In order for the print obtained in this way to have high quality, the spot position of the light beam M _S scanned by each mirror surface of the rotating polygon mirror 14 must be adjusted in the light beam scanning direction (arrow X direction) and in the direction perpendicular to this (arrow X direction). They must be lined up at equal intervals in the direction of arrow Y). Since the rotating polygon mirror 14 has mechanical processing errors such as angle division errors, the timing of the initial position of each pixel in the scanning direction varies slightly for each scan. In order to correct this, a photodetector 18 (consisting of a light receiving element) is installed as a light detection means at the scanning start position, and the scanning light detection output is used to generate a pixel (light beam modulation) via the light modulator control circuit 17. ) A method is used to control the timing.

FIG. 2 shows the output waveform of the conventional photodetector 18, in which a is a peak waveform and b is a flat waveform. In either case, if the rising and falling timings are shaped using a constant threshold value L and are taken as the light detection timings, Fig. 2a
As shown in the figure, the rise times of the output waveforms V ₁ , V ₂ , and V ₃ of the photodetectors corresponding to different mirror surfaces of the rotating polygon mirror 14 are t _r1 , t _r2 , and t _r3 , and the respective fall times are t The timings are different like _f1 , t _f2 , and t _f3 . Further, in the case of a peak-shaped waveform as shown in FIG. 2a, it is possible to increase the accuracy of the photodetection timing by analog peak detection, but in the case of b, peak detection is impossible. Of course, it is conceivable to capture the peak of the output waveform of the photodetector 18 and use it as a synchronization signal, but there is a large risk of capturing the wrong peak value when noise or the like enters.

Therefore, although there are differences in the output waveform of the photodetector 18 for each mirror surface of the polygon mirror 14, the scanning light beam synchronous control method (unexamined patent application Showa 53-
(Refer to Publication No. 122331).

In FIG. 2a, the median value P of each rise time and fall time is determined, and at time t _S after a certain period of time T _c has elapsed from the median value, the synchronization signal S
Output. With this synchronization signal, the scanning light beam
Define this as the initial position for M _S printing. It is clear that the synchronization signal _S at this time t S is generated at the same timing for all mirror surfaces. Here, regardless of the output waveform V ₁ , V ₂ , V ₃ of any of the photodetectors 18, the rising time t _r1 , t _r2 , t _r3 is defined as time 0, and the falling time t _f1 , t _f2 , t _f3 to t
As a result, the half time t/2 coincides with the peak time in both cases. Therefore, the relationship t _S =t/2+T _c (1) holds true for any photodetector output waveform. Therefore, each waveform V ₁ , V ₂ , V ₃
The time (t S - t) from the falling time t _f1 , t _f2 , _{t f3} to the synchronization signal generation time t _S is calculated as t _S - t = T _c - t/2 by substituting the above equation (1). ...(2) is obtained. That is, according to the prior art, the rise t _r1 ,
Start measuring the elapsed time at t _r2 and t _r3 (initial value 0),
Stop measuring the elapsed time at the falling edge (t _f1 , t _f2 , t _f3 ), immediately halve the elapsed time, set this as the initial value, start measuring the elapsed time again, and then When the value reaches _Tc , a synchronizing signal S is sent out and the series of operations is completed.

-t/2 in the above equation (2) means returning time to time t/2, and this is done in the process in the above section. The steps in this section can be easily carried out using an electronic circuit, and are carried out by measuring the elapsed time described above using a counter.

FIG. 3 is a circuit diagram of a conventional scanning light beam synchronization control system, and FIG. 4 is a time chart showing waveforms at various parts in FIG. In FIG. 3, 18 is the photodetector already mentioned, 18' is the threshold value L shown in FIG.
This is the synchronization signal required by a comparator S that compares the output of the photodetector 18 and the level. Reference numeral 31 denotes a timing clock generator that supplies a clock pulse of frequency f necessary for measuring elapsed time, and the waveform of the clock pulse A is shown in FIG. 4A. The scanning light beam M _S arrives, and the output B of the photodetector 18 is the fourth
When the voltage changes as shown in Figure B and crosses the threshold value L, the output waveform C of the comparator 18' rises as shown in Figure 4C. Thereafter, the Q output of the D-type flip-flop 32 rises at the timing when the clock pulse A first falls (see FIG. 4D). At the same time, the Q of the D-type flip-flop 33 whose D terminal has the logical value "1"
The output also rises (see Figure 4E). Then, the Q output opens the AND gate 34, and the clock pulse A passes through the AND gate 34 (fourth
(See Figure F). The clock pulse A from the AND gate 34 is received, and the J terminal has a logical value of "1".
The Q output of the JK flip-flop 35 is as shown in FIG. 4G. Therefore, clock pulse A from AND gate 34 and Q from flip-flop 35
The output of the AND gate 36 whose input is the output is the fourth
The result will be as shown in Figure H. That is, comparator 1
After the output C of 8' becomes the logical value "1" (second
At time t _r1 , t _r2 or t _r3 in the figure), the output of the AND gate 36 is 1/2 frequency (1/2f) of clock pulse A.
This becomes a clock pulse, which is applied to the counter 37. A clock pulse with a frequency of 1/2 of this,
That is, the counter 37 counts the 1/2 frequency divided output of the clock pulse A. The steps up to this point correspond to the steps already described. When the counter 37 starts counting the 1/2 frequency divided output of the clock pulse A, and the photodetector output crosses the threshold L in FIG. 4B again (this is at time t _f in FIG. 4B, t _f1 , t _f2 , t _f3 in Figure 2
), the output C of the comparator 18' falls,
The Q output of the flip-flop 32 falls at the timing when the clock pulse A rises, and the Q output of the flip-flop 35 holds the logic value "1" (see FIG. 4G). The steps up to this point correspond to the steps already described.

Immediately after this, the process begins, and the first time of the process is reduced to 1/2. This corresponds to halving the system time and is achieved by doubling the frequency of the clock pulses. After falling below the threshold value L as shown in FIG. In other words, the clock pulse to the counter 37 is switched from the 1/2 frequency divided output of the clock pulse A to the clock pulse A itself (frequency f). Thereafter, the counter 37 counts T _c ×f pulses shown in FIG. 2a using the clock pulse whose frequency has been doubled, and
A synchronization signal _S obtained at time tS is output from the carry terminal CY of the counter 37. The synchronization signal S is simultaneously applied to flip-flops 33, 35 and counter 37.
via line 38. This corresponds to the process already described.

In this way, a synchronization signal S with no phase shift is ensured for each mirror surface. In the above explanation, the timekeeping clock generator 31 and the counter 37 constitute timekeeping means,
Flip-flops 33 and 35 and AND gates 34 and 36 constitute calculation means.

However, in the above circuit system, although the detection accuracy of the scanning light is high, if the photodetector 18 malfunctions due to the intrusion of noise etc., even if the next true photodetection signal is input continuously, after a predetermined time elapses, Since reset cannot be performed during the time period until the synchronization signal S is output, there is a drawback that malfunction recovery processing cannot be performed.

(c) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention has been made to determine the authenticity of the scanning light at the time of detection of the scanning light, to enable quick malfunction recovery processing, and to enable high-precision scanning light position detection at low cost. The purpose is to provide a circuit that

(d) Structure of the Invention According to the present invention, this object includes a light source, a scanning means for scanning a light beam emitted from the light source, and a light beam placed on a surface to be scanned to be scanned by the scanning contact means. It is equipped with a detection means, a timer for measuring the time from the rise to fall of the output of the light detection means, and a calculation means for calculating the median time between the rise and fall of the output, and the initial position of the scanning light in each scan. In a scanning light beam synchronization control method for positioning a scanning light beam, a determining means determines whether the counted value of the time measuring means is true or false within a predetermined range, and when the determination result of the determining means is false, the time measuring means and means for initializing the calculation means and the determination means, and outputs a scanning light beam synchronization signal after a predetermined time has elapsed from the time calculated by the calculation means when the determination result of the determination means is true. This is achieved by providing a scanning light position detection circuit that achieves this.

(e) Examples of the invention Examples of the invention will be described in detail below with reference to the drawings. In the figure, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and redundant explanation thereof will be omitted.

FIG. 5 shows a circuit diagram of a scanning light position detection circuit according to the present invention.

In the figure, the area outside the dashed line is the conventional circuit shown in FIG. 3, and the area inside the dashed line is the circuit of the present invention. 4
1 is a sample and hold circuit whose clock terminal C is connected to the output terminal of the flip-flop 32, and whose data terminal D is connected to the Q terminal of the counter 37. However, the sample hold circuit 41
Q output of comparator 42 and comparator 43
are input in parallel to one side of the comparison input terminal W 1 of the comparator 42, and the other comparison input terminal W ₁ of the comparator 42
The lower limit value of the photodetector output pulse width is set and input to , and the upper limit value of the photodetector output pulse width is set and input to the other comparison input terminal W ₂ of the comparator 43 .

Further, each output terminal of the comparators 42 and 43 is inputted to an OR gate 44, and the output terminal is outputted as a status signal Z, and the status signal Z is inputted to each reset terminal R of the comparators 42 and 43.
are connected in parallel to each other, and further connected to one of the input terminals of the OR gate 45. In addition, the circuit configuration is such that the carry terminal CY output is taken out from the counter 37 and connected to the other input terminal of the OR gate 45, and the output terminal of the OR gate 45 is connected via the line 38 to the flip-flops 33 and 35 and the reset terminal R of the counter 37. It's getting old.

Next, the operation of the circuit of this embodiment will be explained.

The output of the flip-flop 32 is an inverted waveform of the waveform shown in FIG. The Q output of the counter 37 is inputted to the comparison terminals of the comparators 42 and 43 as a sampling value (that is, the count value of the timer corresponding to the time width exceeding the threshold value L). The lower limit value set and input to the input terminal W ₁ of the comparator 42 and the upper limit value set and input to the input terminal W ₂ of the comparator 43 are both reference values of the determination means for determining the authenticity of the output of the photodetector 18. If the signal is false, it will either exceed the upper limit or fail to reach the lower limit, and in this case, the comparators 42 and 43
At least one of the outputs becomes a logical value "1".
Therefore, since at least one of the inputs of the OR gate 44 has a logic value of "1", its output has a logic value of "1" and outputs the status signal Z with a logic value of "1". The logical value "1" of the status signal Z opens the OR gate 45, and the reset terminals of the counter 37 constituting the time measuring means, the flip-flops 33 and 35 constituting the calculating means, and the comparators 42 and 43 of the determining means are connected via the line 38. drive and initialize each means. Also, the carry terminal of counter 37
When the synchronizing signal S is outputted from CY with a logical value of "1", the OR gate 45 is opened and the above-mentioned means are initialized via the line 38.

Next, if the output of the photodetector 18 is a true signal, it is satisfied that the lower limit value ≦ the sampling value (count value) ≦ the upper limit value, and in this case, the outputs of the comparators 42 and 43 are both logical. The value becomes "0", and therefore the output of the OR gate 44 becomes the logical value "0".
Therefore, no status signal is output and no reset action is performed. That is, when the output of the photodetector 18 is determined to be a true signal, the timekeeping means and calculation means are executed as normal and initialized with the output of the synchronization signal S. Further, when a false signal is determined, each means is initialized immediately after the upper limit value is determined.

(f) Effects of the Invention As explained above in detail, according to the scanning light position detection circuit of the present invention, a malfunction detection function can be added easily and inexpensively to a conventional high-precision scanning light position detection circuit, and noise can be reduced. This has the advantage that the position of the scanning light can be detected with high precision even in many adverse environments. If applied to laser printers, etc., it can be used for equipment such as large motors.
You can expect stable printing without any disturbance when turning on or off.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a laser printer as an example of a device that uses scanned laser light, Figure 2 is an example of the output waveform of a photodetector that detects the position of the scanning light, and Figure 3 is a diagram of the conventional scanning light FIG. 4 is a circuit diagram of the beam synchronization control system, FIG. 4 is a time chart showing waveforms at various parts of FIG. 3, and FIG. 5 is a circuit diagram of a scanning light position detection circuit according to the present invention. In the figure, 12 is a light source, 14 is a rotating polygon mirror, 1
8 is a photodetector, 18' is a comparator, 31 is a timing clock generator, 32, 33 and 35 are flip-flops, 34 and 36 are AND gates, 37 is a counter, 41 is a sample and hold circuit, 42 and 4
3 is a comparator, 44 and 45 are OR gates, M
, M _S is a light beam, S is a synchronization signal, and L is a threshold value.

Claims (1)

[Claims] 1. A light source, a scanning means for scanning a light beam emitted from the light source, a light detection means installed on a surface to be scanned by the scanning means, and a period from the rise to the fall of the output of the light detection means. In a scanning light beam synchronization control method for positioning the initial position of the scanning light in each scan, the scanning light beam synchronization control method includes a timer for measuring the time of , and a calculation means for calculating the median time of the rise and fall of the output, and positions the initial position of the scanning light in each scan. comprising a determining means for determining the truth or falsehood of whether the counted value is within a predetermined range, and means for initializing the clocking means, the calculating means, and the determining means when the determination result of the determining means is false; A scanning light position detection circuit characterized in that, when the determination result of the determination means is true, a scanning light beam synchronization signal is output after a predetermined period of time has elapsed from the time calculated by the calculation means.