JPH0451100B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an FM stereo demodulation circuit suitable for use in an FM receiver.

[Background technology]

The FM multiplex demodulation circuit reproduces a 38KHz subcarrier transmission signal based on the 19KHz pilot signal in the composite signal obtained by FM detection, and also performs switch selection of the composite signal using the reproduced subcarrier signal. Therefore, the right signal and the left signal are reproduced.

The subcarrier signal is detected by a voltage controlled oscillation circuit, a frequency divider circuit or a flip-flop circuit that receives the output of the voltage controlled oscillator circuit, and a phase detection circuit that detects the phase difference between the output of the frequency divider circuit and the pilot signal. A so-called PLL consisting of a filter circuit that forms a control voltage for the voltage controlled oscillation circuit based on the output of the phase detection circuit.
(phase locked loop).

The present inventors have discovered that when the power supply voltage drops, the above-mentioned frequency divider circuit enters an oscillation state due to the phenomenon described below, and accordingly, the frequency, phase, and duty ratio of the subcarrier signal during FM transmission are changed. etc., a reproduced subcarrier signal that does not correspond at all is formed, and stereo demodulation is performed using such an undesired reproduced carrier signal, and the resulting stereo reproduction output contains abnormal sounds and such oscillations occur. It was revealed that this caused radio interference to other circuits. In addition, in Japanese Patent Application Laid-open No. 53-143101,
A stereo switch circuit that selectively supplies the reproduced subcarrier signal from the frequency dividing circuit to a multiplexer or a stereo coder according to stereo/mono reproduction is forced into a monaural reproduction state in response to a drop in the power supply voltage. An FM stereo demodulation circuit is disclosed that prevents abnormal sound from being added to the stereo playback output due to the noise. However, since the configuration described in the publication controls a stereo switch circuit, it is not necessarily sufficient to prevent abnormal noise from occurring depending on the timing of detecting a drop in power supply voltage and switching to monaural operation. Furthermore, radio interference removal is not taken into consideration.

An object of the present invention is to provide a stereo demodulation circuit that can prevent abnormal sounds from being added to the stereo reproduction output and is less likely to cause radio wave interference.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief summary of the invention disclosed in this application is as follows.

That is, a switching means is provided for each of a pair of transistors that perform a phase inversion operation of a flip-flop circuit used as a frequency divider constituting a stereo demodulation circuit, and when the power supply voltage drops, the level thereof is detected and the switching means is driven. This turns the pair of transistors off at the same time and prevents them from entering an oscillation state.

〔Example〕

Next, an embodiment of a stereo demodulation circuit to which the present invention is applied will be described with reference to FIGS. 1 to 3.
Note that FIG. 1 is a circuit diagram of a flip-flop circuit using the present invention, FIG. 2 is a waveform diagram for explaining circuit operation, and FIG. 3 is a circuit diagram of a stereo demodulation circuit.

The flip-flop circuit FF of FIG. 1 has a terminal _T1 to which an input signal to be frequency-divided is applied, and a terminal Q to which a complementary output signal of frequency division by 2 is output, which are added according to the present invention. It has a trigger terminal _T2 . Flip-flop circuit FF is a terminal
When T ₂ is at a low level such as approximately 0 volts, it operates as a 1/2 frequency divider circuit, and outputs a signal whose frequency is divided by 2 with respect to the input signal applied to the terminal T ₁ to the output Q.

In the flip-flop circuit FF ₁ shown in Fig. 1, transistors Q ₅ , Q ₆ and resistors R ₇ , R ₈ operate as a forced stop circuit, and when the +V _CC power supply level drops, the Q output and output have a duty ratio of 50%. The FF ₁ can be stopped while being held.

Assume now that the +V _CC power supply is at a normal voltage level and a trigger signal is supplied to terminal _T1 . In this case, the collector voltage V _CQ1 of transistors Q ₁ and Q ₂ has a duty ratio of 50 as shown in FIG. 2A.
%, and the collector voltages V _CQ3 and V _CQ4 of transistors Q ₃ and Q ₄ , in other words, the Q output and the output change polarity as shown in FIG. 2B and C. At this time, unless the control signal P _C is supplied from the terminal T ₂ , the transistors Q ₅ and Q ₆ remain off, and do not have any influence on the circuit operation.

On the other hand, when the V _CC power supply decreases, even if the Q output and the output change to high or low levels, the voltage difference between them becomes small, and it becomes difficult to turn transistors Q ₃ and Q ₄ on or off sufficiently. The base-emitter voltage V _BE cannot be supplied, and if left as is, the transistors Q ₃ and Q ₄ may be inverted even by minute noise components. This reversal phenomenon means that the flip-flop circuit FF enters an oscillating state, and the oscillation frequency becomes a radio wave for preventing damage to other circuits.

However, in this embodiment, when the level of the +V _CC power supply drops below a predetermined level, a control signal P _C is supplied from a power supply voltage detection circuit, which will be described later, to drive transistors Q ₅ and Q ₆ to the on state.

As a result, the bases of transistors Q ₃ and Q ₄ are forcibly connected to GND, thereby preventing the abnormal oscillation phenomenon from occurring. What should be noted here is that transistors Q ₃ and Q ₄ are turned off at the same time. That is, even if either transistor Q ₃ or Q ₄ is turned off, the other transistor operates, and there is no problem that the duty ratio of the Q output and the output are different.

Next, the circuit operation of the stereo demodulation circuit using the flip-flop circuit FF will be described. In addition,
In the stereo demodulation circuit shown in Figure 3, 1/2
The above flip-flop circuit is used in frequency dividers 6, 7, and 8.
When the FF is used and the +V _CC power supply supplied from the battery E drops in level, the same circuit operation as above is performed for the 1/2 frequency dividers 6, 7, and 8 by the control signal P _C obtained from the voltage detector 20. is carried out, and the above-mentioned oscillation phenomenon does not occur.

Terminal 1 of the stereo demodulation circuit in Figure 3 has an FM
A composite signal as obtained by wave detection is added. The composite signal is sent to preamplifier 1
The signal is supplied to phase detectors 2 and 10 and a stereo decoder 11 via.

The phase detector 2, low pass filter 3, DC amplifier 4, voltage controlled oscillator 5, and 1/2 frequency dividers 6 and 7 are as follows:
It constitutes a so-called PLL (Phase Locked Loop) circuit, and is provided to reproduce the 39KHz subcarrier signal that is phase-locked to the 19KHz pilot signal in the composite signal supplied via the preamplifier 1. There is.

The phase detector 10 receives the FM detection signal supplied via the preamplifier 1 and the regenerated signal from the 1/2 frequency divider 8.
Compare the phase with the 19KHz signal. Phase detector 10
The output is a signal indicating whether or not there is a pilot signal in the FM detection signal, in other words, a signal indicating whether it is a stereo broadcast or a monaural broadcast. The light is supplied to the lamp driver 15.

The lamp driver 15 drives a stereo/monaural display lamp supplied to the terminal 9.

The stereo switch circuit 12 is driven by the output of the hysteresis circuit 14, and in the case of stereo broadcast reception, supplies the 38KHz reproduced subcarrier signal supplied from the 1/2 frequency divider 6 to the stereo decoder 11.
For monaural broadcast reception, the input to the stereo decoder 11 is set to high level.

The stereo decoder 11 receives the signal from the preamplifier 1.
The FM detection signal and the reproduction subcarrier signal via the stereo switch circuit 12 are received, and the stereo reproduction output Lout,
Form a route.

In this embodiment, the outputs of the hysteresis circuit 14 and the inverter 1 are commonly connected so that the low level has priority. As a result, the stereo switch circuit 12 the playing card driver 15
is also driven by the inverter 21.

The input signal for inverter 21 is formed by voltage detector 20 .

The voltage detector 20 is configured to detect the level of the power supply voltage +Vcc, and produces a high-level output when the power supply voltage +Vcc falls below a predetermined level. Therefore, when the level of the +V _CC power supply drops, the 1/2 frequency dividers 6, 7, and 8 are provided to prevent the flip-flop circuit from oscillating, and the stereo switch 12 is completely controlled by the output of the inverter 21. Since the stereo switch 12 is turned off, the 38KHz subcarrier signal is not supplied to the decoder 11 from the stereo switch 12. Therefore, in the stereo demodulation circuit described above, even if the level of the +V _CC power supply decreases, the degree of separation between the R signal and the L signal does not decrease.

〔effect〕

(1) By detecting a drop in the level of the power supply voltage and forcibly completely stopping the operation of the frequency divider that makes up the stereo demodulation circuit, damage prevention waves due to the oscillation phenomenon of the flip-flop circuit provided as the frequency divider can be prevented. The occurrence of such problems can be completely prevented.

(2) At the same time as the circuit operation in (1) above, by completely stopping the circuit operation of the stereo switch 12, the subcarrier signal is not supplied to the decoder, and the R
It is possible to prevent a decrease in the degree of separation between the signal and the L signal.

[Application field]

In the above description, the invention made by the present inventor has mainly been described with respect to a stereo demodulation circuit, which is the application field that forms the background of the invention, but the present invention is not limited thereto.

For example, the flip-flop circuit described above can be used in various counting circuits.

[Brief explanation of the drawing]

FIG. 1 shows a circuit diagram of a flip-flop circuit showing an embodiment of the present invention, FIGS. 2A, B, and C show waveform diagrams explaining the circuit operation of the flip-flop circuit, and FIG. A circuit diagram of a stereo demodulation circuit using as a frequency divider is shown. FF...Flip-flop circuit, 6, 7, 8...
... Frequency divider, 20... Voltage detection circuit, Q ₁ , Q ₂ , Q ₃ ,
Q ₄ , Q ₅ , Q ₆ ...transistor, P _C ...control signal,
E...lol.

Claims (1)

[Claims] 1. A phase detector, a voltage controlled oscillator whose operation is controlled by the output of the phase detector, and a reproduced subcarrier signal by dividing the output of the voltage controlled oscillator. A frequency divider to form an FM
A multiplex demodulation circuit, comprising: a voltage detection circuit that detects a drop in the level of the power supply voltage; and a pair of switching transistors that are turned on when the level of the power supply voltage drops by the output of the power supply detection circuit. The pair of switching transistors are coupled to the pair of transistors so as to forcibly stop the pair of transistors forming the phase detector output in the frequency divider when the level of the power supply voltage drops. An FM multiplex demodulation circuit characterized by the following.