JPH0451224A - Method and device for optical parallel arithmetic processing - Google Patents

Abstract

PURPOSE:To allow the execution of arbitrary logical expressions described by Boolean algebra by optical parallel processing which can make multistage processing and is programmable by utilizing the parallelism and high speediness of light. CONSTITUTION:The light from a light source 2-1 is linearly polarized by a polarizer 2-2, is spacially resolved to a picture element by a pixel mask 2-3 then is made incident on a 1st transmission type special modulator 2-4 and is subjected to the substitution of polarization by the input from a circuit 2-5. This light is spacially separated by a double refractive plate 2-6, is further made incident on a 2nd transmission type spacial modulator 2-7 and is subjected to the substitution of polarization by the input from a circuit 2-8. The light after coding using this polarized light, etc., is made incident on a kernel 2-10 for computation where spacial selecting elements array, by which the results of logical operations are obtd. A symbol 2-11 is a spacial optical modulator (SLM). The SLM modulates the written reading out light when the constant determined from the wavelength, intensity, time, etc. of the incident light within certain finite time exceeds a certain constant. A symbol 2-12 is a polarization beam splitter for admitting reading out light to 2-11 and 2-13 for admitting the reading out light to 2-11.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method and apparatus for optically performing logical operations between a plurality of digital pattern information,
In particular, image processing, logical operations between various symbols, and their processing equipment (
It belongs to the field of computers).

(Prior art) FIG. 4 is an explanatory diagram of conventional optical parallel arithmetic processing.
1 is a light source of incident light for processing; 12 is a polarizer; 1-
3 is a pixel mask arranged to prevent the coded light of adjacent pixels from overlapping after spatial encoding; 1-
4 is the first input that replaces the binary information of the first input with polarization information.
Transmissive spatial modulator 1-5 is the first transmissive spatial modulator in spatial modulator 1-4.
1-6 is a birefringent plate, 1-7 is a second
a second transmissive spatial modulator that replaces input binary information with polarization information; 1-8 is a circuit that provides second information for the spatial modulator 1-7; 1-9 is a birefringent plate; -10 is the kernel. The light from the light source 1-1 becomes linearly polarized light by the polarizer 1-2, is spatially decomposed into pixels by the pixel mask 1-3, and enters the first transmissive spatial modulator 1-4, where it becomes linearly polarized light. -4 undergoes a displacement of polarization by the first input from circuit 1-5. According to this state, the separated light is spatially separated by the birefringent plate 1-6, and the separated light is further incident on the second transmissive spatial modulator 1-7, and is transmitted to the second transmissive spatial modulator 1-7 by the birefringent plate 1-6.
The polarization is replaced by the input, and the birefringence plate 1-9 spatially separates the polarized light according to this state. The light encoded using this polarization and spatial position obtains a calculation result by a calculation kernel 1-10 in which spatial selection elements are arranged. In FIG. 4, the polarization and position at the time of encoding are attached. Depending on the logic values of pixels a and b, they take four spatially different positions.

(Problems to be Solved by the Invention) The present invention utilizes the parallelism and high speed of light to execute arbitrary logical expressions written in pool algebra using a multi-stage and programmable optical parallel processing method. The object of the present invention is to provide a method and apparatus for doing so. In particular, we aim to achieve system simplicity.

(Means for Solving the Problems) The present invention performs polarization encoding for each pixel on binary digital information to be operated on, repeats the operation of spatially separating the encoded light, and performs logical operation. The operation is performed by selecting only the light at spatially separated positions corresponding to By doing this, the output light is made into light at one spatial position (or at multiple positions), but the processing involves inputting this output light into an optical writing type spatial light modulator with certain characteristics, and It is characterized in that the readout output is obtained as the final calculation result. The feature here is that it operates as a threshold for a constant determined from the intensity, wavelength, time, etc. of the light incident within a finite time for the write input of the modulator. It is.

It differs from conventional technology in the following points.

(1) The optical parallel arithmetic method shown in Figure 4 is basically a serially configured arithmetic method and arithmetic device, and it does not have a memory function to hold the arithmetic results, so it cannot be used for complex logical arithmetic expressions. It was difficult to operate, and the configuration of the device had to be changed depending on the logical formula, for example, by increasing the number of stages or arranging devices in parallel, and it was not scalable to general-purpose processors.

Although the configuration of the present invention is almost the same as this configuration, the type of operation that can be executed is only possible by adding an extremely complex general-purpose processor configuration to the system shown in FIG. , can be executed with this simple configuration. For example, an operation expressed as the sum of the products of two human forces can be executed.

(2) If the same calculation is implemented using a feedback system processing method as described in (1) above, the feedback is repeated many times, which not only takes calculation time but also tends to accumulate errors. The configuration of the present invention is highly likely to be advantageous in terms of calculation time and calculation accuracy.

(Embodiment) FIG. 1 is a conceptual diagram of the configuration of an embodiment of the present invention, and 2-
1 to 2-10 are 1-1 to 1-1 in Figure 4.
It is the same as 0. To repeat the explanation here, 2-1 is a light source of incident light for processing, 2-2
2-3 is a polarizer, 2-3 is a pixel mask arranged to prevent the coded light of adjacent pixels from overlapping after spatial encoding, and 2-4 is polarization information for the binary information of the first input. 2-5 is a circuit that provides information of the first input to the spatial modulator 2-4, 2-6 is a birefringent plate, and 2-7 is a circuit that provides information of the first input to the spatial modulator 2-4. a second transmissive spatial modulator that replaces binary information with polarization information; 2-8 is a circuit that provides second input information to the spatial modulator 2-7; 2-9 is a birefringent plate; 2- 10 is a kernel. The light from the light source 2-1 becomes linearly polarized light by the polarizer 2-2, and the light from the pixel mask 2-
3, the first transmissive spatial modulator 2-4 enters the first transmissive spatial modulator 2-4, and the first pixel from the circuit 2-5 is input to the first transmissive spatial modulator 2-4.
The polarization is replaced by the input. According to this state, the light is spatially separated by the birefringent plate 2-6, and the separated light is further incident on the second transmissive spatial modulator 2-7, where it is transmitted to the second transmissive spatial modulator 2-7 from the circuit 2-8. The polarization is replaced by the input, and depending on this state, the light is spatially separated by the birefringent plate 2-9. This encoding using polarization and spatial position is performed for each pixel. The light encoded using this polarization and spatial position is incident on the calculation kernel 2-10 in which spatial selection elements are arranged, and a logical calculation result is obtained. By independently controlling each selection element of this kernel (or each pixel when a spatial light modulator or the like is used in the kernel), calculations for each pixel can be independently instructed.

In FIG. 1, the polarization and position at the time of encoding are attached. pixel a
It takes four spatially different positions depending on the logical values of and b.

2-11 onwards are the parts showing the features of the present invention.

2-11 is a spatial light modulator (SLM). This SLM
is an optical writing type and has the following characteristics. Regarding light incident within a certain finite time, if a constant determined from its wavelength, intensity, time, etc., including operating conditions, etc., exceeds a certain constant specific to the SLM, the SLM modulates the writing and reading light. . If it does not exceed this, no modulation occurs.

2-12 is the readout light source for 2-11 (including a polarizer if necessary), 2-13 is a polarizing beam splitter for inputting the readout light into 2-11 (same for half mirror-ten analyzer), When a transmission type SLM is used for 2-11, a polarizing beam splitter 2-13 is placed in front of 2-11 so that the readout light is incident on 2-11.

In reality, as shown below in the explanation of FIG. 3, it is necessary to time each operation and execute calculations, so some kind of control device is required.

FIG. 2(a) is a block diagram for explaining conventional arithmetic processing, and FIG. 2(b) is a block diagram for explaining arithmetic processing of the present invention. clarifies the difference between

The conventional technology is composed of an encoding section and a logic operation execution section, and the incident readout light is encoded, and this encoded light is spatially selected in the logic operation execution section according to the content of the logical operation. The result is obtained as output light. In the technology of the present invention, a logical operation result processing section is provided after this logical operation execution section, and the light that has been encoded and logically converted is subjected to final operation processing in this logical operation result processing section. Output.

FIG. 3 is a diagram showing an example of a timing chart for explaining the operation of the arithmetic processing of the present invention. In Figure 3, 4
-1 and 4-2 indicate the timing of the write command to the encoder, and they are respectively human power 1 (from 2-5 to 2 in Figure 1).
-4)・Input 2 (from 2-8 to 2 in Figure 1)
-7). 4-3 is the timing of an instruction to the logical operation execution unit (2-10 in FIG. 1).

4-4.4-5 is a logic operation result processing unit (2-1 in Figure 1).
1), which are a write mode command that commands a write state and a read mode command that designates a read timing. This read mode command may not be necessary depending on the SLH used. This is a case where it is sufficient to read at an appropriate timing (for example, timing 4-6) after writing is completed.

4-6 is the timing of the readout light to the SLM of the logical operation result processing section.

Next, the operation will be explained.

For example, assume that a logical operation A-B+C-D in the sum-of-products format is performed. First, parallel binary patterns A and B are input to input 1.2. As shown in 4-1.4-2, this is input at the timing of the first write.

After this input, at the minimum timing of 4-3 (AND)
Send calculation instructions. Next, rewrite the input and 4-1゜4-
After inputting C and D to 2, execute .(AND). While this logic conversion result is being output, the SLM of the logic operation result processing section is kept in write mode as shown in 4-4. In order to prevent unnecessary light from entering and writing at a timing unrelated to the result of this logical operation, if necessary, the logical operation is normally set to 0 (the logical operation execution unit 2-10 is set so that no light passes through it at all). Setting 2-10 to logical operation 0 corresponds to 2-10 not allowing any light to pass through), or control the on/off timing of the readout light to the encoder. ,do. The condition for the input of the logical operation processing unit is modulated when the first logical operation result is 1, the second logical operation result is 1, or both are l. In other words, if the input is 0, it will not be modulated, but if a light pulse comes even once (due to the threshold function)
Let it be modulated. This depends on the operating conditions in 2-11 and the write timing width by read light (4-3
This can be done by setting the pulse width), the intensity of the reading light, and the introduction of the writing light as a bias. In this way, the processing of the sum of products between two human forces can be done with this configuration,
In addition, in the case of a product between three human forces or a sum of products between multiple inputs, a logic operation execution unit for the basic number of inputs is configured, and a logic operation result processing unit is provided using the method of the present invention. Can be executed.

Next, try executing the sum-product type operation (A + B) / (C + D). First, binary patterns A and B are parallel to inputs 1 and 2.
Enter. As shown in 4-1.4-2, this is input at the timing of the first write. After this input, 4-
At the first timing of step 3, a + (OR) operation command is sent.

Next, after rewriting the input and inputting C and D into 4-1.4-2, execute + (OR). While this logical operation result is being output, the SLM of the logical operation result processing section is kept in write mode as shown in 4-4. To prevent unnecessary light from entering and writing at a timing unrelated to the result of this logical operation, if necessary, the logical operation is normally set to 0 (the logical operation execution part 2-10 is set so that no light passes through). Either the on/off timing of the readout light to the encoder is controlled. The conditions for the input of the logical operation processing section are such that the first logical operation result is 1,
And the second logical operation result is also modulated when it is 1, that is, it is not modulated when there is O in the human power, but it is modulated when the light pulse comes both times (by the Threnshold function). . This can be done by setting the operating conditions in 2-11, the width of the write timing by the read light (pulse width in 4-3), the intensity of the read light, and the introduction of the write light as a bias. In this way, the processing of the product of sums between two human forces can be performed with this configuration, and in the case of the sum of three human forces or the product of sums between multiple inputs, the logical operation execution unit for the basic number of inputs can be used. The method of the present invention can be implemented by providing a logical operation result processing unit.

In addition to the above, there are two or more 1 in the logical product between two human forces.
If they match, it becomes possible to output 1. In other words, A-B, C-D, E-F, G-H.

If there are two 1's in the number, the calculation can be easily performed.

In case of 3 or more people, it can be done in the same way as mentioned above in the case of sumaki.

(Effects of the Invention) In the present invention, a spatial light modulator having a threshold function for the accumulated amount of input light incident within a finite time is added to the method using polarization and spatial separation encoding and kernel selection. By using it, even complex processing contents can be executed by a processing device with a simple configuration, and there is no inferiority in terms of speed.

It can also handle a considerable amount of calculations and can be used as a semi-general purpose processor.

[Brief explanation of the drawing]

Figure 1 is a conceptual diagram of the configuration of an embodiment of the present invention, Figure 2 (a)
is a block diagram for explaining conventional arithmetic processing, FIG. 2(b) is a block diagram for explaining the arithmetic processing of the present invention, and FIG. 3 is a timing diagram for explaining the operation of the arithmetic processing of the present invention. A diagram showing an example of a chart, FIG. 4 is an explanatory diagram of conventional optical parallel calculation processing. 1-1... Light source 1-2... Polarizer 1-3.
...Pixel mask 1-4...First transmissive spatial modulator 1-5...Circuit for providing first input information to the spatial modulator 1-6...Birefringence plate 1-7. ...Second transmissive spatial modulator 1-8...Circuit for providing second input information to the spatial modulator 1-9...Birefringent plate 1-1O...Kernel 2-
1... Light source 2-2... Polarizer 2-3...
Pixel mask 2-4...First transmission type spatial modulator-5...Circuit for providing first input information to the spatial modulator-6...Birefringent plate 7...Second transmission Type spatial modulator 8...Circuit for providing second input information to the spatial modulator 9...Birefringent plate 2-10...Kernel-11.
...Spatial light modulator 12...Light source-13...Polarization beam splitter

Claims (1)

[Claims] 1. A method for optically encoding one-dimensional or two-dimensional digital information and optically performing a logical operation between a plurality of pieces of digital information, comprising: in an encoding unit, a binary state of each pixel; As a way to express this, we replace the two states with two polarized lights that are perpendicular to each other, and perform encoding to separate the replaced light so that there is no spatial overlap according to the polarization. The separated polarized light in one pixel is replaced with two mutually orthogonal polarized lights according to the binary state of each pixel of digital information that is to be subjected to further calculation processing. After the received light is encoded by dividing one pixel into four positions in total so that there is no spatial overlap according to the polarization, each pixel is divided according to the logic to be operated in the logical operation execution section. A logical operation is performed by selectively extracting only the light at a position that corresponds to the logic of , light intensity, irradiation time,
There is a constant (P_t_h) determined by the wavelength, etc., and for one or more optical inputs input and written into the spatial light modulator within a finite time, the optical intensity of each optical input,
When a constant determined by the irradiation time, wavelength, etc. exceeds the P_t_h, the spatial light modulator modulates the readout light as a response, and does not modulate when the constant does not exceed the P_t_h, or vice versa; In other words, the P_
The output light as a result of the logical operation is configured to drive a writing type spatial light modulator which has a characteristic that when P_t_h is exceeded, the spatial light modulator does not modulate the readout light as a response, but modulates it when the above P_t_h is not exceeded. 1. An optical parallel arithmetic processing method, characterized in that the spatial light modulator is arranged to serve as input light to the spatial light modulator, and a response to the incident light within a finite time to the spatial light modulator is extracted as a computation output. 2. The optical parallel processing method according to claim 1, wherein the logical operation result output light that is spatially encoded and selected according to the logical conversion is subjected to an inverse operation of the spatial separation in the encoding. The position of the emitted light is spatially superimposed on a single light beam in the incident state before encoding,
An optical parallel calculation processing method, characterized in that the superimposed light is input to the spatial light modulator, and the rest obtains calculation results in the same manner as in claim 1. 3. In the optical parallel processing method according to claim 1, the encoding section further repeats the same polarization modulation and spatial separation according to the input of the next stage, and finally if there are N stages, 2N spaces are obtained. As an optical parallel calculation method, the output light is inputted to the optical modulator as the output light of the logical operation result by performing encoding separation at the desired position and then performing the logical operation by selecting it with a spatial selection element. An optical parallel calculation processing method characterized by performing calculations as light. 4. In the optical parallel processing method according to claim 3, after performing the encoding and logical operation between two or more stages without continuing up to N stages, the inverse of the spatial separation in the encoding is performed. Coding is performed by repeatedly performing operations such as spatially superimposing the position of the emitted light onto a single light beam in the incident state before encoding, and then performing further encoding and logical operations. An optical parallel arithmetic processing method characterized by executing logical operations. 5. A light source, a polarizer that polarizes the light from the light source, and the polarized light of the polarizer is orthogonalized to the portion of the light beam corresponding to each pixel in accordance with the binary state of digital information of each pixel. a spatial light modulator that replaces the light with two polarized lights, an optical element that separates the light emitted from the spatial light modulator so that there is no spatial overlap according to the two polarized lights, and spatial separation by the optical element. A spatial light modulator or light valve that selects a subsequent light output in accordance with the processing, the optical writing type spatial light modulator, and an optical element/component that performs a reverse operation of spatial separation to spatially overlap light beams. and a control unit that provides an operation instruction for logical operation processing in the encoding unit and the logical operation execution unit and controls the timing of write light and read light to the spatial light modulator, and a control unit that controls the read timing of the spatial light modulator. An optical parallel arithmetic processing device comprising: a control section for the optical modulator that controls input light to the optical modulator. 6. In the optical parallel processing device according to claim 5, the writing type spatial light modulator is a PIN whose input surface is GaAs.
An optical parallel arithmetic processing device characterized in that a spatial light modulator whose structure and light modulation section are made of ferroelectric liquid crystal is used.