JPH0451292A - Display control circuit - Google Patents

Abstract

PURPOSE:To utilize frame buffers for plural image planes effectively by adding a gradational display control circuit and a display permission/inhibition control circuit to the each frame buffer for plural image planes in a disconnectable state. CONSTITUTION:Image data A6a read out of a frame memory A6 is inputted to a video signal generation part 16 through an AND gate A9 and an OR gate 11 only when display permission A1b indicates logic 1. Image data B7b read out of a frame memory B7 is also inputted to the video signal generation part 16 through an AND gate B10 and the OR gate 11 only when display permission B1c indicates logic 1. A display address control part 3 and a data rewrite address control part 4 assign the frame memory A and B in a continuous address space, display data are written, and the display permission A1b and display permission B1c are set to logic 1 at the same time. Consequently, continuous data of two image planes can be displayed while scrolled up and down by varying the display start address.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a circuit for controlling a simple display for displaying a seal impression, etc. II.This invention relates to a display control circuit suitable for switching and using several screen display modes.

[Conventional technology]

When performing monochrome gradation display in a conventional display control circuit, as described in Japanese Patent Laid-Open No. 62-200394, it has two frame buffers, and one frame buffer stores basic image data. Then, there is a method that converts the gradation of this signal and writes it to the other frame buffer for display, or a method that performs a logical operation from the color signal to generate a brightness modulation signal and display it in a monochrome gradation, as described in Japanese Patent Laid-Open No. 62-244090. There are methods for displaying gradations, but each method has a frame buffer for multiple screens, but this is used only for gradation display, so the frame buffer for gradation display is effective when not performing NtA display. No consideration was given to the means to be used.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not take into consideration the means to effectively utilize the frame buffer for gradation display when displaying a screen that does not display gradation, and if the system is operated without using gradation display, There has been a problem in that the frame buffer for gradation display cannot be effectively used for other purposes, such as being used as a frame buffer for separate or continuous screens. The purpose is to add a gradation display control circuit and a display permission/inhibition control circuit to each in a detachable manner, and to effectively utilize frame buffers for multiple screens depending on the operating form of the system.

[Means to solve the problem]

In order to achieve the above purpose, display is enabled/disabled in units of multiple frame memories that store one screen's worth of display data, and display permission signals output by the display control unit that controls the frame memories. A circuit that performs
It has a circuit that gives different brightness to the data in each frame memory according to the gradation display instruction signal outputted by the display control unit, and the address space of multiple frames of frame memory can be set to the same address or the same address, depending on the system operation mode. Or, by allocating it to another consecutive address space and further controlling the combination of the display permission signal and the gradation instruction signal, it is possible to effectively utilize the frame memory on multiple sides for multiple purposes.

[Effect]

The address space of the frame memory for multiple screens is controlled by the address control unit, and the data read out for one display is given permission/disallowance for one display, brightness information for gradation display, and independent display. , or continuous display of separate screens or gradation display. As a result, complicated timing control is not required for memory access during data rewriting, and control such as memory contention is not required for memory access during display, and malfunctions do not occur.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 1 to 6, taking as an example a case in which a frame memory is provided for two screens.

Figure 1 shows the 9-display control section (1) showing the circuit configuration of this embodiment.
The address spaces of frame memory A (6) and frame memory B (7) controlled by the display address control unit (
3) and the data rewriting address control unit (4),
As shown in FIG. 2, they can be allocated to consecutive address spaces or to the same address space. Image data A (6a) read from frame memory A (6) is 1 display permission A (1
Only when b) is logical 1, the signal is input to the video signal generation section (16) through the AND gate A (9) and the OR gate (11). Image data B (7b) in frame memory B (7)
Similarly, only when the display permission B (lc) is logic 1, the signal is input to the video signal generation unit (16) through the AND gate B (10) and the OR gate (11). Also, N tone display instruction (
If 1d) becomes logical 1, display permission A (lb),
Regardless of display permission B (lc), frame memory A (
Image data A (6a) read from frame memory B (7) passes through oven collector gate A (13) and becomes normal luminance data, and image data B (7a) read from frame memory B (7) passes through oven collector gate A (13). Gate B (14)
The current passes through the current limiting resistor (15) and becomes low brightness data. By wire-ORing this, frame memory A (
6) Depending on the presence or absence of data in frame memory (B),
No brightness, low brightness, normal brightness.

The video signal generation unit (16) generates four types of high-luminance image data.
can be input to.

Next, a specific display example will be explained using figures. If the data in frame memory A (6) and frame memory B (7) is treated as data for two consecutive screens without performing one gradation display first, display address control section (3), data rewriting address control Part (4) allocates frame memories A and B to consecutive address spaces, writes display data, and sets display permission A (lb) and display permission B (lc) to logic 1 at the same time.As a result, the table in FIG. As shown in the example, by changing the display start address, continuous data for two screens can be displayed while scrolling up and down.

In addition, the display address control unit allocates the address spaces of frame memories A (6) and B (7) to the same space only in the case of 5 displays, and controls the display permissions A (lb) and B (lc). It is also possible to perform a window display as shown in FIG. 4 or a superimposed display of two screens as shown in FIG.

Furthermore, when performing gradation display, the display address control section (
3) The data rewriting address control unit (4) allocates frame memories A (6) and B (7) to the same address space, sets the gradation display instruction (1d) to logic 1, and sets data write permission A (5a). , B (5b), the frame memory A (
6) If you write data only to normal brightness, frame memory B
If you write data only in (7), the brightness will be low and the frame memory A (
6) and B(7), it is possible to display the data as high brightness data.

When performing this operation using the conventional technology, frame memory A
It was necessary to have frame memory for a total of 4 screens, with (6) dedicated to normal brightness for 2 screens and frame memory B (7) dedicated to low brightness for 2 screens, but with this method's display address control. By adding the section (3) and the data rewrite address control section (4), NvI4 display and continuous data display (scrolling) on two screens are possible with half the memory capacity of the conventional one.

As described above, according to the mainstream example, in a simple display device, the frame memory can be used effectively in accordance with the operating form of the system, and various types of display can be performed.

Furthermore, similar effects can be obtained in color display control by using the same control as in this embodiment, by having frame memory for three or more screens, and replacing the part that provides luminance information in the gradation display section with color information.

〔Effect of the invention〕

According to the present invention, the frame memory for multiple sides can be independently and
Alternatively, it can be used for both continuous separate screen display and gradation display, and the frame memory can be used effectively according to the system operation mode, making it a cost-effective solution suitable for controlling simple displays. This has the effect of enabling high-level display control.

[Brief explanation of drawings]

Fig. 1 is a circuit configuration diagram of an embodiment of the present invention having a frame memory for two screens, Fig. 2 is a diagram showing a memory map of the frame memory for two screens, and Fig. 3 is a diagram showing a frame memory for two consecutive screens. Figure 4 is a diagram showing an example of scroll display, Figure 4 is a diagram showing an example of window display for two independent screens, Figure 5 is a diagram showing an example of overlapping display of two independent screens, and Figure 6 is a diagram showing an example of gradation display. FIG. 1...Display control section, 2...Address control section, 5.Data control section, 6.Frame memory A, 7..Frame memory B, 8..Display permission/prohibition control section, 12..Floor Adjustment display control section. Figure tree collection map

Claims (1)

[Claims] 1. In a circuit that controls a display that displays characters and figures, there are multiple frame memories that store display data for one screen, a display control unit that controls the frame memories, and writing data to the frame memories. a data control unit that controls permission/prohibition; and a display screen switching unit that individually controls display permission/prohibition for each of the plurality of frame memories based on a display permission signal output from the display control unit;
By the gradation display instruction signal output from the display control section,
It consists of a gradation display control that adds luminance information to each frame memory of multiple planes, and a gradation display control that adds brightness information to each frame memory of multiple planes. Frame memory of minutes (n screens) allows independent or continuous display of n screens and 2^n
A display control circuit that is characterized by the ability to achieve both gradation display.