JPH0451565A - Semiconductor memory device and its manufacture - Google Patents

Abstract

PURPOSE:To eliminate the generation of a crosstalk to adjacent bits or other elements and to enhance relaibility by a method wherein, at a memory cell structure for a DRAM, a channel of a MOSFET as a switching transistor protrudes on a substrate. CONSTITUTION:This DRAM is constituted of the following: a MOSFET formed on a high-resistance p-type silicon substrate 1; and a capacitor formed by using its drain 4 as a lower-part electrode and by laminating a capacitor insulating film 8 and an upper-part electrode metal 9. The MOSFET is constituted of the following: an n<+> diffusion layer 2, as an n-type source region, which is formed inside the substrate 1; a p-type single-crystal silicon layer 3, as an n- channel region, which is formed selectively on the layer; a gate insulating film 5 which is formed so as to go over the side face of the silicon layer 3 from the surface of the substrate up to one part on the surface and which is composed of a silicon oxide film; a gate electrode 6 which is formed on it and which is composed of a polycrystalline silicon film; and the n<+> type polycrystalline silicon layer 4, as a drain region, which is formed so as to come into contact with the silicon layer 3 and so as to cover the gate electrode 6.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor memory device and a method for manufacturing the same;
In particular, the present invention relates to a dynamic RAM (DRAM) in which a memory cell is composed of a MOSFET and a MOS capacitor.

(Prior Art) In recent years, with advances in semiconductor technology, particularly advances in microfabrication technology, DRAMs are also rapidly becoming more highly integrated and have larger capacities.

As integration increases, the area of capacitors that store information charges decreases, resulting in serious problems such as erroneous reading of memory contents or soft errors in which memory contents are destroyed by A-rays, etc. It has become.

To solve this problem, for example, in 4M to 16M class DRAM, element isolation grooves are formed in the semiconductor substrate.
A technique has been proposed for forming a capacitor and a MOS transistor in the trench.

An example of such a RAM structure is shown in FIG.

This DRAM is constructed by forming a transistor 41 on the upper side wall of a trench that is formed running vertically and horizontally on the surface of a p-type silicon substrate 40 by anisotropic etching, and a trench capacitor 42 at the bottom of the trench. be.

That is, the lower sidewall and bottom of the trench are covered with a capacitor insulating film 43, and the inside thereof is filled with an n-type doped polycrystalline silicon layer 44, and a portion of this polycrystalline silicon layer 44 is covered with the substrate 40. I am in contact with.

In addition, the transistor 41 uses the polycrystalline silicon layer in contact with the substrate 40 as a source 47, the n medium diffusion layer formed on the substrate surface as a drain 48 (bit line), and the upper side wall of the trench and the drain 48 (bit line). The insulating film covering the bottom is a gate insulating film 45, and a gate electrode 46 (
word lines). Here, 49 is an element isolation region.

In such a RAM structure, the channel of the transistor is formed on the surface of the substrate 40 along the sidewall of the insulating film 45 of the vertical transistor 41, and the MOS capacitor and MOSFET are stacked vertically in the trench to form an integrated structure. , the area occupied by the memory cell is small, and high integration is possible.

In the transistor formed in this way, the elements are separated on the surface by the element isolation region 49, but they are separated in the deep part of the substrate, and there is a problem of crosstalk during operation of the element. . This crosstalk is, for example, a bunch-through phenomenon that occurs during the operation of two elements, or a current leakage to the other that occurs when only one element is in operation.

Furthermore, since the channel of this transistor is formed on the substrate side of the sidewall of the gate, there is also the problem of soft errors occurring due to irradiation with alpha rays.

Furthermore, since the structure is such that contact is made from the capacitor at the bottom of the groove, manufacturing is more or less complicated.

FIG. 8 shows the results of examining the threshold voltage of each transistor formed in this manner as characteristic value data. Here, the horizontal axis is the threshold voltage, and the vertical axis is the number of elements. From this figure, it can be seen that ±0.15V is centered around the threshold voltage of 0.75V.
It can be seen that there is a wide variation in distribution within the range of V.

(Problems to be Solved by the Invention) As described above, in the conventionally proposed cell structure in which capacitors and MOS transistors are vertically stacked in a trench, there is a problem of crosstalk or soft errors caused by alpha ray irradiation. In addition to the problem of generation, variations in device characteristics tend to occur, and these have become major problems that hinder high integration.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a DRAM that is easy to manufacture and has high reliability.

[Structure of the invention]

(Means for Solving the Problems) Therefore, in the present invention, in a stacked DRAM formed by stacking a canister on top of a MOSFET, this MOS
In an FET, a first conductivity type diffusion layer formed on the surface of a semiconductor substrate serves as either a source or a drain, a second conductivity type semiconductor layer grown on the surface of the diffusion layer serves as a channel layer, and this channel A capacitor, in which a gate insulating film and a gate electrode are formed on at least the side surfaces of the layer, the other one of the source or the drain is formed in the upper layer so as to be in contact with the channel layer, and the lower electrode of the capacitor is formed in the upper layer. We are trying to form a

Preferably, the gate electrode is formed so as to extend from the side surface to the top surface of the channel layer, and the other one of the source and drain formed in the F layer is in contact with the channel layer and is connected to the channel layer through an interlayer insulating film. It is formed so as to cover the upper surface of the gate electrode.

Furthermore, in the method of the present invention, after selectively impurity diffusion is performed on the surface of a semiconductor substrate of a first conductivity type to form a diffusion layer of a second conductivity type that will become a source region, the surface of this diffusion layer is first epitaxially grown. A silicon layer is selectively formed and recrystallized to form a single crystal silicon layer as a channel region.

(Function) In the memory cell structure of the DRAM of the present invention, the channel of the MOSFET as a switching transistor has a structure that protrudes above the substrate, and there is almost no occurrence of crosstalk with adjacent bits or other elements. .

Therefore, since it is not necessarily necessary to perform element isolation, it can be said that the structure is particularly suitable for high integration.

Furthermore, since the MOSFET is a vertical type, the occupied area is significantly reduced, and since the channel is formed from a region formed by selective growth, it is possible to maintain high dimensional accuracy.

In addition, the channel length is determined by the thickness of the single-crystal silicon layer formed by selective growth and the distance to the electrode on the top surface of this layer, and since both can be controlled with high precision, variations in device characteristics can be greatly reduced. It can be reduced.

Furthermore, since solid phase growth is used to form the channel, it can be formed without imparting significant thermal history to the underlying semiconductor element region.

In addition, the capacitor connects the drain region of the MOSFET,
By forming the capacitor on the step from the channel region through the side surface of the gate electrode to the top surface of the gate electrode, it is possible to take advantage of the step of the gate electrode to increase the surface area and increase the capacitance of the capacitor. can. This can be said to be a particularly effective structure when miniaturization progresses and the capacitor area in the vertical direction makes a large contribution to the capacitor capacity.

Further, according to the method of the present invention, since the channel region is formed in a self-aligned manner with the source region, the mask alignment process is reduced, and a fine and highly accurate DRAM can be easily formed.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1(a) shows a DRAM according to an embodiment of the present invention.
Figure 1 (b) is a perspective view showing 2 bits of the same DRA.
The plan view of M and FIG. 2 are its equivalent circuit diagrams.

This DRAM is a MOSFET in which only an n+ diffusion layer 2 as a source region is formed in a high-resistance p-type silicon substrate 1, and a channel region 3 and a drain are formed on the surface of the substrate. A capacitor is formed by stacking a capacitor insulating film and an upper electrode, with the capacitor serving as a lower electrode.

This MOSFET has an impurity concentration of, for example, 3 as an n-type source region formed in a high-resistance p-type silicon substrate 1.
n medium scattering layer 2 with a depth of 0°3 to 05 μm and a film thickness selectively formed on this upper layer]
, 0pIIl p-type impurity concentration 3 x 1.016 cm-3 as a channel region, and a p-type monocrystalline silicon layer 3 formed from the substrate surface to cover a part of the top surface of this n-type single crystal silicon layer beyond the side surfaces. A gate insulating film 5 made of a silicon oxide film with a thickness of 320 nm and a gate electrode 6 made of a polycrystalline silicon film with a thickness of 3250 nm formed on this layer, and an n-type single crystal 2932 nm formed on this upper layer. layer 3
A film with a thickness of 0.5 μm and an impurity concentration of 3.2×1020 CI11″′3 was formed so as to be in contact with and cover the gate electrode 6.
and an n-medium polycrystalline silicon layer 4 as a drain region. Note that a silicon oxide film as an interlayer insulating film 7 is interposed between the gate electrode 6 and the n medium polycrystalline silicon layer 4 as a drain layer. Furthermore, the above-mentioned diffusion layer 5 is a bit line, as shown in FIG. 1(a).
A drawer section is provided extending from the front of the page or the back side of the page.

The capacitor uses an n+ type polycrystalline silicon layer 4 as a drain layer as a lower electrode, and a capacitor insulating film 8 made of a silicon oxide film with a thickness of 150 Å is formed by this and an upper electrode 9 made of, for example, a polycrystalline silicon layer. This is what happens.

A bit line (not shown) made of a polycrystalline silicon film, an aluminum film, or the like is provided so as to be in contact with the source region (diffusion layer 5) of the MO5FET. In addition, a word line (not shown) made of a polycrystalline silicon film or an AJ film is also provided at the gate electrode portion of the MOSFET.
is installed.

Next, a method for manufacturing this DRAM will be explained.

FIGS. 3(a) to 3(h) are perspective views showing the manufacturing process of this cell.

First, as shown in FIG. 3(a), a film with a thickness of 5.2 μm was deposited on the surface of a p-type silicon substrate 1 with a specific resistance of about 5 Ωcm using the CVD method.
m silicon oxide 3] was deposited, and by photolithography,
This was patterned to a depth of 5 μm and an opening of 1. OXl
, I) forming an opening 32 of μI+12;

Using this silicon oxide film 31 as a mask, arsenic ions are implanted at an acceleration voltage of 70 KV and a dose of 5.times.10@15 cm@-2 to form an impurity diffusion layer 2 serving as a source within this opening 32.

Next, as shown in FIG. 3(c), a p-type amorphous silicon layer with a thickness of 1.0 μm is selectively grown on the impurity diffusion layer 2 exposed in the opening 32, and this is formed into a solid phase. A p-type crystalline silicon layer 3 is formed by recrystallization using a growth method. The growth conditions at this time were disilane gas as a reactive gas, a deposition temperature of 580° C., and annealing conditions for single crystallization at 600° C. in an N2 atmosphere.

Subsequently, as shown in FIG. 3(d), the silicon oxide film 31 is removed by etching using buffered hydrofluoric acid.

Thereafter, as shown in FIG. 3(e), thermal oxidation is performed at 850° C. to form 98 silicon oxides 5n on the substrate surface.

Further, a doped polycrystalline silicon layer with a thickness of 3250 μm, which will become the gate electrode, is deposited on this upper layer by the CVD method, and patterned by photolithography to form the gate electrode 6 and the gate insulator, as shown in FIG. 3(r). A film 5 is formed.

Here, the polycrystalline silicon layer is formed by adding an impurity such as phosphine to a reactive gas so that it is doped to an n-type at the same time as it grows.

Then, as shown in Figure 3(g), 850'C8
Thermal oxidation is performed for 0 minutes, and the entire surface is etched to expose the surface of the p-type earth crystal silicon layer 3. Since the n-polycrystalline silicon layer constituting the gate electrode is highly doped, the oxidation rate is significantly higher than that of the single-crystalline silicon layer 3, and a thick film is formed. Therefore, when the entire surface is etched to expose the surface of the single crystal silicon layer 3, the upper and side surfaces of the gate electrode have a sufficient thickness (3
25 people) remains.

After that, as shown in FIG. 3(h), shallow ion implantation is performed to make the surface of the single crystal silicon layer 3 n+, and then CVD
An n-type polycrystalline silicon layer 4 is deposited by a method and patterned by photolithography. This n+ type polycrystalline silicon layer 4 serves as a drain region and a lower electrode. At this time, this n-shaped polycrystalline silicon layer 6 is
The impurity concentration is set to, for example, about I x 10 "Cm-'.

Then, on this upper layer, a capacitor insulating film 8 having a laminated structure of about 150 silicon nitride films and silicon oxide films is formed. Next, an upper electrode 9 made of a polycrystalline silicon film is embedded in this upper layer. Specifically, a phosphorus-topped polycrystalline silicon film is deposited to a thickness of approximately 600 nm, and this is etched by an RIE method containing CF4 gas to pattern it into a desired shape. Here, as the capacitor insulating film, in addition to the laminated structure of silicon nitride film and silicon oxide film, Ta
In addition to a metal oxide film such as 205, a thermal oxide film, a silicon nitride film, a combination thereof may also be used.

In this way, the DRAM shown in FIG. 1 is completed.

FIG. 4 shows the results of examining the threshold voltage of each transistor formed in this manner as characteristic value data. Here, the horizontal axis is the threshold voltage, and the vertical axis is the number of elements. From this figure, it can be seen that there is almost no variation around the threshold voltage of 0.7V, and that the variation in device characteristics is significantly improved compared to the conventional transistor shown in FIG.

The DRAM thus formed has a structure in which the channel of the MOSFET as a switching transistor protrudes above the substrate, and there is almost no crosstalk with adjacent bits or other elements.

Further, since the MOSFET is vertical, the occupied area is significantly reduced, and since the channel is formed from a region formed by selective growth, high dimensional accuracy can be maintained.

Furthermore, the capacitor connects the drain region of the MOSFET,
This drain region, which serves as a lower electrode and is formed on the MOSFET, is formed on a step so as to extend from the channel region through the side surface of the gate electrode to the upper surface of the gate electrode.

Therefore, by utilizing the step of the gate electrode, the surface area can be increased, and the capacitance of the capacitor can be increased. This can be said to be a structure particularly suitable for miniaturization.

In addition, the channel length is determined by the thickness of the single-crystal silicon layer formed by selective growth and the distance to the electrode on the top surface of this layer, both of which can be controlled with high precision, significantly reducing variations in device characteristics. can do.

Furthermore, since no element isolation region is required, it can be said that the structure is particularly suitable for high integration.

In addition, since solid-phase growth is used to form the channel,
It can be formed without imparting significant thermal history to the underlying semiconductor element region.

In the above embodiments, the channels were selectively formed by in-phase growth, or selective CVD, laser annealing, or other methods may be used.

Further, although not described in the embodiments, it can be easily integrated with other elements.

Furthermore, in the embodiment described above, no element isolation region was formed, or as another embodiment of the present invention, as shown in FIG. A DRAM may be formed by similarly forming an epitaxial growth layer using a selective CVD method using , disilane, or the like as a reactive gas.

In this case, the element isolation region is divided and the occupied area is inevitably increased slightly, but the element isolation is complete.

Furthermore, in the above embodiment, the gate electrode was formed so as to cover a part of the upper surface of the single crystal silicon layer 3 forming the channel, but as shown in FIG. The gate electrode may be formed only on the top surface, and the drain region may occupy almost the entire top surface.

This makes it possible to achieve even higher integration.

In addition, in the embodiment described above, a DRAM having an n-channel type FET has been described, but it goes without saying that the present invention is also applicable to a DRAM having a p-channel type FET.

〔Effect of the invention〕

As described above, according to the present invention, a first conductivity type diffusion layer formed on the surface of a semiconductor substrate is used as either a source or a drain, and a second conductivity type diffusion layer grown on the surface of the semiconductor substrate is used as either a source or a drain. The semiconductor layer of is used as a channel layer, a gate insulating film and a gate electrode are formed on at least the side surfaces of this channel layer, the other one of a source or a drain is formed on this upper layer so as to be in contact with the channel layer, and further, this upper layer. Since a capacitor is formed using this as the lower electrode of the capacitor, there is almost no crosstalk with adjacent bits or other elements, and variations in element characteristics can be significantly reduced. This makes it possible to achieve a high degree of miniaturization.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a DRAM according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of the same DRAM, and FIGS. 3(a) to 3(h)
4 is a diagram showing the manufacturing process of the DRAM, FIG. 4 is a diagram showing the results of measuring variations in characteristics of the DRAM, FIGS. 5 and 6 are diagrams showing other embodiments of the present invention, and FIG. 8 is a diagram showing a conventional DRAM, and FIG. 8 is a diagram showing the results of measuring variations in characteristics of the conventional DRAM. 1...p-type silicon substrate, 2...n medium scattering layer (SOS region), 3...p-type silicon layer (channel covering area) 4...
・n polycrystalline silicon layer (drain/capacitor electrode)
, 5... Kate insulating film, 6... Kate insulating film, 7...
Interlayer insulating film, 8... Capacitor insulating film, 9... Capacitor electrode, 2o... Field insulating film, 31... Silicon oxide film, 32... Opening.

Claims (3)

[Claims] (1) a source region made of a first conductivity type diffusion layer formed on the surface of the semiconductor substrate; a channel layer made of a second conductivity type semiconductor layer grown on the surface of the diffusion layer; and the channel layer. A MOSFET comprising a gate insulating film and a gate electrode formed to cover at least side surfaces of the channel layer, and a drain region formed to be in contact with an upper surface of the channel layer, and the drain region of the MOSFET is used as a lower electrode of a capacitor. , a capacitor comprising a capacitor insulating film and an upper electrode sequentially laminated thereon. (2) The gate electrode is formed to extend from the side surface to the upper surface of the channel layer, and the drain region is formed to be in contact with the channel layer and to extend over the upper surface of the gate electrode via an interlayer insulating film. The semiconductor memory device according to claim 1, characterized in that: (3) a diffusion step of selectively diffusing impurities into the surface of the semiconductor substrate of the first conductivity type to form a diffusion layer of the second conductivity type that will become a source region; and selectively diffusing impurities onto the surface of the diffusion layer by epitaxial growth. a channel region forming step in which a silicon layer is formed and recrystallized to form a single crystal silicon layer as a channel region; and after the surface of the single crystal silicon layer is oxidized to form a silicon oxide film, a polycrystalline silicon layer is formed. form,
After patterning these to form a gate insulating film and a gate electrode, and performing surface oxidation, the entire surface is etched to expose the surface of the channel region and leave a silicon oxide film around the gate electrode. an interlayer insulating film forming step, a drain region forming step of forming a polycrystalline silicon layer constituting a drain region in contact with the exposed channel region, and forming a capacitor insulating film and an upper electrode in an upper layer of the drain region. 1. A method of manufacturing a semiconductor memory device, comprising: a capacitor forming step of forming a capacitor.