JPH0451849B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a cross-call control system,
In particular, the present invention relates to a cross-call control system in which devices such as magnetic disk drives are controlled by a plurality of control devices.

[Background of the invention]

FIG. 2 shows the system configuration of a conventional magnetic disk device. Here, 1a and 1b are central processing units (hereinafter referred to as CPU), 2a and 2b are disk control units (hereinafter referred to as DKC), 3a and 3b are connection devices (hereinafter referred to as DSC), and 4-0 to 4-n. is a magnetic disk unit (hereinafter referred to as DKU).
Further, FIG. 3 shows the device occupancy of the data path and the selection response in the cross-call control shown in FIG. 2. This will be explained below with reference to FIGS. 2 and 3.
When executing data read/write operations to DKU4-0 according to instructions from CPU1a,
Prior to a series of operation instructions associated with reading/writing data, the DKC2a sets the bit corresponding to DKU4-0 in the assign register 7a that stores control information for DKU4-0 to DKU4-n in the cross-call control section 5a of the DSC3a. and then reset after the data read/write operation is completed. Also,
When the CPU 1a wants to occupy DKU4-0 for the CPU 1b (reserve instruction), it sets the bit corresponding to DKU4-0 in the assign register 7a for the DSC 3a through the DKC 2a, as described above. In this case, CPU1a is DKC2b, DSC
Although operations such as reading/writing data to DKU4-1 to DKU4-n can be performed arbitrarily through DKU4-1 to DKU4-n through 3b, similar operations to DKU4-0 are not possible because the bit of DKU4-0 in the assign register 7a is set. DKC2b, CPU through line 6
It is reported to 1b as long busy and informed that it is unusable. After that, when the bit corresponding to DKU4-0 of the assignment register 7a of the CPU 1a is reset, the signal line 6 is set on the CPU 1b side.
BUSY TO by pole sequence via
Free interrupt is detected and DKU4-0 can be used. During this unusable period, CPU1a,
This is determined by the processing content of the CPU1b program, and generally lasts from several μs to several hours.
The time is not regulated by a, 2b, DSC3a, 3b. There are also instructions for the DSCs 3a and 3b and control instructions for the DKUs 4-0 to 4-n without setting the assignment registers 7a and 7b, but normally in such cases the operation is completed in a short time of about a few μs. Treated as short busy. For example, CPU1a, DKC2a
If DKU4-0 is activated from CPU1b and DKC2b while it is operating without setting the bit of assign register 7a corresponding to DSC3a for DKU4-0, DKC2b connects signal line 6 and DSC3b.
Receive reports of shoot-busy through. When receiving short-busy, the DKC 2b repeats the restart operation and time count operation through a selection routine loop until short-busy is released. This time count operation will be executed by DSC if shot busy is not canceled after a certain period of time has elapsed.
It is assumed that 3a or 3b is abnormal and a time over error is reported to the CPU 1b.

Conventionally, in addition to the assignment registers 7a and 7b, the cross call control units 5a and 5b have NOT
A patch register (not shown) for READY TO READY interrupts, a device end register (not shown) for BUSY TO FREE reporting, a reserve register (not shown) for DKU reservation, etc.
Units are easy.

In recent years, in order to further increase the usage efficiency of DKU4-0 to 4-n, CPU1a and
DKC2b, CPU1b and DKC2a paths are now used to perform control that enables dynamic path connection and disconnection through program control.

For example, this type of method is
It is described in Publication No. 146941. This is the CPU
DKU4-0 through 1a, DKC2a, DSC3a
After the seek operation command for CPU1a, DKC2
When a is executing a data read/write operation to DKU4-1, the seek completion report for DKU4-0 is sent to CPU1a, DKC2b, and DSC.
This was made possible through the pass of 3b. Therefore, in addition to the above-mentioned registers, the cross-call control units 5a and 5b
Channel group configuration and identification of CPU1a and 1b,
The amount of information for exclusive control, etc. has increased significantly, and several kilobytes of RAM8a, 8b are required to store this information.
began to be used. Reading/writing of information from the CPU 1a and DKC 2a to the RAMs 8a and 8b is performed simultaneously for reliability and system program operation. That is, the instructions of CPU1a or CPU1b are executed to DKC2a, DSC3a or DKC2b, DSC3b,
Reading/writing of information in RAMs 8a and 8b is performed simultaneously, and the read contents of RAMs 8a and RAM 8b are compared and confirmed to check whether the operations have been completed normally.

In such a conventional method, RAM8a, 8b
When the DKC2a, 2b and DSC3a, 3b were in a short busy state during a read/write operation, the connection was established by restarting the DKC2a, 2b, so as the short busy state increased, the connection waiting time increased. There was a problem.

[Purpose of the invention]

The purpose of the present invention is to improve the above-mentioned conventional problems, and to provide a cross-call control system capable of dynamic path control, which reduces connection waiting time due to an increase in short busy states and improves equipment usage efficiency. The purpose is to provide a control system.

[Summary of the invention]

To achieve the above object, the present invention provides a cross-call control system that connects/disconnects a bus between a disk control device and a connected device according to the usage status of the disk device, in which cross-call control information is stored in each connected device. A memory is provided and the connected devices are connected so that the memories in each connected device can be accessed mutually. When one disk controller is connected to one connected device, the memory of that connected device is accessed from the other connected devices. When access is being made from the device, the disk control device is kept connected to the above-mentioned connected device, and after access to the memory is released, the disk control device that was on standby executes a control operation to the disk device. There are certain characteristics.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a partial configuration diagram of a cross-call control system showing an embodiment of the present invention. This is an improved version of the connecting devices 3a and 3b shown in FIG. 2, and since the other configurations are the same as those shown in FIG. 2, this is used.

In Figure 1, 9 is a decoding circuit that decodes instructions from DKC2a and 2b, and 10 is RAM8.
a, 8b (hereinafter referred to as memory) (hereinafter referred to as memory), a short-busy operation detection circuit detects an instruction that requires reading/writing; 11 is a memory read/write circuit;
An AND circuit that waits for writing, 12 is an operation circuit 1 that reads/writes the memory.
3 is a signal line that informs that system A is in the short busy state, 14 is an interlock circuit that interlocks the operation circuit of one system, and 15 is an invert circuit that inverts the detection signal of the short busy operation circuit 10 to the other system. be. Here, a is added after the symbol for the circuit of system A, and system B
The circuit shown in is marked with b after the symbol.

The same applies to the case of system B, which will be described below regarding the case where the execution command comes first to system A (DSC 3a).

Instructions from the DKC 2a are obtained by decoding the TAG line and BUS line input to the decoding circuit 9a of the DSC 3a, but instructions requiring memory read/write are detected by the short busy operation detection circuit 10a. , is sent to the DSC 3b via the signal line 13. At this time, DSC3
When an instruction that requires memory read/write comes to b, the AND circuit 11b causes TAG
Since the GATE signal is inhibited (waiting state), the operation circuit 12b does not operate.
In other words, DSC3b is in a waiting state, which is
This continues until the memory read/write operation of the DSC 3a is completed, that is, while the signal line 13 is ON. When the signal line 13 is turned off, the operation circuit 12b of the DSC 3b starts a memory read/write operation.

If a memory read/write command comes to DSC3a and DSC3b at the same time, both systems will use TAG.
GATE signal may not be input.
In this case, the interlock circuits 14a and 14b operate the isolation circuit of one system preferentially and inhibit the other system (wait state), thereby prohibiting the DSCs 3a and 3b from performing memory read/write operations at the same time. .

If the above circuit configuration is adopted, DSC3a,
No matter what timing a memory read/write command is issued to 3b, by placing one system in an instruction execution wait state, only one system's instructions can be executed.

In this way, according to this embodiment, when the shot is busy as in the conventional case, the DKC2a, 2b and the DSC
When disconnecting 3a and 3b and waiting in the DKC2a and 2b startup sequence loop to restart, check the response time, cable delay time, and signal confirmation when disconnecting and connecting both DKC2a and 2b and DSC3a and 3b. If you add the waiting time of , it becomes several μs to several tens of μs. DSC3a, 3 from DKC2a, 2b
RAM once in the operation sequence for b
Since the read/write operation for 8a and 8b is about 1 μs, that is, the short busy waiting time of this embodiment is about 1 μs, the efficiency of use of the DKU is improved.

〔Effect of the invention〕

As described above, according to the present invention, in a cross-call control system that can perform dynamic path control, it is possible to reduce the connection waiting time associated with an increase in short busy states and improve device usage efficiency.

[Brief explanation of the drawing]

FIG. 1 is a partial configuration diagram of a cross-call control system showing an embodiment of the present invention, FIG. 2 is a configuration diagram of a cross-call control system of a conventional magnetic disk device, and FIG. 3 is a diagram showing device occupancy and selection of data paths. It is a figure showing a response. 1: CPU, 2: DKC, 3: DSC, 4: DKU,
5: Cross call control section, 7: Assign register, 8: RAM, 9: Decode circuit, 10: Short busy operation detection circuit, 11:
AND circuit, 12: Operation circuit, 14:
Interlock circuit, 15: Invert circuit.

Claims (1)

[Scope of Claims] 1. A disk drive system that includes a plurality of disk devices, a plurality of disk control devices that control the disk devices, and a connection device that connects the disk devices and the disk control device, and that In a cross-call control system that connects/disconnects the bus between the disk control device and the connection device using The memories in the connected devices are made mutually accessible, and when the one disk control device is connected to the one connected device and the memory of that connected device is accessed by another connected device, the above A cross call characterized in that a disk control device is kept on standby while connected to the connection device, and after access to the memory is released, a control operation is executed from the disk control device that has been on standby to the disk device. control system.