JPH0452050B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital synchronous detection relay.

In a digital protective relay that performs power system protection calculations using digital quantities, one of its protective functions is to monitor the synchronization status between two systems by comparing the voltages of both systems, and to detect an out-of-synchronization There is a synchronization detection process that determines the system position and takes measures to trip the disconnector. As shown in the characteristic diagram in Figure 1, a relay with this synchronization detection function detects whether the phase difference between one voltage V ₁ and the other voltage V ₂ is within the range of the judgment angle ±θ ₀ . Synchronous detection is performed depending on the method. For this synchronous detection, both system voltages V ₁ and V _2
The setting value K (=
cosθ ₀ ), it is determined that cosθ≧K ……(1), and in practice, the vector inner product of voltages V ₁ and V ₂ is calculated and the set value is calculated as shown in equation (2) below.
This was due to the size comparison with KV ₁ and V ₂ .

V ₁ V ₂ cosθ≦KV ₁ V ₂ ...(2) By the way, in order to acquire system voltage and current data in a digital protective relay, as shown in Fig. 2, an analog signal ( In the figure, the voltages V ₁ , V ₂ ) are sampled at a constant period by sample-and-hold circuits 1 ₁ , 1 ₂ , and the sample values are sequentially taken into an analog-digital (A/D) converter 3 by a multiplexer 2 . Using the digital signal converted by the converter 3, a digital protection calculation device 4 such as a microcomputer performs protection calculation. The synchronization detection relay obtains an output indicating the presence or absence of synchronization as a result of the protection calculation. In this digital protection relay, there is a quantization error associated with sampling, and this error and the conversion error of the A/D converter 3 appear as an error in the protection calculation. In a synchronous detection relay, the judgment angle θ ₀ is generally set to 0° to 30°, and the calculated value cosθ and setting value K
Since (cosθ ₀ ) is relatively small, the above-mentioned quantization error,
There was a problem that the ratio to the conversion error became small and the judgment accuracy deteriorated. For example, at θ ₀ = 10° and θ ₀ = 15°, the left side of equation (2) above, V ₁ V ₂ cos θ, has a value of about 2%.
There is only a change of , and if the setting increments are set at 1° intervals, it becomes impossible to judge.

An object of the present invention is to provide a synchronous detection relay that can perform synchronous detection with high accuracy even if the phase difference θ between two voltage detection signals is small.

FIG. 3 is a block diagram showing an embodiment of the protection arithmetic device according to the present invention. Voltage detection signal V ₁ ,
V ₂ is input to the vector inner product calculation unit 5, and the vector inner product V ₁ V ₂ cosθ is calculated. On the other hand, the signal V ₂ is also input to the phase shifter 6 and phase-shifted by 90 degrees in electrical angle. The phase shift signal V ₂ e ^-j90 ° of this phase shift section 6 and the signal
V ₁ is input to the vector inner product calculation unit 7 to perform a vector inner product calculation, which is the calculation of V ₁ V ₂ sinθ. The calculation results of calculation units 5 and 7 are converted into absolute values by absolute value calculation units 8 and 9, respectively.
V ₁ V ₂ cosθ|, |V ₁ V ₂ sinθ| are applied. The output |V ₁ V ₂ sin θ| of the calculation unit 9 is multiplied by a set value −K in the multiplication unit 10 . The multiplication result -K|V ₁ V ₂ sin θ| of the multiplication unit 10 is added or subtracted from the output |V ₁ V ₂ cos θ| of the absolute value calculation unit 8 in the addition unit 11. The addition result |V ₁ V ₂ cosθ|−K|V ₁ V ₂ sinθ| of the addition unit 11 is determined to be positive or negative by the positive/negative determination unit 12.
On the other hand, the calculation result of the vector inner product calculation unit 5 V ₁ V ₂
Cos θ is determined to be positive or negative by the positive/negative determining section 13 . The output section 14 obtains an out-of-synchronization output when the judgments of the judgment sections 13 and 12 are both positive.

With this configuration, the judgments of the judgment units 12 and 13 are as follows: |V ₁ V ₂ cosθ|≧K|V ₁ V ₂ sinθ| ...(3) V ₁ V ₂ cosθ≧0 ...(4), (3) The equation is converted to the following equation (5).

|coTθ|≧K ...(5) As is clear from equation (5), the tangent value of the phase difference θ between the signals V ₁ and V ₂ in the range of 0° to 30° |coTθ
As the change in | becomes larger, it becomes easier to detect and judge synchronization. For example, at θ=10° and 15°, the tangent value |coTθ|
There is a change of 30% or more.

Further, errors included in the vector inner product due to quantization errors and the like are canceled out by determining the output ratio of the vector inner product sections 5 and 7, and a highly accurate determination can be obtained.

FIG. 4 shows a flowchart of the digital protection arithmetic device according to the present invention. Voltage detection signal V ₁ V ₂
are sequentially taken in as digital quantities by sampling and A/D conversion as in the case of FIG. 2 (step S ₁ ), and a vector inner product operation is performed on these digital signals V ₁ and V ₂ (step S ₂ ). Operation result A at step _S2 (=|V・₁ ||V・₂ |cosθ)
is determined, for example, by the three product method. This three product method uses three consecutive sampling data, and the signals V ₁ and V ₂ are respectively V ₁ =V ₁ sinωt ……(6) V ₂ =V ₂ sin(ωt−θ) ……( 7) If three consecutive sampling data of V ₁ and V ₂ are respectively V ₁₁ , V ₁₂ , V ₁₃ and V ₂₁ , V ₂₂ , V ₂₃ , then from the calculation of equation (8) below, V ₁₁ V ₂₁ −K ₁ V ₁₂ V ₂₂ +V ₁₃ V ₂₃
=K ₂ V・₁ V・₂ cosθ (8) The vector inner product K ₂ V・₁ V・₂ cosθ can be obtained. The constants K ₁ and K ₂ are values determined by the sampling angle.
At 30 degree intervals, K ₁ = 1, K ₂ = 1/2.

Next, sampling data _V.2 ' obtained by shifting the phase of the signal _V2 by 90 degrees is extracted (step S3). This step S3
In this case, when the signal V ₂ is taken out at a sampling interval of 30°, it means that data of three samples before is read from the memory. The sampling data _V.2 ' is subjected to a vector inner product operation with the current sampling data _V.sub.1 of the signal _V.1 (step S4). This vector inner product is performed in the same way as the above equation (8), and the three data following the sampling data V・₂ ′ and the three data of V・₁ are
Calculated using two data. This calculation result B
Since V・₂ ′ is phase shifted by 90°, V・₁・V・
₂
Corresponds to sinθ.

Next, the following equation (9) is calculated using the values A and B obtained in steps S2 and S4 and the set value K (step S5).

C=|A|-K|B|...(9) Regarding this calculation result C, if the conditions of determination of C≧O (step S6) and determination of A≧O (step S7) are satisfied, the calculation output of out-of-synchronization is determined. get (step
S8). Further, when C<O or A<O, a calculation output indicating that the synchronization state exists is obtained (step S9).
These calculations are performed within the sampling period,
Each time each sampling data is taken in, a result of determining whether or not synchronization has occurred is obtained.

As described above, according to the present invention, signals of both systems
In order to compare and judge the ratio of the vector inner product of V ₁ and V ₂ and the vector inner product with one phase shifted by 90° with the setting value K,
Even when the phase difference between the signals V ₁ and V ₂ is small, there is an effect that accurate synchronization detection can be performed without being affected by quantization errors and the like.

[Brief explanation of the drawing]

Fig. 1 is a characteristic diagram of a synchronization detection relay, Fig. 2 is a configuration diagram of a digital protection relay, Fig. 3 is a block diagram showing an embodiment of the present invention, and Fig. 4 is a flowchart of a protection calculation device in the present invention. It's a chat. 1 ₁ , 1 ₂ ... Sample hold circuit, 2 ... Multiplexer, 3 ... A/D converter, 4 ... Protection calculation device, 5, 7 ... Vector inner product calculation section, 6 ...
...Phase shift section, 8, 9... Absolute value calculation section, 10... Multiplication section, 11... Addition section, 12, 13... Positive/negative determination section, 14... Output section.

Claims (1)

[Claims] 1. The voltage signals V ₁ and V ₂ of the two electric power systems are sequentially sampled and held at a constant period, and analog-to-digital converted and taken into a digital type protection calculation device, and this protection calculation device converts the digital signals of the signals V ₁ and V ₂ Result A of the vector inner product calculation, result B of the vector inner product calculation of one digital signal shifted by 90 degrees in electrical angle, and the above calculation results A and B.
1. A digital synchronization detection relay comprising means for obtaining an out-of-synchronization output when the ratio of K is larger than a set value K and the calculation result A is positive.