JPH0452068B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device using an inverter set using self-extinguishing semiconductor elements, particularly gate turn-off thyristors (hereinafter abbreviated as GTO) and transistors, and in which the inverter sets are connected in parallel.

Figure 1 shows an inverter set parallel device using GTO. This circuit is an inverter device in which a two-arm single-phase inverter using a two-divided DC power supply is connected in parallel via a current balancing interphase reactor. In the figure, 1 and 2 are single-phase inverter sets, 3 and 4 are DC power supplies, and 5 is a load.
1 is a resistor, and 52 is a reactor. 11,12
constitute the positive side and negative side arms of inverter 1
GTOs 11' and 12' are respective feedback diodes; 21 and 22 are GTOs forming the positive and negative arms of the inverter 2; 21' and 22' are respective feedback diodes. Also, 7 is inverter 1
and 2 are interphase reactors for output current balancing.

Conventionally, in this device, the interphase reactor was
A voltage v _IPX is added according to the GTO switching time difference. Figure 2 shows switching operation patterns due to variations in switching time of a conventional GTO. In the figure, a shows the operation of the GTO 11, and b shows the action of the GTO 21. If you choose GTO arbitrarily, GTO
11 as a standard, the GTO 21 can be considered to have pattern 1 in which turn-on is delayed and turn-off is advanced, and pattern 2 in which turn-on is advanced and turn-off is delayed. Furthermore, GTO12 and GTO22
There is a similar pattern of operation. Each side
When GTO is selected arbitrarily, voltage may be applied in only one direction between the interphase reactor terminals. FIG. 3 shows the operation of each part when GTO is arbitrarily selected as in the conventional case. In this figure, GTO11
GTO21 becomes pattern 1 based on
This figure shows the operation of each part when GTO 21 operates in pattern 2 using GTO 12 as a reference. In the figure, CS is a control signal for modulated wave A and carrier wave B,
PWM is a pulse width modulation signal, INV1 is the operation of inverter 1, INV2 is the operation of inverter 2, i _u is the load current, and v _IPX is the voltage between the interphase reactor terminals. In FIG. 3, all voltages to the interphase reactors are applied in the positive direction. Also, contrary to Figure 3,
When GTO 21 operates in pattern 2 with GTO 11 as a reference, and GTO 22 operates in pattern 1 with GTO 12 as a reference, voltage only in the negative direction is applied to the interphase reactor.

In this way, in conventional equipment, if a voltage of the same polarity is continuously applied between the interphase reactor terminals, the magnetic flux of the interphase reactor becomes saturated, making it impossible to maintain current balance and making it impossible to perform set parallel operation normally. Can not. Alternatively, even if current balance could be maintained, the interphase reactor required for this purpose would be extremely large.

The object of the present invention is to maintain the output current balance of each inverter in an inverter set parallel device which eliminates the above-mentioned drawbacks, and to further downsize the current balancing interphase reactor.

In order to achieve the above object, the present invention provides a circuit in which self-extinguishing semiconductor elements are connected in series using positive side and negative side arms, a DC power supply connected to both ends of the series connection circuit, and a DC power supply connected to both ends of the series connection circuit. The inverter is equipped with output terminals at positive and negative arm connection portions of the circuit, wherein at least two inverters are provided, and the output terminals of each inverter are connected via a reactor to form arms on the same side of each inverter. In a parallel device of inverters that controls the firing of the semiconductor elements based on the same firing signal and supplies power from each of the inverters to a load connected to a midpoint of the reactor, on the same side of each of the inverters. The self-arc-extinguishing semiconductor elements of one arm have switching characteristics such that, when the turn-on and turn-off operations of the semiconductor elements of one inverter are taken as a reference, the semiconductor elements of the other inverter have the same turn-on and turn-off operations. will move forward together?
Alternatively, both elements are characterized by having a delay characteristic.

With the above configuration, it is possible to realize a switching operation pattern in which voltage pulses are applied alternately in the positive and negative directions to the interphase reactor terminals, and the excitation voltage of the interphase reactor is always reversed in positive and negative directions, so that the magnetic flux is unidirectional. do not become. Therefore, the amount of excitation of the interphase reactor is also reduced, and even if a small reactor is used, the interphase reactor will not be saturated, and current balance can be maintained.

Figure 4 shows a GTO with GTO11 and GTO12 as a reference when voltages in the positive and negative directions are alternately applied to the interphase reactor in the same single-phase inverter set parallel device as in Figure 1, which is an embodiment of the present invention.
21 shows the switching operation pattern of GTO22. In the diagram, a indicates the operation of inverter 1, and b indicates the operation of inverter 2, and the switching characteristics of the GTO may be selected so that one of the four patterns 1 to 4 in the diagram is achieved. Switching operation pattern 1 in Fig. 4, that is, one in which the turn-on and turn-off times of GTO21 are fast based on GTO11,
FIG. 5 shows the operation when GTO 22 is selected to have a quick turn-on and turn-off time based on GTO 12. The signals in the figure correspond to those in FIG. In Fig. 5, when the load current i _u is positive,
A negative voltage is applied between the time when the GTO 21 is turned on and the time when the GTO 11 is turned on, and a positive voltage is applied between the interphase reactor terminals between when the GTO 21 is turned off and the time when the GTO 11 is turned off.
When the load current i _u is negative, a positive voltage is applied between the time when GTO22 is turned on and GTO12 is turned on, and a negative voltage is applied between the interphase reactor terminals between when GTO22 is turned off and GTO12 is turned off. .

Therefore, the voltage applied to the interphase reactor is positive,
Since the voltage is in both negative directions, the reactor does not become saturated and current balance can be maintained. As an example, if we compare the size of the interphase reactor required to maintain current balance in the case of 9 PWM pulses in Figures 3 and 5, we can see that the size of the reactor between the phases is larger than that of the former when the number of PWM pulses is 9. can be reduced to approximately 1/9 in terms of the iron core cross-sectional area, proportional to the reciprocal of the number of PWM pulses. Also, when the number of PWM pulses is 15 or 27, it is 1/15 and 1/1, respectively.
27, and as the number of pulses increases, this effect increases.

Note that the present invention is not limited to the single-phase inverter shown in FIG. 1, but can also be applied to a three-phase inverter shown in FIG. 6. In the figure, 10 and 20 are three-phase inverter sets, 30 is a DC power supply, and 50 is a load, which is generally an AC motor. DC power supply 3 is common to inverters 1 and 2,
The u-phase, v-phase, and w-phase of each inverter are connected to respective interphase reactors 70, 80, and 90, and supply their respective output currents to the load 50. GTO is two GTO1 corresponding to inverter 10 and 20 respectively.
1 and GTO21, GTO12 and GTO22, GTO1
3 and GTO23, GTO14 and GTO24, GTO1
5 and GTO25, GTO16 and GTO26, as shown in the above-mentioned single-phase inverter, one GTO switching characteristic is used as a reference, and the other
GTO will proceed both turn-on and turn-off,
Alternatively, if the inverter is selected so that both turn-on and turn-off are delayed, the same effect as a single-phase inverter can be obtained.

As described above, according to the present invention, in the inverter set parallel device to which GTO is applied, two corresponding inverters 1 and 2 are connected.
Both turn-on time and turn-off time are fast when using either as a reference for GTO.
By selecting GTO as the other side, it becomes easier to maintain the current balance state of the inverter, and the phase-to-phase reactor for current balance can be made smaller.
This has the great effect of making the device smaller. Although the present invention has been described with reference to the case where the GTO is applied to an inverter, it goes without saying that it can be similarly applied to a transistor.

[Brief explanation of the drawing]

Figure 1 is a diagram showing an example of a single-phase inverter set parallel circuit, Figure 2 is a diagram showing an example of the switching operation pattern of the GTO in Figure 1, and Figure 3 is a diagram showing an example of a switching operation pattern of the GTO in Figure 1. Fig. 1 is an explanatory diagram of the operation, Fig. 4 is a diagram showing an example of the GTO switching operation pattern when both positive and negative voltages are applied to the interphase reactor, Fig. 5 is an explanatory diagram of the operation of Fig. 4, and Fig. 6 FIG. 3 is a diagram showing another embodiment of the present invention. 1, 2, 10, 20...Inverter set, 1
1, 12, 13, 14, 15, 16, 21, 2
2, 23, 24, 25, 26...GTO, 7, 7
0, 80, 90... Interphase reactor for current balance.

Claims (1)

[Scope of Claims] 1. A circuit in which self-extinguishing semiconductor elements are connected in series using positive and negative arms, a DC power supply connected to both ends of the series connection circuit, and positive and negative arm connections of the series connection circuit. The inverter is equipped with an output terminal on a part thereof, the inverter is provided with at least two units, the output terminal of each inverter is connected via a reactor, and the semiconductor element forming an arm on the same side of each inverter is In a parallel inverter system in which ignition is controlled based on the same ignition signal and power is supplied from each inverter to a load connected to a midpoint of the reactor, self-extinguishing of arms on the same side of each inverter is provided. Regarding the arc-shaped semiconductor element, in terms of the switching characteristics that the element has, when the turn-on and turn-off operations of the semiconductor element of one inverter are taken as a reference, the turn-on and turn-off operations of the semiconductor element of the other inverter proceed together;
Alternatively, a parallel inverter device characterized by comprising elements having characteristics that both have a delay.