JPH0452261U - - Google Patents
Info
- Publication number
- JPH0452261U JPH0452261U JP9204090U JP9204090U JPH0452261U JP H0452261 U JPH0452261 U JP H0452261U JP 9204090 U JP9204090 U JP 9204090U JP 9204090 U JP9204090 U JP 9204090U JP H0452261 U JPH0452261 U JP H0452261U
- Authority
- JP
- Japan
- Prior art keywords
- gate
- instruction
- clock
- output
- microcomputer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002093 peripheral effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Microcomputers (AREA)
Description
第１図は本考案を示すブロツク図、第２図は第
１図の各部動作を示すタイムチヤートである。
３……インストラクシヨンデコーダ、４，６…
…ＡＮＤゲート、５……ＲＳ−ＦＦ、７……タイ
マー。
FIG. 1 is a block diagram showing the present invention, and FIG. 2 is a time chart showing the operation of each part of FIG. 3... Instruction decoder, 4, 6...
...AND gate, 5...RS-FF, 7...timer.
Claims (1)
クが印加される第１のＡＮＤゲートと、 前記第１のＡＮＤゲートの出力が印加されてセ
ツトされ、第２の命令クロツクが印加されてリセ
ツトされるフリツプフロツプと、 前記解読出力、前記フリツプフロツプの出力、
及び第３の命令クロツクが印加される第２のＡＮ
Ｄゲートと、を備え、 前記特定命令を２回連続実行した時の前記第２
のＡＮＤゲートの出力によつて、新たに追加され
た周辺回路の動作を制御することを特徴とするマ
イクロコンピユータ。 (2) 第１、第２、及び第３の命令クロツクは、
マイクロコンピユータを動作させるための順次繰
り返し発生するクロツクであることを特徴とする
請求項(1)記載のマイクロコンピユータ。[Claims for Utility Model Registration] (1) A first AND gate to which the decoding output of a specific instruction and a first instruction clock are applied; and a second AND gate to which the output of the first AND gate is applied and set; a flip-flop to which an instruction clock of is applied and reset; the decoding output; the output of the flip-flop;
and a second AN to which a third instruction clock is applied.
D gate, when the specific instruction is executed twice consecutively, the second
A microcomputer characterized in that the operation of a newly added peripheral circuit is controlled by the output of an AND gate. (2) The first, second, and third instruction clocks are
2. The microcomputer according to claim 1, wherein the clock is a clock that is repeatedly generated in order to operate the microcomputer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9204090U JPH0452261U (en) | 1990-08-31 | 1990-08-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9204090U JPH0452261U (en) | 1990-08-31 | 1990-08-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0452261U true JPH0452261U (en) | 1992-05-01 |
Family
ID=31828202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9204090U Pending JPH0452261U (en) | 1990-08-31 | 1990-08-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0452261U (en) |
-
1990
- 1990-08-31 JP JP9204090U patent/JPH0452261U/ja active Pending