JPH0452493B2 - - Google Patents

Description

[Detailed description of the invention]

A. Technical Field The present invention relates to a procedure debug support system, and more particularly to a procedure debug support system that enables efficient debugging by utilizing a job step program execution inhibiting function. B. Prior art and its problems Debugging a procedure written in a job control language is done by referring to the source list and execution results on a computer, and using the system's execution step number, race function, and address stop function. However, it takes a lot of time for procedures written in the current highly functional job control language (JCL, Job Control Language). This means that when a command in a procedure instructs a job step program to be loaded into main storage, the loaded job step program is executed and most of the execution time of the procedure is spent in the job step program. This is because it is occupied by execution time. C. Object and Structure of the Invention An object of the present invention is to provide a procedure debugging support system that enables efficient debugging of procedures. The present invention provides a procedure debugging support method for supporting debugging of a procedure written in a job control language, which includes: a first flag setting section for setting a debug mode flag; and a first flag setting section for setting a job step program execution inhibition mode flag. a second flag setting section; a determining section that determines whether these flags are set; and a second flag setting section that determines whether the flags are set; and a control section that blocks execution of the job step program in response to an instruction, and the control section is configured to increment an address counter for fetching the next instruction when execution of the job step program is blocked. It is characterized by the fact that When debugging the execution sequence of a procedure or its logic, it is often almost unnecessary to run a job step program. This was done based on the recognition that fairly efficient debugging would be possible if the procedure could proceed as if the job step program had terminated normally. D Examples Examples of the present invention will be described below based on the drawings. FIG. 1 shows a procedure whose job name is "EXAMPLE" to be executed in one embodiment described below. The contents of each command of this procedure are shown in Table 1 below.

【table】

[Table] FIG. 2A, FIG. 2B, and FIG. 2C are diagrams for explaining the operation of this embodiment. Figure 2A,
Figures 2B and 2C illustrate the control flow of the system and the contents of main memory. Debugging of the procedure is performed by an operator operating the console and inputting commands. Each operation command input by the operator is shown in Table 2 below.

[Table] When the operator starts debugging the procedure, he turns on the power from the console, loads the control program from the monitor file 1 into the main storage device 2, and then an instruction to enable operation is displayed on the display. Before starting the procedure to be debugged as a job, the operator inputs an operation command to request debugging support from the system and sets an address stop position (for example, 0021). At the same time, it instructs to suppress execution of the job step program. This operation command is
“JCLDEB, AS=0021, NOEX” is displayed on the display screen. The flag F is added to the data stored in the main storage device 2 by setting the debug mode and setting the job step program execution suppression mode flag.
is erected. The most significant bit F(0) of the flag is
It shows whether the system is in normal mode or debug mode, with F(0)=0 representing normal mode and F(0)=1 representing debug mode.
The next bit F(1) of the flag indicates whether the mode is job step program execution mode or job step program execution inhibition mode.
=0 represents execution mode, and F(1)=1 represents execution inhibition mode. In this case, by inputting the above operation command, F(0)=1 and F(1)=1 are set, and the control program switches the system from normal mode to debug mode and sets job step program execution suppression mode. . Next, when the operator inputs the operation command "CALLEXAMPLE", the procedure (EXAMPLE) stored in the procedure file 3 is read out, the procedure job "EXAMPLE" is started, and the procedure commands are sequentially executed. The job step program "TEST1" is read out from the program file 4 and loaded into the main storage device 2 by the procedure command "LOAD TEST1". The job step program "TEST2" is read out from the program file 4 and loaded into the main storage device 2 by the next procedure command "LOAD TEST2". With the following procedure command “START”,
It is determined whether the flag F(0) is 1, and F
If (0)=1, then it is determined whether flag F(1) is 1 or not. If F(0)≠1 or F(1)≠1, job step programs “TEST1” and “TEST2” loaded into main memory 2
Control of the system is transferred to the job step program, and these job step programs are executed. In this example,
Since F(0)=1 and F(1)=1 are set, control of the system is not transferred to job step programs "TEST1" and "TEST2".
Therefore, execution of these job step programs is inhibited, and after the procedure proceeds as if the job step program had terminated normally, the main memory is freed and the next procedure command is interpreted. FIG. 3 shows the configuration of a circuit section that performs this judgment process. When the operator sets the debug mode and the job step program execution inhibition mode, the debug mode flag setting flip-flop 5 and inhibition mode flag setting flip-flop 6 are each set to "1". The outputs of these flip-flops are
is supplied to the two input terminals of AND gate 7,
A procedure command execution command signal is input to the remaining input terminals of the AND gate. When all inputs of AND gate 7 are at high level,
A high level output signal is generated at the output terminal of the AND gate 7, and this output signal serves as a signal for inhibiting execution of the job step program. On the other hand, when flip-flop 5 or 6 is in the reset state, the output of AND gate 7 is at a low level and the job step program is executed without being inhibited. The procedure command execution command signal input to the AND gate 7 is also supplied to the +1 circuit 8.
The count of address counter 9 is incremented. The address counter 9 addresses the procedure file 3 and sequentially executes procedure commands. Therefore, when execution of a job step program is inhibited, the procedure proceeds as if the job step program had terminated normally. Then, as shown in Figure 2B, when the procedure command "MSG'END!'" is executed, 'END!' appears on the display. ' is displayed to notify the operator of the end of the job step. When a stop address is detected during execution of a procedure command, the debug mode flag F
It is determined whether (0) is 1 or not. F(0)≠
If 1, the procedure command will be executed without being stopped. In this embodiment, the debug mode is set, and therefore, since F(0)=1, execution of the procedure is stopped and the procedure is placed in a state of waiting for instructions. At this time, the display shows the execution process of the procedure commands so far using JCL step numbers. FIG. 4A shows the display screen, and execution of the procedure command is interrupted at step number 0021. In this instruction waiting state, it is possible to change the address stop position, execute a procedure in a single step, or specify cancellation of debug mode. In this embodiment, it is assumed that the operator inputs the operation command "AS=0045, EX". This command is executed at address 004
5 is a command to stop the address and execute the job step program. As a result, the address stop position is stored in the main memory 2, the job step program execution inhibition mode flag F(1) is set to 0, and the system is set to the job step program execution mode. The operator instructs the continuation of the procedure by inputting a key and causes the procedure command to be executed. When a stop address is detected during execution, it is determined whether the debug mode flag F(0) is 1 or not in the same way as described above. If F(0)≠1, the procedure command is executed without being stopped. In this embodiment, the debug mode is set, and therefore, since F(0)=1, execution of the procedure is stopped and the procedure is placed in a state of waiting for instructions. At this time, the display shows the JCL execution process of the procedure so far.
Displayed by step number. FIG. 4B shows the display screen, and step number 0
At 045, execution of the procedure is interrupted. In this instruction waiting state, it is possible to change the address stop position, execute a procedure in a single step, or specify cancellation of debug mode.In this embodiment, debug mode is canceled and the operator inputs the operation command “CAN”. As shown in FIG. 2C, this command sets the debug mode flag F(0) in the main memory to 0, returning the system to normal mode. When the operator instructs to continue the procedure by inputting a key, the procedure command is executed in the normal mode. When procedure command "PEND" is executed, procedure job "EXAMPLE" ends. As is clear from the above embodiments, the execution step number trace function and address stop function allow debugging to be performed while progressing the procedure little by little. E Effects According to the present invention, when debugging a procedure written in a highly functional job control language,
Since execution of the job step program can be suppressed and the procedure can proceed as if the program had terminated normally, it is possible to debug and create a procedure efficiently in a short time.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a procedure in an embodiment of the present invention, FIG. 2A, FIG. 2B, and FIG. 2C are diagrams for explaining the operation of an embodiment of the present invention. FIG. 4 is a diagram showing the configuration of the flag determination processing circuit section, and FIG. 4 is a diagram showing the screen display of the display. In the figure, 1 is the monitor file, 2 is the main memory,
3 is a procedure file, 4 is a program file, 5 and 6 are flip-flops, 7 is an AND gate, 8 is a +1 circuit, and 9 is an address counter.

Claims (1)

[Scope of Claims] 1. In a procedure debugging support method that supports debugging of a procedure written in a job control language, a first flag setting section that sets a debugging mode flag; and a job step program execution suppression mode flag. a second flag setting unit that sets a second flag; a determining unit that determines whether or not these flags are set; and a second flag setting unit that determines whether or not these flags are set; and a control section that blocks execution of the job step program according to instructions from the judgment section, and the control section increments an address counter for fetching the next instruction when execution of the job step program is blocked. A procedure debugging support method is provided.