JPH0452632B2 - - Google Patents

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Publication number
JPH0452632B2
JPH0452632B2 JP60012134A JP1213485A JPH0452632B2 JP H0452632 B2 JPH0452632 B2 JP H0452632B2 JP 60012134 A JP60012134 A JP 60012134A JP 1213485 A JP1213485 A JP 1213485A JP H0452632 B2 JPH0452632 B2 JP H0452632B2
Authority
JP
Japan
Prior art keywords
superconducting
type
semiconductor
inversion layer
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP60012134A
Other languages
Japanese (ja)
Other versions
JPS61171180A (en
Inventor
Hideaki Takayanagi
Goji Kawakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP60012134A priority Critical patent/JPS61171180A/en
Publication of JPS61171180A publication Critical patent/JPS61171180A/en
Publication of JPH0452632B2 publication Critical patent/JPH0452632B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/10Junction-based devices
    • H10N60/11Single-electron tunnelling devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/10Junction-based devices
    • H10N60/128Junction-based devices having three or more electrodes, e.g. transistor-like structures

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  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体を接合部にもつ超伝導素子。
即ち超伝導体−半導体−超伝導体結合素子に関す
るものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a superconducting element having a semiconductor at a junction.
That is, it relates to a superconductor-semiconductor-superconductor coupled device.

〔発明の概要〕[Summary of the invention]

本発明は、P形半導体の表面のn形反転層に形
成された2次元電子ガス(2DEG)によつて二つ
の超伝導電極が結合している半導体結合超伝導素
子を提供すものである。
The present invention provides a semiconductor-coupled superconducting element in which two superconducting electrodes are coupled by two-dimensional electron gas (2DEG) formed in an n-type inversion layer on the surface of a P-type semiconductor.

〔従来の技術〕[Conventional technology]

トンネル形ジヨセフソン素子の発明以来、半導
体におけるトランジスタやFETに対応する超伝
導三端子素子の研究は数多く行なわれて来た。こ
の中にあつて、半導体結合超伝導素子は、バリア
ーハイトが低く電極間隔が広くとれること、更に
半導体に対する電気的制御により三端子動作の可
能性があることから、多くの試みがなされて来た
が、実用に供するものは得られていない。
Since the invention of the tunnel-type Josephson device, much research has been conducted on superconducting three-terminal devices, which correspond to transistors and FETs in semiconductors. In this regard, many attempts have been made to develop semiconductor-coupled superconducting devices because they have a low barrier height and can have a wide electrode spacing, and also have the possibility of three-terminal operation through electrical control of the semiconductor. However, nothing of practical use has been obtained.

第13図に従来の半導体結合素子の断面構造を
示すが、これまでに実現されたものでは、基板1
の半導体として単結晶Siを用い、拡散又はイオン
注入により高濃度のP形として第13図のように
超伝導電極2を互に近接して形成した構造で超伝
導電流が得られている。これについては、R.C.
Ruby&T.Van Duzar:IEEE Trans.Elect.
Device,ED−28,1394,(’81)に報告されて
いる。
FIG. 13 shows a cross-sectional structure of a conventional semiconductor coupling device.
A superconducting current is obtained in a structure in which single-crystal Si is used as a semiconductor, and superconducting electrodes 2 are formed close to each other as shown in FIG. 13 as highly concentrated P-type semiconductors by diffusion or ion implantation. Regarding this, RC
Ruby & T. Van Duzar: IEEE Trans.Elect.
Device, ED- 28 , 1394, ('81).

ところで、半導体結合超伝導素子の特性は、半
導体中の超伝導拡散長ξNと、超伝導体と半導体と
の界面特性に密接に関連している。超伝導近接効
果理論J.Seto&T.Van Duzer:Low Tempera−
ture Physics−LT−13,328,New York,
Plenum,(’74)によれば、最大超伝導電流Ic
は、 Ic∝Tj2exP(−L/ξN)/ξN−(式1) となる。ここで、Tjは超伝導体/半導体界面に
おける電子のトンネリング確率であり、上式より
大きなIcを得るためにはTjが大きく、ξNの長い
必要のあることがわかる。一般的に、金属/半導
体界面にはシヨツトキーバリアーが形成される
が、Tjはこのバリアー高が低く、バリアー幅の
うすい程大きくなる。
Incidentally, the characteristics of a semiconductor-coupled superconducting device are closely related to the superconducting diffusion length ξ N in the semiconductor and the interface characteristics between the superconductor and the semiconductor. Superconducting proximity effect theory J. Seto & T. Van Duzer: Low Tempera−
ture Physics−LT− 13 , 328, New York,
According to Plenum, ('74), the maximum superconducting current Ic
is Ic∝Tj 2 exP(−L/ξ N )/ξ N − (Formula 1). Here, Tj is the tunneling probability of electrons at the superconductor/semiconductor interface, and it can be seen from the above equation that in order to obtain a large Ic, Tj must be large and ξ N must be long. Generally, a Schottky barrier is formed at the metal/semiconductor interface, and Tj increases as the barrier height decreases and the barrier width decreases.

第14図は超伝導体−P形シリコン−超伝導体
素子のエネルギーバンド図であり、EFはフエル
ミレベル、EC,EVはそれぞれ伝導帯、価電子帯
の下端及び上端エネルギーレベルを示す。P形シ
リコンの場合バリアー高Ebは0.2eVである。バリ
アー幅Wはキヤリア濃度nに依存し、nが大きい
程うすくなる。従つて、P形シリコンを用いた素
子では1020cm-3とnをなるべく大きくする必要が
あつた。一方、ξNは半導体の移動度をμ(cm2
VS)とすると、 ξN∝μ1/2n1/3 −(式2) となる。
FIG. 14 is an energy band diagram of a superconductor-P-type silicon-superconductor device, where E F is the Fermi level, and E C and EV are the lower and upper end energy levels of the conduction band and valence band, respectively. In the case of P-type silicon, the barrier height E b is 0.2 eV. The barrier width W depends on the carrier concentration n, and the larger n is, the thinner it becomes. Therefore, in an element using P-type silicon, it was necessary to increase n to 10 20 cm -3 as much as possible. On the other hand, ξ N represents the mobility of the semiconductor as μ(cm 2 /
VS), then ξ N ∝μ 1/2 n 1/3 − (Equation 2).

前述のP形Siの場合、T=4.2Kでμ60cm2
VSと小さく、ξNは約0.01μと短い。このようにP
形シリコンを用いた素子ではnが1020cm-3と大き
いにもかかわらずξNは短く、素子長L=0.1μm前
後の素子しか実現できなかつた。キヤリア濃度が
1020cm-3ではもはや半導体とは言いがたく金属的
であり、例えMIS(電圧駆動型)やMES(電流注
入駆動型)構造が実現されても、ゲートの印加電
圧や流入電流の変化に対してごく感度の鈍いもの
になり、トランジスタ又はFET素子のような半
導体としての特徴を生かすことはできない。また
超伝導電極間隔が0.1μmでは、半導体上に第三端
子を形成すること自体非常に困難である。
In the case of the P-type Si mentioned above, μ60cm 2 /
VS is small, and ξ N is short at approximately 0.01μ. Like this P
In the case of a device using type silicon, ξ N is short even though n is as large as 10 20 cm −3 , and only a device with a device length L of around 0.1 μm could be realized. Carrier concentration
At 10 20 cm -3, it can no longer be called a semiconductor and is metallic, and even if an MIS (voltage-driven) or MES (current-injection driven) structure is realized, it will be sensitive to changes in the applied gate voltage and inflow current. However, it becomes extremely insensitive, and cannot take advantage of its characteristics as a semiconductor such as a transistor or FET element. Furthermore, if the superconducting electrode spacing is 0.1 μm, it is very difficult to form the third terminal on the semiconductor.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明は、前述の従来の超伝導体−半導体−超
伝導体結合素子における問題点、すなわち超伝導
電流を得るために超伝導電極間隔を極めて短かく
しなければならず、また半導体のキヤリア濃度を
極めて高くしなければならないという問題を解決
し、特性の優れた超伝導二端子あるいは三端子素
子を実現しようとするものである。
The present invention solves the problems with the conventional superconductor-semiconductor-superconductor coupling device described above, namely, the distance between the superconducting electrodes must be extremely short in order to obtain a superconducting current, and the carrier concentration of the semiconductor must be reduced. The aim is to solve the problem of having to increase the height extremely high and to realize a superconducting two-terminal or three-terminal device with excellent characteristics.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、P形半導体の表面反転層中に2次元
電子ガス(2DEGという)が形成されること、及
び2次元において超伝導拡散長ξN∝μ1/2n1/3に対
して、後述のようにξN∝μ1/2n1/2となるという解
折結果に着目してなされたものである。
The present invention provides that a two-dimensional electron gas (referred to as 2DEG) is formed in the surface inversion layer of a P-type semiconductor, and that in two dimensions, for a superconducting diffusion length ξ N ∝μ 1/2 n 1/3 , This was done by focusing on the analysis result that ξ N ∝μ 1/2 n 1/2 as described later.

本発明において、P形半導体の表面反転層中の
2DEGによつて二つの超伝導電極が結合している
半導体結合超伝導素子を提供する。
In the present invention, in the surface inversion layer of a P-type semiconductor,
A semiconductor coupled superconducting element in which two superconducting electrodes are coupled by 2DEG is provided.

本発明構成において、P形半導体の表面にn型
反転層が形成され、その中に2DEGが形成されて
いること、 該2DEGが形成された半導体層と二つの超伝導
電極との接触がオーミツクであることが必要であ
る。
In the structure of the present invention, an n-type inversion layer is formed on the surface of a P-type semiconductor, a 2DEG is formed therein, and the semiconductor layer in which the 2DEG is formed is in ohmic contact with the two superconducting electrodes. It is necessary that there be.

以下より詳細に本発明をその作用とともに解説
する。
The present invention will be explained in more detail below along with its operation.

〔作用〕[Effect]

近接効果理論によると、半導体中の超伝導拡散
長ξNはξN=(〓D/2πkBT)1/2で与えられる。こ
こで、〓=h/2πでhはブランク定数、Dは拡散係 数、kBはボルツマン係数、Tは温度である。
According to the proximity effect theory, the superconducting diffusion length ξ N in a semiconductor is given by ξ N = (〓D/2πk B T) 1/2 . Here, h is a blank constant, D is a diffusion coefficient, k B is a Boltzmann coefficient, and T is a temperature.

Dは3次元の場合、D=1/3vFl(vFはフエルミ 速度、lは平均自由行程)であるが、2次元の場
合D=1/2vFlとなり、l=μvFm〓/e(m〓は 有効質量)、kF=(2πnS1/2,vF=〓kF/m〓であ
るから、2次元系のξNは ξN=(〓3μ/4πkBTem〓)1/2(2πnS1/2∝μ1
/2

nS 1/2 −(式3) と求まる。3次元の場合のξN∝μ1/2n1/3と比較す
ると、例えばn,nSが共に1桁上がつた時の効果
は2次元の場合の方が大きく、それだけ制御性は
向上すると言える。又、ξNを大きくするためには
n,nSを上げねばならないことは同じであるが、
前述の様に、3次元(バルク)の半導体の場合、
nを大きくするためにドーパントを多くドープす
ると、それが散乱体となつてμが落ち、結果とし
てξNが小さくなるという結果を招く。しかし、2
次元の場合は次の理由によつてそのようなことは
ない。
When D is three-dimensional, D=1/3v F l (v F is Fermi velocity, l is mean free path), but in two-dimensional case, D=1/2v F l, and l=μv F m〓 /e (m〓 is the effective mass), k F = (2πn S ) 1/2 , v F =〓k F /m〓, so ξ N of the two-dimensional system is ξ N = (〓 3 μ/4πk B Tem〓) 1/2 (2πn S ) 1/2 ∝μ 1
/2

It is found as n S 1/2 − (Equation 3). Compared to ξ N ∝μ 1/2 n 1/3 in the three-dimensional case, for example, when both n and n S increase by one order of magnitude, the effect is greater in the two-dimensional case, and the controllability improves accordingly. Then you can say. Also, in order to increase ξ N , n and n S must be increased, but
As mentioned above, in the case of three-dimensional (bulk) semiconductors,
If a large amount of dopant is doped in order to increase n, it becomes a scatterer and μ decreases, resulting in a decrease in ξ N. However, 2
In the case of dimensions, this is not the case for the following reasons.

一般にバルク半導体のキヤリア濃度nを増すた
めには、これと同程度のドーパントをドーピング
する必要があり、この結果前記のように移動度は
このド−パントによる散乱によつて小さくなる
(前述のP形シリコンの場合、n=1020cm-3でμ
60cm2/VS)のであるが、P形半導体の表面反
転層中の2DEGの場合、基板のキヤリア濃度が
元々小さくても2〜10nmの狭い領域に自然に、
あるいは電界によつてキヤリアが集まる。このた
めキヤリアの面密度nSは1012〜1013cm-2(nに換
算すると1013cm-2以上)と大きく、又基板中の散
乱体が元々少いため移動度μも大きい。更に、nS
は外部からかけた電界によつて制御できる。
Generally, in order to increase the carrier concentration n of a bulk semiconductor, it is necessary to dope it with a dopant of the same degree as this, and as a result, the mobility decreases due to scattering by this dopant (as mentioned above). In the case of silicon, n = 10 20 cm -3 and μ
60cm 2 /VS), but in the case of 2DEG in the surface inversion layer of a P-type semiconductor, even if the carrier concentration of the substrate is originally small, it naturally occurs in a narrow region of 2 to 10 nm.
Alternatively, carriers are gathered together by an electric field. For this reason, the areal density n S of the carrier is as large as 10 12 to 10 13 cm -2 (more than 10 13 cm -2 when converted to n), and since the number of scatterers in the substrate is originally small, the mobility μ is also large. Furthermore, n S
can be controlled by an externally applied electric field.

次に、本発明において、超伝導電極と2DEGが
形成されている半導体層との接触がオーミツクで
あることが要求されるが、このオーミツクの本発
明における意味を解説する。
Next, in the present invention, it is required that the contact between the superconducting electrode and the semiconductor layer in which the 2DEG is formed is ohmic, and the meaning of this ohmic in the present invention will be explained.

半導体と金属との接触がオーミツクであると
は、その接触部の電流電圧特性がオームの法則に
従うものをいう。一般に金属と半導体の接触部に
は第14図のようなシヨツトキーバリアーや第1
5図のような酸化物バリアー、そして両者のあわ
さつたバリアー等が形成される。液体ヘリウム温
度(1気圧で4.2K)のような極低温ではこのバ
リアーを通して流れる電流はトンネル効果による
ものが主であり、その電流電圧特性は上に述べた
意味でオーミツクであり、これによる接触抵抗が
発生する。この抵抗はトンネル確率Tjに反比例
し、Tjはバリアーの高さ及び幅、特に幅に強く
依存するから、接触抵抗を下げて電流を多く流す
ためには、バリアー幅をうすくする必要がある。
これを素子にあてはめてみる。超伝導臨界電流
(最大超電導電流)Icと常伝導抵抗RNとの積は、
Nb,Pb等の超伝導金属を電極2に使用した場合
最大2mVのオーダーであり、可観測という意味
からIcとしては最小10μA程度必要と考えられるか
ら、RNとしては200Ω以下が要求される。仮にRN
として、上記の接触抵抗だけを考え、超伝導電極
2と反転層5の2DEGとの接触面積を5nm×
100μm(2DEGの厚さ×素子幅)とすると、接触
抵抗は5×10-7Ωcm2(5×10-11Ωm2)以下が必
要となる。
An ohmic contact between a semiconductor and a metal means that the current-voltage characteristics of the contact conform to Ohm's law. Generally, the contact area between metal and semiconductor is provided with a shot key barrier or a first barrier as shown in Fig.
An oxide barrier as shown in Figure 5 and a barrier between the two are formed. At extremely low temperatures such as liquid helium temperature (4.2K at 1 atmosphere), the current flowing through this barrier is mainly due to the tunnel effect, and its current-voltage characteristics are ohmic in the sense mentioned above, and the contact resistance due to this occurs. This resistance is inversely proportional to the tunneling probability Tj, and Tj strongly depends on the height and width of the barrier, especially the width. Therefore, in order to lower the contact resistance and allow more current to flow, it is necessary to make the barrier width thinner.
Let's apply this to the element. The product of superconducting critical current (maximum superconducting current) Ic and normal conducting resistance R N is:
When superconducting metals such as Nb and Pb are used for electrode 2, the maximum voltage is on the order of 2 mV, and for observability, it is thought that a minimum of about 10 μA is required for Ic, so R N is required to be 200 Ω or less. . If R N
Considering only the above contact resistance, the contact area between the superconducting electrode 2 and the 2DEG of the inversion layer 5 is 5 nm ×
Assuming 100 μm (thickness of 2DEG×device width), the contact resistance needs to be 5×10 −7 Ωcm 2 (5×10 −11 Ωm 2 ) or less.

本発明で言うところのオーミツク特性とは、こ
のような小さい接触抵抗を持つたバリアー特性の
ことである。
The ohmic properties referred to in the present invention refer to such barrier properties having low contact resistance.

〔実施例〕〔Example〕

(実施例 1) 第1図に本発明の実施例の断面構造を示してい
る。図において、1はP形InAs基板、2は超伝
導電極、5は反転層、6はスパツタ法や蒸着法に
よつて形成されたSiOやSiO2等の絶縁膜、7は金
(Au)等の第三電極である。
(Example 1) FIG. 1 shows a cross-sectional structure of an example of the present invention. In the figure, 1 is a P-type InAs substrate, 2 is a superconducting electrode, 5 is an inversion layer, 6 is an insulating film such as SiO or SiO 2 formed by sputtering or vapor deposition, and 7 is gold (Au), etc. This is the third electrode.

P形InAsの表面はキヤリア濃度に関係なくn
形に反転しており、この反転層中に2DEGが形成
される。第2図に第1図の実施例の第三電極(ゲ
ート)部位におけるバンド図を示している。図の
ようにP−InAsの表面はn形に反転し、該反転
層の絶縁体との界面側に2DEGが発生している。
該2DEGキヤリア濃度nは第三電極7にかける電
圧Vgにより制御され、それにより2つの超伝導
電極2間の2DEG中を流れる超伝導電流を制御す
る。
The surface of P-type InAs is n regardless of the carrier concentration.
The shape is reversed, and 2DEG is formed in this reversed layer. FIG. 2 shows a band diagram at the third electrode (gate) portion of the embodiment shown in FIG. As shown in the figure, the surface of P-InAs is inverted to n-type, and 2DEG is generated on the interface side of the inversion layer with the insulator.
The 2DEG carrier concentration n is controlled by the voltage Vg applied to the third electrode 7, thereby controlling the superconducting current flowing in the 2DEG between the two superconducting electrodes 2.

上述のようにP−InAsの表面はキヤリア濃度
に関係なくn形に反転しており、この反転層中に
2DEGが形成されるが、n反転層からP層へのト
ンネルによるリーク電流の存在を考えると、キヤ
リア濃度は2〜3×1017cm-3以下が望ましく、こ
の場合4.2KでnS=2.5×1012cm2-2,μ=5000cm2
VSが実現されており(E.Yamaguchi:
Extended Abstract of the 1984 International
Conference on Solid State Devices and
Materials,Kobe,(’84),371参照)、ξN
0.19μmと長い。
As mentioned above, the surface of P-InAs is inverted to n-type regardless of the carrier concentration, and there are
2DEG is formed, but considering the existence of leakage current due to tunneling from the n inversion layer to the P layer, the carrier concentration is preferably 2 to 3 × 10 17 cm -3 or less, and in this case, at 4.2 K, n S = 2.5 ×10 12 cm 2-2 , μ=5000cm 2 /
VS has been realized (E. Yamaguchi:
Extended Abstract of the 1984 International
Conference on Solid State Devices and
Materials, Kobe, ('84), 371), ξ N also
It is long at 0.19μm.

さらに、本実施例で、超伝導電極2と半導体1
とが前述のようにオーミツクに接触する(半導
体/超伝導体界面での電子トンネル確率Tjが大
きい)ことが要求されるが、この点に関して、P
形InAs基板1の表面の反転層のn形InAs層の金
属に対するシヨツトキーバリアー高は第3図に示
すように常に負で、オーミツク・コンタクトを形
成する。従つて、半導体/超伝導体界面での電子
のトンネル確率TjはP形シリコン等に比べると
ずつと大きくなる。
Furthermore, in this embodiment, the superconducting electrode 2 and the semiconductor 1
As mentioned above, it is required that P be in contact with the ohmic (electron tunneling probability Tj at the semiconductor/superconductor interface is large).
As shown in FIG. 3, the Schottky barrier height of the n-type InAs layer of the inversion layer on the surface of the InAs-type InAs substrate 1 to the metal is always negative, forming an ohmic contact. Therefore, the electron tunneling probability Tj at the semiconductor/superconductor interface gradually increases compared to P-type silicon or the like.

このように、本実施例ではξNが長く、且つトン
ネル確率Tjが大きいから、先に示した式2(二次
元、三次元を問わず成立)から、大きなIc(最大
超伝導電流)が得られることが明らかであろう。
In this way, in this example, since ξ N is long and the tunneling probability Tj is large, a large Ic (maximum superconducting current) can be obtained from equation 2 shown earlier (holds true regardless of two-dimensional or three-dimensional). It is clear that

電極間隔LとξNとの関係は、IEEE
TRANSAC−TION ON ELECTRON
DEVICES,VOL.ED−28,NO.11,
NOVEMBER 1981,PP 1394〜1397にLはξN
数倍乃至10倍位までとれることが示されている。
The relationship between electrode spacing L and ξ N is given by IEEE
TRANSAC-TION ON ELECTRON
DEVICES, VOL.ED−28, NO.11,
It is shown in NOVEMBER 1981, PP 1394-1397 that L can range from several times to about 10 times ξN .

本実施例において、このようなことから電極間
隔Lを約0.5μmと長くとれ、そのため二端子構造
はもちろん、三端子構造の作成が可能となり、
2DEG中に超伝導電流が流れる二端子動作が可能
であり、更に、半導体におけるMOSFETのよう
に、電極7に加える電圧Vgで前述のようにnS
変化させ、これによつて二端子特性を制御する、
所謂三端子動作が行なえる。
In this example, for this reason, the electrode spacing L can be set as long as about 0.5 μm, which makes it possible to create not only a two-terminal structure but also a three-terminal structure.
Two-terminal operation is possible in which a superconducting current flows during 2DEG, and furthermore, like a MOSFET in a semiconductor, n S can be changed as described above by applying a voltage Vg to the electrode 7, thereby changing the two-terminal characteristics. Control,
So-called three-terminal operation can be performed.

(実施例 2) 第4図に示すのは、P形InAs基板1の半導体
表面のn型反転層5の上に、直接金属電極(第三
電極)7を形成した例であり、絶縁膜6の開口部
に金属電極7が形成されている。超伝導電極2に
関しては実施例1と同様である。
(Example 2) FIG. 4 shows an example in which a metal electrode (third electrode) 7 is directly formed on the n-type inversion layer 5 on the semiconductor surface of the P-type InAs substrate 1. A metal electrode 7 is formed in the opening. The superconducting electrode 2 is the same as in the first embodiment.

第5図にゲート部(第三電極7)についてのエ
ネルギーバンド図が示されている。この場合、二
端子動作としては実施例1とおなじであるが、三
端子動作は異なる。すなわち、この場合は
MESFET的、或いは電流注入による三端子動作
となる。
FIG. 5 shows an energy band diagram for the gate portion (third electrode 7). In this case, the two-terminal operation is the same as in the first embodiment, but the three-terminal operation is different. That is, in this case
MESFET-like or three-terminal operation using current injection.

(実施例 3) 第6図に示すのは、P−InAs基板1の表面に
リツジ(凸部)8を形成し、その両側に超伝導電
極2のNb層を形成した二端子構造の例である。
(Example 3) Figure 6 shows an example of a two-terminal structure in which a ridge (protrusion) 8 is formed on the surface of a P-InAs substrate 1, and a Nb layer of a superconducting electrode 2 is formed on both sides of the ridge. be.

第9図に、そのI−V特性を示す。 図におい
て、aは直流電流を印加した時のI−V特性であ
り、超伝導電流がの領域で流れており、は電
圧状態である。bは10GHZのマイクロ波を照射
した特性である。なお、見易くするためにa,b
の原点はずらして表示している。
FIG. 9 shows its IV characteristics. In the figure, a is the IV characteristic when direct current is applied, the superconducting current flows in the region, and is the voltage state. b is the characteristic of irradiation with 10GHZ microwave. In addition, for ease of viewing, a, b
The origin of is shown shifted.

(実施例 4) 第7図は、リツジ8を形成している他は実施例
1と同等なMIS構造三端子素子である。
(Example 4) FIG. 7 shows a three-terminal element with an MIS structure that is the same as Example 1 except that a ridge 8 is formed.

第10図に、本実施例においてゲート電圧を変
えた時に超伝導電流の変化すること(図中Icは最
大超伝導電流,RNは常伝導抵抗)が示されてい
る。
FIG. 10 shows how the superconducting current changes when the gate voltage is changed in this example (Ic in the figure is the maximum superconducting current and R N is the normal resistance).

(実施例 5) 第8図に示す例は、MES構造三端子素子で、
リツジ8構造を備える他は実施例2の第4図と同
等である。
(Example 5) The example shown in Fig. 8 is a three-terminal element with an MES structure.
The structure is the same as FIG. 4 of the second embodiment except that it has a ridge 8 structure.

第11図は、本実施例で注入電流Ijを変えた時
のIcの変化を示し、図示のようにIjによつて超伝
導電流が制御されている。
FIG. 11 shows the change in Ic when the injection current Ij is changed in this example, and as shown, the superconducting current is controlled by Ij.

(実施例 6) 第12図はP形InAs基板1の裏面にP形InAs
とオーミツク・コンタクトを形成する金属例えば
AuとZnの合金(Au90%+Zn10%)等で電極1
0を形成した実施例である。電極10は接合ゲー
トに相当し、電極10と電極2或いは7との間に
かける電圧によつて、p−n接合(この場合n層
は反転層)中の空乏層幅を制御し、これによつて
nSを変化させる三端子動作を行なう。なお、電極
10と2の間に電圧をかける場合は、電極7及び
絶縁膜6は必要ない。
(Example 6) Figure 12 shows P-type InAs on the back side of P-type InAs substrate 1.
Metals that form ohmic contact with e.g.
Electrode 1 made of Au and Zn alloy (Au90% + Zn10%), etc.
This is an example in which 0 is formed. The electrode 10 corresponds to a junction gate, and the width of the depletion layer in the p-n junction (in this case, the n-layer is an inversion layer) is controlled by applying a voltage between the electrode 10 and the electrode 2 or 7. Sideways
Performs three-terminal operation to change nS . Note that when applying a voltage between the electrodes 10 and 2, the electrode 7 and the insulating film 6 are not necessary.

以上実施例を示したが、本発明は、これに限る
ものではなく、例えば表面反転層中に2次元電子
ガス(2DEG)が生ずる他の半導体を用いること
ができ、また超伝導電極材料もNb,Pb以外に
種々の超伝導材料を用いることができる。
Although the embodiments have been described above, the present invention is not limited thereto. For example, other semiconductors in which two-dimensional electron gas (2DEG) is generated in the surface inversion layer can be used, and the superconducting electrode material can also be Nb. , various superconducting materials other than Pb can be used.

〔発明の効果〕〔Effect of the invention〕

以上のごとく、本発明は、P形半導体表面のn
形反転層に形成される2DEGによつて二つの超伝
導電極が結合している半導体結合超伝導素子を提
供するものであり、2DEG中に超伝導電流が流れ
る二端子動作が可能であり、しかも電極間隔Lを
従来の素子よりずつと広くとれる利点がある。更
に、第三電極により二端子特性を制御する、所謂
三端子動作が行なえるものであり、本発明によれ
ば特性の優れた二端子或いは三端子素子が実現さ
れる。
As described above, the present invention provides n on the surface of a P-type semiconductor.
The present invention provides a semiconductor-coupled superconducting element in which two superconducting electrodes are connected by a 2DEG formed in a shape inversion layer, and is capable of two-terminal operation in which a superconducting current flows in the 2DEG. There is an advantage that the electrode spacing L can be made wider than that of conventional elements. Furthermore, a so-called three-terminal operation in which the two-terminal characteristics are controlled by the third electrode can be performed, and according to the present invention, a two-terminal or three-terminal element with excellent characteristics can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第3図は、それぞれ本発明の第1の実
施例の断面図、ゲート部位についてのバンド図及
び超伝導電極部位についてのバンド図、第4図及
び第5図は、それぞれ本発明の第2の実施例の断
面図及びエネルギーバンド図、第6図〜第8図
は、本発明のそれぞれ第3〜第5の実施例の断面
図、第9図〜第11図はそれぞれ本発明の実施例
の素子の−V特性図、超伝導電流のゲ−ト電圧
による変化を示す図及びIcの注入電流依存性を示
す図、第12図は本発明の第6の実施例の断面
図、第13図及び第14図は従来の素子の断面図
及びバンド図、第15図は酸化物バリアーを示す
エネルギーバンド図。 1……P形InAs基板、2……超伝導電極、5
……(n形)反転層、6……絶縁膜、7……第3
電極、8……リツジ。
1 to 3 are a sectional view of a first embodiment of the present invention, a band diagram for a gate region, and a band diagram for a superconducting electrode region, and FIGS. 4 and 5 are a sectional view of a first embodiment of the present invention, respectively. 6 to 8 are sectional views of the third to fifth embodiments of the present invention, and FIGS. 9 to 11 are the cross-sectional views of the third to fifth embodiments of the present invention, respectively. -V characteristic diagram of the device of the sixth embodiment of the present invention, a diagram showing the change in superconducting current depending on the gate voltage, a diagram showing the dependence of Ic on the injection current, and Fig. 12 is a cross-sectional view of the sixth embodiment of the present invention. , FIG. 13 and FIG. 14 are a cross-sectional view and band diagram of a conventional element, and FIG. 15 is an energy band diagram showing an oxide barrier. 1... P-type InAs substrate, 2... superconducting electrode, 5
... (n-type) inversion layer, 6 ... insulating film, 7 ... third
Electrode, 8... Ritsuji.

Claims (1)

【特許請求の範囲】 1 表面反転層中に近接効果による超伝導電子の
拡散によつて超伝導電流の流れる2次元電子ガス
が形成されているP形半導体基板と、 該P形半導体基板の表面反転層とオーミツクに
接触している二つの超伝導電極とが含まれること
を特徴とする半導体結合超伝導素子。 2 前記P形半導体基板がP形InAs基板である
ことを特徴とする特許請求の範囲第1項記載の半
導体結合超伝導素子。 3 表面反転層中に近接効果による超伝導電子の
拡散によつて超伝導電流の流れる2次元電子ガス
が形成されているP形半導体基板と、 該P形半導体基板の表面反転層とオーミツクに
接触している二つの超伝導電極と、 該二つの超伝導電極間に備えられているMIS
型、MES型又は接合型ゲートとを有することを
特徴とする半導体結合超伝導素子。 4 表面反転層中に近接効果による超伝導電子の
拡散によつて超伝導電流の流れる2次元電子ガス
が形成されているP形半導体基板と、 該P形半導体基板の表面反転層とオーミツクに
接触している二つの超伝導電極と、 該P形半導体基板側に形成されたオーミツク電
極とを有することを特徴とする半導体結合超伝導
素子。
[Claims] 1. A P-type semiconductor substrate in which a two-dimensional electron gas in which a superconducting current flows is formed by diffusion of superconducting electrons due to the proximity effect in a surface inversion layer, and a surface of the P-type semiconductor substrate. A semiconductor-coupled superconducting device comprising an inversion layer and two superconducting electrodes in contact with an ohmic. 2. The semiconductor-coupled superconducting device according to claim 1, wherein the P-type semiconductor substrate is a P-type InAs substrate. 3. A P-type semiconductor substrate in which a two-dimensional electron gas in which a superconducting current flows is formed by diffusion of superconducting electrons due to the proximity effect in the surface inversion layer, and ohmic contact with the surface inversion layer of the P-type semiconductor substrate. two superconducting electrodes, and an MIS installed between the two superconducting electrodes.
A semiconductor-coupled superconducting element characterized by having a gate type, MES type, or junction type gate. 4. A P-type semiconductor substrate in which a two-dimensional electron gas in which a superconducting current flows is formed by diffusion of superconducting electrons due to the proximity effect in the surface inversion layer, and ohmic contact with the surface inversion layer of the P-type semiconductor substrate. What is claimed is: 1. A semiconductor-coupled superconducting element comprising: two superconducting electrodes, and an ohmic electrode formed on the P-type semiconductor substrate side.
JP60012134A 1985-01-24 1985-01-24 Semiconductor coupled superconductive element Granted JPS61171180A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60012134A JPS61171180A (en) 1985-01-24 1985-01-24 Semiconductor coupled superconductive element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60012134A JPS61171180A (en) 1985-01-24 1985-01-24 Semiconductor coupled superconductive element

Publications (2)

Publication Number Publication Date
JPS61171180A JPS61171180A (en) 1986-08-01
JPH0452632B2 true JPH0452632B2 (en) 1992-08-24

Family

ID=11797053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60012134A Granted JPS61171180A (en) 1985-01-24 1985-01-24 Semiconductor coupled superconductive element

Country Status (1)

Country Link
JP (1) JPS61171180A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910002311B1 (en) * 1987-02-27 1991-04-11 가부시기가이샤 히다찌세이사꾸쇼 A superconductor device
JPH0724338B2 (en) * 1987-03-18 1995-03-15 株式会社日立製作所 Electronic device
JPS6486575A (en) * 1987-06-17 1989-03-31 Hitachi Ltd Superconducting device

Also Published As

Publication number Publication date
JPS61171180A (en) 1986-08-01

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