JPH0452965B2 - - Google Patents

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (Fig. 1) Working Example (a) One Implementation Explanation of the overall configuration of the example (Figure 2) (b) Explanation of the configuration of the preemption control section (Figures 3 and 4)
(Figure) (c) Explanation of startup processing operation (Figures 5 and 6) (d) Explanation of host processing operation (Figures 7 and 8) (e) Explanation of drive processing operation (Figure 9) , 10th
(Figure) (f) Explanation of overall operation (Figure 11) (g) Explanation of other embodiments Effects of the invention [Summary] Magnetic tape that is equipped with a buffer that can store multiple instructions transferred from a higher level and that preempts instructions. In the instruction preemption control method of the device, by determining that the end area has been reached when the magnetic tape has traveled a certain distance from the vicinity of the end area during the execution of a write-related command.
This allows writing within the tape end area without reducing the number of prefetch instructions.

[Industrial application field]

The present invention relates to an instruction prefetch control method and apparatus for prefetching instructions from a higher level into the buffer in a magnetic tape device having a buffer capable of storing a plurality of instructions.

Magnetic tape devices are widely used as external storage devices for computers, and in recent years have been used particularly for backing up other external storage devices such as magnetic disk devices.

In such a magnetic tape device, the 12th
As shown in the figure, a tape drive unit 1 has a magnetic head that writes to and reads from a magnetic tape, and a magnetic tape drive unit that drives the magnetic tape.
and a control unit CT that controls this based on instructions from a host controller.

In recent years, a buffer BF has been installed within this control unit CT,
A system has been developed that performs command prefetch control that preempts commands and data from the host controller, stores them in the buffer BF, and causes the tape drive section 1 to sequentially execute the commands and data in the buffer BF, and has been put into practical use. ing.

Such a magnetic tape device is called a buffered magnetic tape device, and can operate the tape drive unit 1 asynchronously in response to commands from the host controller, so the host controller side can operate the tape drive unit 1 in response to one command. Since commands can be issued continuously without having to wait for completion, and the tape drive section 1 can also perform operations continuously without waiting for commands from the host controller, processing efficiency can be improved, especially in streaming mode. Operational efficiency can be improved.

[Conventional technology]

In order to have such a buffer BF and preempt instructions, the buffer BF is composed of an instruction buffer that can store multiple instructions and a data buffer that can store multiple data. 64 instructions, maximum for data buffer
It is designed to be able to store 256KBytes of data, allowing for prefetch instructions and data to be increased.

On the other hand, as shown in FIG. 13A, the magnetic tape 16 does not have an infinite length but a finite length, so at the end there is an EOT
(END OF TAPE) marker is attached,
The tape walking area (TWA) after EOT detection can only be used for approximately 3m.

Therefore, in write-based processing, if the prefetch command/data is 3 m or more when EOT is detected,
It becomes impossible to write this onto the magnetic tape 16,
Some kind of countermeasure is required.

Conventionally, this is why EOT, the end of magnetic tape,
Before detecting the tape end, a signal EWA near the end of the tape was generated.

This tape end vicinity signal EWA is detected from the tape winding diameter of the magnetic tape reel based on the ratio between the rotation angle of the magnetic tape reel per unit time and the amount of tape transport (measured by an idler).

This tape end vicinity signal EWA is, for example, EOT
This occurred approximately 20m before the
As shown in the figure, the amount of data buffer that can be stored (number of data bytes) of the buffer BF was reduced. For example, for a data buffer that can store up to 256 KB of data as shown in Figure 13B,
Until the amount of data accumulated in the data buffer becomes 128KByte or less, acceptance of write data from the host controller is not permitted, thereby preventing such writing failure.

[Problem that the invention seeks to solve]

According to such conventional technology, by limiting the capacity of the data buffer, the number of prefetching of write-related instructions is indirectly limited. The performance of this magnetic tape device is greatly affected by the number of prefetch instructions.

Furthermore, the rotation angle of the magnetic tape reel and the tape transport amount obtained from the idler, which are used to detect the conventional tape end vicinity signal EWA, can only be measured with sufficient accuracy to control the feeding of the magnetic tape. Therefore, in a general magnetic tape device, the tape winding diameter can only be detected at intervals of about 25 m, which is converted into the magnetic tape feeding length.

For this reason, in the conventional technology, signals near the end of the tape are
The EWA detection point could not be specified in detail, and furthermore, the EWA would occur at least 20 meters before EOT, making the early warning area (EWA) from EWA detection to EOT detection longer than necessary. Ta.

EOT limits the number of prefetching of write instructions.
The number of instructions that can be prefetched determines how far in advance of detection, but in order to avoid degrading the performance of the magnetic tape device, the timing of limiting the number of prefetching write instructions must be set appropriately. Must be set.

Therefore, as in the prior art, from EWA detection
If the number of instructions from the host controller is limited in the early warning area (EWA) up to EOT detection, the host controller will have to wait to issue instructions until the limited data buffer becomes available after the EWA detection point, and the instruction pre-emption will occur. There was a problem in that the number of magnetic tape devices was also limited, leading to a decline in streaming performance of the magnetic tape device.

The present invention provides an instruction prefetching control method and device for a magnetic tape device that does not limit the number of prefetched instructions from a host controller in EWA and can reliably execute prefetched instructions in TWA. With the goal.

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

In the present invention, when the magnetic tape drive section 1 runs the magnetic tape 16 and detects an area near the end of the magnetic tape (EWA), the control section CT counts and calculates the traveling distance of the magnetic tape from the point near the end area. When the numerical value ECTR reaches a certain value EPTR, it is assumed that the tape end area has been detected, and a pseudo EOT is obtained.

This pseudo-EOT has the same effect as normal EOT detection, whereby EOT is handled before actually detecting the EOT marker provided on the magnetic tape.

[Effect]

In the present invention, since a logical pseudo-EOT is obtained, the TWA can be lengthened by advancing the EOT detection time to a point where all prefetched write instructions can be executed as shown in FIG. 1A. For this reason, the number of blocks that can be written to the TWA increases, so as shown in FIG. 1B, there is no need to reduce the number of write-related instructions that are pre-fetched from the time the EWA is detected.

Therefore, the host controller is not subject to the prefetching restriction of write-related commands in EWA, and can prevent performance deterioration in streaming running. In other words, as shown in Figure 1C, the number of instructions prefetched is as large as possible until near EOT, and when EOT approaches,
This enables ideal preemption control to reduce the number to a writable number.

This prevents writing to TWA from becoming impossible and prevents performance from deteriorating.

〔Example〕

(a) Description of overall configuration of one embodiment FIG. 2 is an overall configuration diagram for explaining one embodiment of the present invention.

In the figure, the same components as those shown in FIG. )1
1 and a supply reel (file reel) 12, a magnetic tape 16 is attached to the roller 1 of the tension arm 15.
5a, a magnetic head 14, an idler 13, and a take-up reel 11.
4 is guided by guides 17a and 17b on both sides.

On the other hand, the take-up reel 11 and the supply reel 12 are rotationally driven by drive motors 10a and 10b, respectively, and rotary encoders 18a and 18b are provided on the drive motors 10a and 10b to detect the amount of rotation of the drive motors 10a and 10b. I'm trying to make it possible. Further, the idler 13 is also provided with a rotary encoder 19a, which makes it possible to monitor the actual running position of the tape, while the tension arm 15 is provided with a tension detector 19b.
This makes it possible to detect tape tension.

Reference numeral 2 denotes a drive control section, which drives the tape running and drives the head for writing or reading according to commands and data from a command/data prefetch control section, which will be described later.
a, 18b, and 19a to monitor the running state, and also monitor the tension from the output of the tension detector 19b.
a and 10b to drive the tape to run while keeping the tape tension constant, and also to drive the magnetic head 14.
It supplies write data to perform writing and receives read data from the magnetic head 14.

Reference numeral 3 denotes a command/data prefetch control unit which receives write or read commands and write data from the host controller, stores them, and sends write commands and write data to the drive control unit 2 in the case of write commands. If the operation is completed normally, the next block write command and write data are sent, and if the operation is not completed normally, the drive control unit 2
This causes a write retry operation.

The command/data prefetch control unit 3 has a command buffer and a data buffer, which will be described later, and operates as a magnetic tape device for the host controller.
For the drive control unit 2, it is an adapter that operates as a host controller.

(b) Description of the structure of the prefetch control section FIG. 3 is a block diagram of the main part in the structure of FIG. 2, that is, the instruction/data prefetch control section 3.

In the figure, 30 is a microprocessor (hereinafter referred to as MPU).
), which controls the reception of commands and data from the host controller and controls the transmission of data and status according to the microprogram in the program memory, which will be described later. Controls reception of data and status from the control unit,
3 further performs state control processing for drive 1;
1a is a program memory that stores programs to be executed by the MPU 30; 31b is a program memory;
is random access memory (hereinafter referred to as RAM)
, various data necessary for MPU30 processing,
It stores instructions and parameters, and has an instruction buffer area CBUF, an instruction buffer management area CA, a data buffer management area DA, various mode management areas EA, and a read instruction register RC.

The instruction buffer area CBUF contains the instruction prefetched from the host controller and the start address in the data buffer, byte count, etc. of the data transferred by the instruction in the case of a write command, and the read execution result of the prefetched block in the case of a read command. The start address and number of bytes in the data buffer of read data are stored, and the instruction buffer management area CA stores the instruction storage number CBSTK, buffer size CBSiZE, and final limit value CBE. The instruction storage number CBSTK is the number of prefetched instructions that are stored in the instruction buffer area CBUF and has not been executed yet for a write type command, and the number of prefetched blocks is stored for a read type command, and the buffer size CBSiZE
is the size of the instruction buffer area CBUF in terms of the number of instructions, and the final limit value is the logical
This is the final limit value for the number of write-related instructions prefetched in EWA when not in EOT mode.

The data buffer management area DA contains a buffer free capacity FSEG that indicates the free capacity of the data buffer in units (in units of 1KByte), and a buffer address BADR that indicates the start address of the data buffer at the time of data transfer for writing to the data buffer.
The maximum block length MAXL indicating the maximum length of the data block to be processed is stored.

The mode management area EA has recording density (1600rpi or 6250rpi) when writing from the load point.
Write recording density and logical
LEOT flag indicating EOT mode,
A travel counter ECTR is stored that stores the tape travel distance after EWA detection in the logical EOT mode.

32a is a drive interface circuit for exchanging control signals etc. with the drive control unit 2; 32b is a host interface circuit for exchanging control signals etc. with the host controller. Reference numeral 33 is a data transfer control circuit, which controls a data buffer (described later) to control data transfer with the host controller or the drive control unit 2, and issues a data transfer request signal to the host controller and controls the drive. It receives a data transfer request signal from part 2 and controls data transfer, and stores address counter to data buffer.
It has an SCTR, a load address counter LCTR from a data buffer, a byte counter BCTR when loading a buffer, and the like.

34 is a data buffer, which is controlled by the data transfer control circuit 33, stores write data from the host controller and transfers it to the drive control unit 2, and conversely stores read data from the drive control unit 2 and sends it to the host controller. 35 is a data bus, which connects the MPU 30, program memory 31a, RAM 31b, drive interface circuit 32a, host interface circuit 32b, and data transfer control circuit 33. It is used to connect and exchange commands and data.

36a is a control signal line, which is connected to the drive control unit 2.
36b is a tape end vicinity area detection signal line, which is used to send commands, etc. to the drive control unit 2, and conversely receive status etc. from the drive control unit 2. 36b is a tape end vicinity area detection signal line, which receives the tape end vicinity area detection (EWA) signal from the drive control unit 2. 36c is an interrupt line for the transfer of the drive interface circuit 32.
Something that notifies the MPU 30 of an interrupt from a, 37
37b is a data transfer control signal line for transmitting a data transfer request signal from the drive control unit 2 to the data transfer control circuit 33 and a data transfer end signal to the drive control unit 2; 37b is a write data bus; , for transmitting write data from the data buffer 34 to the drive control unit 2, 3
7c is a read data bus for transmitting read data from the drive control unit 2 to the data buffer 34; 38 is a control signal line for exchanging commands and status with the host controller; 39a is a data bus A transfer control signal line is used to transmit a data transfer request signal to the host controller and a data transfer end signal from the host controller. 39b is a write data bus that transmits write data from the host controller to the data buffer 34. A read data bus 39c is used to transmit read data from the data buffer 34 to the host controller.

Therefore, the MPU 30 communicates via the data bus 35.
RAM31b, host interface circuit 32
b, writes and reads between the drive interface circuit 32a and the data transfer control circuit 33, and performs desired processing.

That is, the host interface circuit 32b exchanges commands and status with the host controller under the control of the MPU 30 via the control signal line 38, and the drive control unit 2 and the control signal line 36a.
The drive interface circuit 32a exchanges commands and status under the control of the MPU 30 via the MPU 30.

On the other hand, in response to instructions from the MPU 30, the data transfer control circuit 33 issues a data transfer request to the host controller via the data transfer control signal line 39a, and in response, the host controller transfers the write data to the data buffer 3 via the write data bus 39b.
4 and accumulate it. In addition, the drive control section 2
In response to a data transfer request from the data transfer control signal line 37a, the data transfer control circuit 33 issues write data from the data buffer 34 to the drive control section 2 via the write data bus 37b.

Further, the data transfer control circuit 33 stores read data from the drive control unit 2 via the read data bus 37c in the data buffer 34 according to instructions from the MPU 30, and transmits the read data from the data buffer 34 to the host controller via the read data bus 39c.

The drive control unit 2 detects the vicinity of the tape end area by monitoring the running position using the rotary encoder 19a, and transmits the EWA signal to the signal line 36b.
and sends a TWA signal to signal line 3 upon EOT detection.
Emit at 6a.

As shown in FIG. 4A, such an interface between the preemption control unit 3, the host controller, and the drive (device) 1 is such that the MPU 30 is connected to the host controller by receiving the activation signal GO and command signal from the host controller. A response signal FBY is sent back to the host controller via the interface circuit 32b, and a data busy DBY indicating that the command is being executed is also given to the host controller.

If the command signal is a write command that involves data transfer, the data transfer control circuit 33 gives a write strobe pulse WSTB to the host controller, and the host controller transfers the write data in synchronization with the write strobe pulse WSTB, sequentially to the data buffer. Stored. The host controller sends the last word signal LWD to the data transfer control circuit 33 at the same time as the final write data.
The control circuit 33 sends this last word signal to
Light strobe pulse when detecting LWD
Stops WSTB transmission, terminates data transfer, provides a status signal indicating normal/abnormal reception operation to the host controller, turns off data busy DBY, and terminates write data transfer operation. still,
The received command is stored in the command buffer CBUF.

On the other hand, if the command is a read command, the read data read from the tape drive 1 is transferred to the host controller together with the read strobe pulse RSTB. The end of read data transfer is notified to the host controller by turning off data busy DBY.

Such an interface procedure is shown in Figure 4B.
As shown in , the same is true between the prefetch unit 3 and the drive 1, and when the command buffer CBUF and data buffer 34 of the prefetch unit 3 are full, even if a GO signal or a write command arrives from the host controller, the buffers CBUF and 34 are data busy until free
I try not to raise DBY and make data transfer wait.

(c) Description of startup processing operation in one embodiment FIG. 5 is a startup processing flow diagram of one embodiment of the present invention, and FIG. 6 is an initialization processing flow diagram in FIG. 5.

When the power is turned on, the MPU 30 checks the write recording density setting of the drive via the drive interface circuit 32a, and stores the write recording density setting of the drive in the write recording density of the area EA of the RAM 31b. Then, the initial setting process (1) shown in FIG. 6A is performed. That is, MPU30 is
Clear the instruction storage number CBSTK in the instruction buffer management area CA of RAM31 to zero, set the buffer free capacity FSEG in the data buffer management area DA to the maximum of 256, and set the data buffer address
Set BADR to “00”.

Furthermore, the maximum block length MAXL of the data buffer management area DA is set to the minimum 8 units (8KByte).
, turn off the logical EOT mode flag of the area EA, and finish the initial settings (1).

Next, when the power is turned on, after the initial settings are completed after executing the REW command or UNL command, or in a routine waiting for startup from the host, the MPU 30
5 through the drive interface circuit 32a.
It is checked whether the magnetic tape is set on the supply reel 12 and in an online state via the magnetic tape.

When online, the MPU 30 connects to the host interface circuit 32b via the bus 35.
The contents of the register are checked to see if a REW (rewind) command or UNL (unload) command has arrived from the host.

If a REW or UNL command has arrived,
The MPU 30 checks whether the execution processing mode of the drive control unit 2 is read type, write type, or not currently being executed.

If the execution processing mode is read, drive 1
Stop reading ahead. That is, when the drive control unit 2 finishes the process being executed, the control line 36a is transmitted via the drive interface circuit 32a.
Therefore, the drive control unit 2 is not instructed to perform any new processing, and the read-related processing is stopped.

On the other hand, if the execution processing mode is write type, all write type instructions in the instruction buffer CBUF are executed.

After executing all instructions, if there is no processing in progress, or after stopping drive processing, the MPU 30
via the drive interface circuit 32a
REW command (return tape to BOT) or
Give the UNL command (wind up the tape) to make drive 1 execute it, and return to the initial setting of the step.

On the other hand, if the REW instruction or UNL instruction has not arrived, the MPU 30 checks the contents of the register of the host interface circuit 32b via the bus 35 to see if there is a start (GO) from the host.

If there is no activation from the host, the process waits for activation and returns to step.

When it is determined that there is activation from the host, that is, a GO signal has been received, the MPU 30 checks the contents of the register of the host interface circuit 32b via the bus 35, and determines what the given command is.

If the given command is a read type command, the process goes to step, and if it is a recording density setting, the process goes to step and executes the processing routine.

If the command is to set the recording density, the MPU 30 notifies the data busy DBY to be turned on via the host interface circuit 32b, and also notifies the drive 1 via the drive interface circuit 32a.
Check whether the magnetic tape 16 is located at the load point LDP, ie, BOT.

If it is at the load point LDP, the recording density setting command is valid, so the MPU 30 executes the recording density setting command to the drive via the drive interface circuit 32b.
The recording density set by the host is set to the write recording density of area EA of RAM 31b.

If it is not at the load point LDP, the recording density setting command is invalid and there is no need to set the write recording density.

Thereafter, the MPU 30 reports completion to the host via the host interface circuit 32b, turns off the data busy DBY, and returns to step.

On the other hand, if the given command is light type,
The MPU 30 checks whether the execution processing mode of the drive control unit 2 is read type, write type, or not currently being executed.

If the execution processing mode is read, drive 1
Stop the read ahead processing. That is, when the drive control section 2 finishes the process being executed, the control line 3 is transmitted via the drive interface circuit 32a.
6a, the drive control unit 2 is not instructed to perform any new processing, and the read-related processing is stopped.

Next, execute the initial settings (2) in Figure 6A,
The MPU 30 clears the instruction storage number CBSTK in the instruction buffer management area CA of the RAM 31 to zero,
Set the buffer free capacity FSEG in the data buffer management area DA to the maximum of 256, and set the data buffer address BADR to "00".

After completing this step or if the drive control unit 2 is not running, the initial settings (3) in Figure 6B
Set the buffer size.

First, the MPU 30 checks whether the EWA (area near the end of the tape) signal on the signal line 36b is on or off via the drive interface circuit 32a, and if it is off (has not yet reached the area near the end of the tape), the EWA signal of the RAM 31b is checked. Area EA
Turn on the LEOT mode flag and turn on the travel counter
Clear ECTR to zero.

On the other hand, if the EWA signal is on, RAM31b
Checks whether the LEOT mode flag is on (YES) or off (NO), and if it is off, moves the final limit value CBE of the instruction buffer management area CA to the buffer size CBSIZE and returns.

Conversely, after the LEOT mode flag is turned on or the aforementioned travel counter ECTR is cleared to zero, the MPU 30
The buffer size CBSIZE in the instruction buffer management area CA of the RAM 31b is set to the maximum value "64" and the process returns.

Next, the MPU 30 adjusts the tape position by
A command (space or buffer space) for tape position adjustment is given to the drive control unit 2 via the drive interface circuit 32a.

The program then proceeds to a write-related processing routine in FIG. 7, which will be described later.

On the other hand, if the execution processing mode in the step is write type, the process immediately advances to the write type processing routine.

If the instruction transferred in the step is a read type instruction, the MPU 30 checks whether the execution processing mode of the drive control unit 2 is read type, write type, or not being executed.

If the execution processing mode is read type, MPU30
First, it is checked whether the read directions match, and if the read directions do not match, the pre-reading process of the drive 1 is stopped. That is, when the drive control section 2 finishes the process being executed, the drive control section 2 is not instructed to perform any new processing via the control line 36a via the drive interface circuit 32a, and the read-related processing is stopped.

Furthermore, the MPU 30 executes the same initial setting (2) as in the step, and then performs the tape position adjustment as in the step.

On the other hand, if the execution processing mode is write, all instructions in the instruction buffer section CBUF are executed.

Then, after all instructions are executed, if there is no process being executed, or after the drive process is stopped, the above-mentioned prefetch read-related instructions are set in the read instruction register RC of the RAM 31b.

After this setting, or if the read directions match, the process advances to the read-related processing routine shown in FIG.

Therefore, if the activation from the host is a write-related command, even if read-related processing is in progress, it switches to write-related processing, and if it is write-related processing, write-related processing is continued.

And the initial setting (1) is the maximum block length MAXL
is the minimum unit of 8, and with the initial setting (1) or (2), the number of instruction memory CBSTK is zero, and the data buffer free space is
FSEG is maximum 256, data buffer address
BADR is set to (00), and in the initial setting (3), the buffer size CBSIZE is set to the maximum 64 or the final limit value CBE, depending on whether the LEOT mode is on or off.

Also, the area where the write recording density is RAM31b
Set to EA.

(d) Description of host-related processing operation FIG. 7 is a flowchart of host-based write system processing.

When the MPU 30 is activated by a write command from the host controller as shown in FIG.
The instruction memory number CBSTK of CA and the instruction buffer size CBSiZE are read out via the bus 35 and compared. If CBSiZE≦CBSTK, that is, write-related instructions are stored in the instruction buffer CBUF up to the number of instructions that can be stored, storage of the write-related commands in the instruction buffer CBUF is suspended.

On the other hand, if CBSiZE>CBSTK, the write-related instruction can be stored in the instruction buffer CBUF, so the MPU 30 checks whether the write-related instruction uses the data buffer 34 or not.
If the erase/write tape mark data buffer 34 is not used, turn on the data busy DBY and set the final limit value of the step.
Proceed to the CBE initial configuration steps.

As shown in FIG. 5A, when a start (GO) command is given from the higher level (host), the lower level (preemption control unit 3) will, if the command can be executed,
It turns on the data busy DBY signal indicating that it is being executed and returns it to the upper level. This relationship is the same even when the prefetch control section 3 is placed at the upper level and the drive control section 2 is placed at the lower level.

Conversely, if the write-related instruction is a normal write instruction that uses the data buffer 34, the MPU 30 determines whether automatic transfer to the data buffer 34 is permitted.

That is, first, the MPU 30 reads the free buffer capacity FSEG and the maximum block length MAXL of the data buffer management area DA of the RAM 31b, and
Free buffer capacity FSEG is maximum block length
Check whether it is greater than or equal to MAXL. If the free buffer capacity FSEG is less than the maximum block length MAXL,
It suspends the reception of write data and waits until the data buffer 34 is free for the maximum block length MAXL.
Free buffer capacity FSEG is maximum block length
If it is more than MAXL, transfer is allowed. Therefore, the aforementioned data busy DBY signal is turned on to notify the host controller that transfer is possible.

Next, the MPU 30 checks whether the magnetic tape 16 of the drive 1 is located at the load point LDP via the drive interface circuit 32a.

If it is not at the load point LDP, the final limit value CBE has already been set, so
Proceed to the next automatic transfer step.

On the other hand, if it is located at the load point LDP,
The final limit value CBE is set based on the write recording density.

That is, the MPU 30 checks the write recording density of the mode area EA of the RAM 31b, and if the write recording density is 1600 rpi, sets the final limit value CBE of the instruction buffer management area CA of the RAM 31b to "8".
Similarly, for 6250rpi, the final limit value CBE is "16"
and proceed to the next step.

Next, the MPU 30 checks whether the write-related instruction uses the data buffer 34 or not.

If the data buffer 34 is not used,
Proceed to the instruction storage step.

On the other hand, if the data buffer 34 is used, data transfer is executed.

Next, the MPU 30 reads the first buffer address BADR of the data buffer management area DA of the RAM 31b, and
Set the store address counter SCTR of
The data transfer control circuit 33 is activated. As a result, the data transfer control circuit 33 issues a data transfer request to the host controller via the data transfer control signal line 39a.

Therefore, the host controller transfers the write data from the write data bus 39b to the data buffer 34, and the write data is stored in the data buffer 34 according to the address of the store address counter SCTR of the data transfer control circuit 33. The store address counter SCTR counts up every time one byte of write data is transferred.

When the data transfer control circuit 33 determines that the data transfer has ended, the MPU 30 reads out the store address counter SCTR of the data transfer control circuit 33, calculates the difference between the data buffer address BADR in the data buffer management area DA, and calculates the difference between the buffer address BADR and the byte of the transferred write data. Find the number BC.

Next, the MPU 30 uses the instruction buffer CBUF and data buffer management area DA of the RAM 31b.
Update.

First, the buffer address (ie, the start address of write data) BADR of the data buffer management area DA of RAM 31b and the calculated number of bytes BC of write data are stored in the relevant instruction column of the instruction buffer CBUF of RAM 31b.

Next, the number of used units USEG of the data buffer 34 is subtracted from the free capacity FSEG of the data buffer management area DA of the RAM 31b, this free capacity FSEG is updated, and the buffer address
Add the number of used units USEG to BADR and update the start address BADR.

Next, the MPU 30 uses the aforementioned number of units to be used (reception block length) USEG and the maximum block length MAXL of the data buffer management area DA of the RAM 31b.
Compare with.

As a result of this comparison, if the number of used units USEG is larger than the maximum block length MAXL, the maximum block length MAXL of the data buffer management area DA is updated to this number of used units USEG. Furthermore, the final limit value CBE is changed depending on the recording density and the maximum block length MAXL.

That is, the MPU 30 reads the recording density of the drive and the maximum block length MAXL of area DA, and if the recording density is 1600rpi, the maximum block length is
If MAXL is greater than "16", the final limit value is set to the minimum "2", and if the maximum block length is less than "16", the final limit value CBE is set to "4".

Similarly, when the recording density is 6250rpi, if the maximum block length MAXL is greater than "32", the final limit value CBE is set to "2", and the maximum block length MAXL is set to "2".
is between "17" and "32", the final limit value CBE is set to "4", and when the maximum block length MAXL is "16" or less, the final limit value CBE is set to "8".

Conversely, the number of units used is USEG, which is the maximum block length.
If it is less than MAXL, the maximum block length MAXL and final limit value CBE are not updated and the process advances to step.

Next, the MPU 30 performs storage processing of the received write-related command.

First, the MPU 30 connects the host interface circuit 32 to the instruction buffer CBUF of the RAM 31b.
Store the received command of b.

Next, in order to update the instruction buffer management area CA of the RAM 31b, the MPU 30 updates the number of instructions stored in the RAM 31b.
Add "1" to CBSTK and update.

Furthermore, the MPU 30 checks the drive interface circuit 32a and checks the EWA of the control line 36b.
(Detection near end of tape) Check whether the signal is on or off. If it is off, the magnetic tape 16 has not reached the vicinity of the end of the tape, so the process advances to step.

On the other hand, if it is on, it means that the tape has reached near the end of the tape, so the area EA of RAM31b is
If the LEOT flag is checked and the mode is LEOT, there is no need to change the instruction buffer size CBSiZE.
Proceed to step.

Conversely, if it is not LEOT mode, MPU30
reads and compares the instruction buffer size CBSiZE and the final limit value CBE in area CA of the RAM 31b. If the instruction buffer size CBSiZE is less than the final limit value CBE, the instruction buffer size
Proceed to step without changing CBSiZE. Conversely, if the instruction buffer size CBSiZE is larger than the final limit value, "2" is subtracted from the instruction buffer size CBSiZE, updated, and the process proceeds to step.

Next, the MPU 30 checks whether the drive control unit 2 is executing a process, and if it is not executing a process (if it is stopped), performs a drive activation process, which will be described later with reference to FIG.

During processing or when drive startup processing is performed, the MPU 30 transmits a TWA signal indicating that the drive control unit 2 has detected EOT via the drive interface circuit 32a to the control line 36a.
Check to see if it is occurring more frequently.

In addition, in the LEOT mode, the MPU 30 checks whether a logical EOT is detected (on) when the travel counter ECTR, which is updated by the drive-related processing shown in FIG. 10, which will be described later, exceeds a certain value EPTR.

If a TWA signal is generated by EOT detection or
If LEOT detection (on), MPU30
Check whether the number of stored instructions (number of unexecuted instructions) CBSTK in the instruction buffer management area CA of the RAM 31b is zero, and if it is not zero, wait until it becomes zero by drive execution. This is to synchronize the commands from the host and the commands executed by the drive in processing after EOT and LEOT.

or LEOT when TWA signal is not occurring
When the MPU 30 is off, the MPU 30 checks from the state of the data transfer control circuit 33 whether the write data transfer in the above-mentioned step has overflowed due to insufficient free space in the data buffer 34.

In the event of an overflow, in order to synchronize as described above, the MPU 30 checks whether the number of stored instructions (number of unexecuted instructions) CBSTK in the instruction buffer management area CA of the RAM 31b is zero, and if it is not zero, it is Wait until it reaches zero.

When no buffer overflow occurs or when CBSTK becomes zero, the MPU 30 is sent to the host controller by the host interface circuit 3.
From 2b, report the completion (normal reception or error) and turn off the data busy DBY signal.
The process returns to the startup waiting routine shown in FIG.

FIG. 8 is a flowchart of host read system processing.

When the MPU 30 receives a read command and performs the startup process through the steps in the startup process flow shown in FIG. 5, the MPU 30 turns on the data busy DBY via the host interface circuit 32b.
Notify the host controller of the start of execution.

Next, the MPU 30 uses the area of RAM 31b.
Subtract "1" from the number of CA look-ahead blocks CBSTK.

Furthermore, the MPU 30 checks whether the drive control unit 2 is executing a process, and if it is not executing a process (if it is stopped), performs a drive activation process which will be described later with reference to FIG.

In addition, the MPU 30 checks whether the number of instructions stored (preread block number) CBSTK in the area CA mentioned above is "0" or more, and if it is a negative value smaller than "0",
Since the read data has not been transferred to the data buffer 34, CBSTK is "0" or more, that is,
Wait until one or more blocks of read data are transferred from the drive 1 to the data buffer 34.

When the number of read-ahead blocks CBSTK becomes "0" or more, read data should have been transferred from drive 1 to data buffer 34.
The MPU30 is the instruction buffer of the RAM31b.
Read execution result from CBUF, start address RADR in data buffer 34 of read data,
Read the read byte count RBC.

Next, the MPU30 performs the steps described above.
Check whether the load point LDP was detected when the drive processed the block based on the read execution result read from the instruction buffer CBUF of RAM31b.
If LDP is detected, check the read direction,
In the read reverse direction, before block detection
Since BOT has been reached and the read data has not been transferred to the data buffer 34, the process advances to step.

On the other hand, if the read direction is the read forward direction, the first block was read from the load point LDP, so the recording density is checked from the read execution result. The recording density of the read execution result indicates the recording density of the magnetic tape read.

And if the recording density is 1600rpi, RAM31b
Final limit value of instruction buffer management area CA
Set "8" to CBE, and similarly set "16" to final limit value CBE for 6250rpi.

Furthermore, if the MPU 30 is not at the load point LDP or after the final limit value CBE is set,
It is checked from the read execution result whether a tape mark indicating a file break was detected during the read execution. If a tape mark is detected, the read data has not been transferred to the data buffer 34, so no data transfer is performed and the process proceeds to the step. move on.

Conversely, if no tape mark is detected,
Proceed to automatic transfer step.

First, the MPU 30 determines whether the aforementioned read-related command involves data transfer. Read instructions that do not involve data transfer include Space, Backspace, and Backspace.
Space), Space File, and Back Space File. For read instructions that involve data transfer,
Executes data transfer to the host controller.

That is, the MPU 30 sets the first buffer address RADR read from the instruction buffer CBUF of the RAM 31b in the load address counter LCTR of the data transfer control circuit 33, sets the number of read bytes in the byte counter BCTR, and starts the data transfer control circuit 33. .

As a result, the data transfer control circuit 33 transfers the read data in the data buffer 34 to the host controller in accordance with the read strobe pulse RSTB (FIG. 4A) and the address of the load address counter LCTR. The load address counter LCTR counts up every time one byte of read data is transferred.

When the data transfer control circuit 33 determines that data transfer for the number of read bytes has been completed, the MPU 30
The number of used units USEG is added to the free capacity FSEG of area DA of the RAM 31b and updated.

On the other hand, since the read data is transferred to the data buffer 34 even in the case of a read-related instruction that does not involve data transfer, the free capacity FSEG is updated in the same way.

Next, the MPU 30 checks whether the aforementioned read-related command is a file search-based command (space file or backspace file), and if it is a file search-based command, returns to step. In other words, file search instructions are divided into read instructions.

On the other hand, if the step is not a file search command, the read direction is reversed, or a tape mark is detected, the host controller MPU 30 not only reports completion (normal reception or error) from the host interface circuit 32b but also indicates data busy. Turn off the DBY signal and return to the startup waiting routine shown in FIG.

In this way, in write processing, in the logical EOT mode, the buffer size CBSiZE is not limited in steps, but by turning on logical EOT, prefetching instructions are prohibited in steps in the same way as when turning on normal EOT.

On the other hand, when not in logical EOT mode,
The final control value CBE is changed according to the recording density and maximum block length MAXL (step),
In EWA, the buffer size is sequentially decreased in steps.

Further, in read-related processing, prefetching is performed regardless of the type of read-related command.

(e) Description of drive processing operation FIG. 9 is a flowchart of drive activation processing.

() In order to start the drive, MPU30
The next instruction to be executed is read from the instruction buffer CBUF of the RAM 31b and checked to see if it is a write type instruction.

If it is not a write-related instruction, that is, if it is a read-related instruction, the MPU 30
Check whether the number of look-ahead blocks CBSTK of CA is a negative value smaller than zero. If CBSTK is greater than or equal to zero, it is already read ahead, so check whether it is okay to start. Returns if it cannot be started (an error was detected during read ahead and stopped).

On the other hand, if bootable, RAM31b area
Check whether the number of look-ahead blocks CBSTK of CA is smaller than "63". If it is not, the instruction buffer CBUF in RAM 31b is full, and the process returns.

On the other hand, if the number of look-ahead blocks is less than 63,
Checks whether the free space FSEG is 64K bytes or more, and if it is less, returns as data transfer is not possible.

() Step () free space FSEG is 64K
If it is a byte or more, the data can be transferred from the drive 1, so the MPU 30 sets the start address BADR of the RAM 31b in the store address counter SCTR of the data transfer control circuit 33, and puts the data transfer control circuit 33 into a standby state.

Next, the MPU 30 checks whether the EWA signal is on or off from the drive interface circuit 32a, and if it is on (YES), it is in EWA.
Turn off the LEOT mode flag of RAM31b and cancel LEOT mode.

Furthermore, the MPU 30 checks whether the read-related command is a read reverse, and if it is a read reverse, turns off the logical EOT.

After this OFF, or if the EWA signal is not OFF or read reverse, the MPU 30 issues a start (GO) signal and the read related command to the drive 1 via the drive interface circuit 32a, and returns.

() On the other hand, if it is determined in step () that it is a write-related command, preparations for automatic transfer to the drive are made.

That is, the MPU 30 reads the write-related instruction from the instruction buffer CBUF of the RAM 31b, and checks whether this instruction involves data transfer.
If the instruction involves data transfer, MPU30
is the start address WADR and number of bytes WBC of the instruction buffer CBUF of the RAM 31b and the load address counter of the data transfer control circuit 33.
Set LATR and byte counter BCTR respectively.

Furthermore, the data transfer control circuit 33 is put into a standby state. After this standby state, or if it is a write instruction (erase, write tape mark, etc.) that does not involve the aforementioned data transfer, the MPU
30 issues the read command and a start (GO) signal to the drive control section 2 from the control line 36a via the drive interface circuit 32a, and returns.

On the other hand, when the drive control section 2 receives the activation signal and command at the above-mentioned steps () and (),
It responds with data busy DBY turned on and starts executing the relevant command.

For example, in the case of a write command that involves data transfer, a data transfer request is sent to the data transfer control circuit 33 from the data transfer control signal line 37a after data transfer preparation is completed. As a result, the data transfer control circuit 33 sends write data for the number of bytes of the byte counter BCTR from the start address indicated by the load address counter LCTR of the data buffer 34 to the drive control unit 2 via the write data bus 37b, and causes it to be executed. The magnetic tape 16 is written.

Furthermore, when the execution of the write-related command in the drive control section 2 is completed, a completion report is sent to the drive interface circuit 32a via the control line 36a. The drive interface circuit 32a thereby interrupts the MPU 30 and interrupts the processing shown in FIGS. 5 to 8.

FIG. 10 is a flowchart of drive write/read processing.

() When the MPU 30 receives a completion report from the drive, it checks whether the type of the completed instruction is a read type or a write type, and if it is a read type, it proceeds to step ().

On the other hand, if the completed instruction type is write type,
MPU30 is drive interface circuit 3
Check whether the EWA signal is on or off via 2a.
If it is off (NO), proceed to step ().

If the EWA signal is on (YES), it is within the termination vicinity area (EWA), so the MPU 30
Check the LEOT mode flag of area EA of RAM 31b to determine whether it is in LEOT mode.

If it is not LEOT mode, it is normal EOT mode, so proceed to step ().

Conversely, in LEOT mode, step () is used to increment the travel counter and detect the LEOT detection point.
Proceed to.

() First, the MPU 30 checks the recording density of the drive.

To determine whether the recording density is 6250rpi or 1600rpi, check the write tape mark length in the travel counter increment and LEOT detection point detection process below.
WTM, erase length ERS, IBG length, judgment value
This is to make the EPTR different, but the processing itself is exactly the same.

That is, the MPU 30 checks whether the instruction in the instruction buffer CBUF is a write instruction, erase variable instruction, write tape mark instruction, or fixed erase instruction.

If the instruction is a write instruction or an erase variable instruction, the number of bytes in the instruction buffer CBUF RBC
is converted into the number of used units USEG, and added to and updated to the running count value ECTR of area EA in the RAM 31b.

Furthermore, if the command is a write tape mark command, the write tape mark length WTM, which is a fixed value, is similarly added and updated to the running count value ECTR.

Furthermore, if the instruction is a fixed erase instruction, the fixed erase length ERS is similarly added and updated to the running count value ECTR.

Furthermore, the IBG length is set to the running count value.
Add and update to ECTR.

Next, the MPU 30 uses this traveling count value ECTR and the judgment value to detect the LEOT detection point.
Compare with EPTR. If ECTR≧EPTR
Since the LEOT detection point has been reached, logical
Turn on EOT. If ECTR<EPTR, logical EOT will not be turned on.

() Next, the MPU 30 checks whether the relevant write-related instruction is an instruction that uses the data buffer 34,
If the instruction is to be used, the number of used units USEG is added to the free capacity FSEG of the data buffer management area DA of the RAM 31b, and the free capacity FSEG is updated.

Next, after this update or data buffer 34
When not in use, the number of instructions stored in the instruction buffer management area CA of RAM31b CBSTK
Subtract "1" from and update.

Furthermore, the MPU 30 checks whether the instruction storage number CBSTK in the RAM 31b is zero, and if it is zero, returns to the routines shown in FIGS.
Execute steps after step () in the diagram.

In this way, the drive sequentially executes the instructions in the instruction buffer asynchronously with the host controller.

() On the other hand, when the instruction type is determined to be a read type in step (), the MPU 30 checks whether the instruction is a read reverse, and if it is a read reverse, checks whether the LDP signal is rising from the drive 1 or not to the drive interface circuit. 32a. If the LDP signal is not rising, or if it is a lead forward, it is checked via the drive interface circuit 32a whether the tape mark detection signal is rising.

If the tape mark detection signal does not rise,
The number of bytes BC of read data transferred to the data buffer 34 upon completion of drive processing is calculated.

That is, the MPU 30 is the data transfer control circuit 33
Read the store address counter SCTR of the buffer address of the data buffer management area DA.
Calculate the difference from BADR to find the number of bytes of read data transferred BC.

Next, the MPU 30 uses the instruction buffer CBUF and data buffer management area DA of the RAM 31b.
Update.

First, the buffer address BADR of the data buffer management area DA of the RAM 31b (ie, the start address of pre-read read data) and the calculated number of bytes BC of the read data are stored in the relevant instruction column of the instruction buffer CBUF of the RAM 31b.

Next, the number of used units USEG of the data buffer 34 is subtracted from the free capacity FSEG of the data buffer management area DA of the RAM 31b, this free capacity FSEG is updated, and the buffer address
Add the number of used units USEG to BADR and update the start address BADR.

Furthermore, the MPU 30 checks whether the drive 1 operates in the forward direction and detects EOT.

If the result is YES, the read execution result (EOT detection) is stored in the corresponding read data storage column of the instruction buffer CBUF, and the process returns to the routine of FIGS. 5 to 8.

Similarly, in the case of LDP detection in tape mark detection and read reverse, the instruction buffer
This is stored in the CBUF and the process returns to the routine shown in FIG. 7 or 8.

On the other hand, if the result of the above-mentioned EOT detection etc. of the MPU 30 is NO, the read execution result (non-detection) is similarly stored in the corresponding read data storage column of the instruction buffer CBUF.

Furthermore, MPU30 uses area CA of RAM31b.
Check whether the number of read-ahead blocks CBSTK is 63 or more, and if it is 63 or more, read ahead is not possible and the fifth
Returning to the routines shown in FIGS. 8 through 8, if the number is less than 63, the process returns to step () in FIG. 9 to execute prefetch reading.

(f) Description of overall operation The operations shown in FIGS. 5 to 10 can be summarized as follows.

In the write system operation, (1) In the initial setting () of the step in Fig. 5, that is, in Fig. 6C, in the LEOT mode, the buffer size CBSiZE is the maximum ``64'' and is not limited;
In normal EOT mode, buffer size
CBSiZE is changed by the final limit value CBE.

(2) At the step in Figure 7, the final limit value
CBE changes depending on recording density and maximum block length.

(3) In normal EOT mode, the early warning area is
Within EWA, buffer size CBSiZE decreases by "2" if it exceeds the final limit value CBE.

For example, the number of write instructions that can be accumulated in the instruction buffer is 64, but is gradually reduced as shown by the dotted line in FIG. 11B.

Therefore, in order to limit the number of write-related instructions that can be stored, write-related instructions such as erase and write tape mark that do not involve write data are also limited, so all write-related instructions can be stored in the magnetic tape (especially in the TWA). can be executed, and the inability to process write instructions can be prevented.

That is, when the tape reaches near the end and the EWA signal turns on, the buffer size CBSiZE is decreased from the maximum value "64" by "2" each time a write command is received from the host controller.
The number of instruction storage permissions gradually decreases. Further TWA
When the (EOT) signal is issued, the number of instructions stored
Do not report completion until CBSTK reaches zero.

Therefore, the number of prefetch instructions gradually decreases as shown by the dotted line in FIG. 11C.

This gradual decrease prevents the host controller from taking an extremely long time to accept the next command. On the other hand, if the number decreases all at once, the host controller will not accept the next instruction until the drive executes the number of instructions equal to (the number of accumulated instructions) - (the number of instructions that can be accumulated after the decrease - 1). Therefore, the host controller's time monitoring will treat this as an abnormality in the device due to a timeout, resulting in an inconvenience.

Gradual reduction can therefore prevent this disadvantage. This gradual reduction is performed when the value is greater than or equal to the final limit value CBE, and the final limit value CBE is sequentially changed according to the recording density and the maximum block length.

(4) On the other hand, in logical EOT mode, the seventh
In the step shown in the figure, the buffer size
No gradual reduction or limitation of CBSiZE takes place.

Then, in step ( ) of FIG. 10, the tape running distance is measured as the running count value ECTR from the detection of the early warning area EWA, and when this reaches the limit value EPTR,
As logical EOT point detection, LEOT is turned on and normal EOT is activated in the steps shown in Figure 7.
The same treatment as detection is performed.

Therefore, in the LEOT mode, the buffer size CBSiZE is not limited until the LEOT point is detected as shown in FIG. 11B, and at the LEOT point detection, CBSiZE becomes substantially zero as in the EOT mode.

Therefore, in the LEOT mode, the number of stored instructions CBSTK decreases from the detection of the LEOT point, as shown in FIG. 11C.

(5) Furthermore, in LEOT mode, as shown in step () in Figure 9, if the count value cannot be guaranteed due to reception or execution of a read-related command after tape travel distance counting has started (after EWA is turned on), , the logical EOT mode is turned off and shifts to the normal EOT mode.

(6) Also, as shown in the step in Figure 7, when a start (GO) is received from the host controller and a write command is given, it is first checked to see if the number of instructions that can be stored in the instruction buffer is within the memory capacity. If the number is within the limit, this command is accepted; if the number exceeds the maximum number of commands that can be stored, acceptance of this command is suspended and the data busy DBY is not raised.

That is, as shown in FIG. 4B, the drive side executes the instructions in the instruction buffer and does not raise the data busy until the number of instructions is within the storable number of instructions. Notify the host controller.

Similarly, in the step, it is checked whether the free capacity of the data buffer is greater than or equal to the maximum block length, and if it is greater than or equal to the maximum block length, the write data is transferred from the host controller, and if it is less than the maximum block length, the data transfer is suspended. Do not increase data busy DBY.

Therefore, the drive side executes the instructions in the instruction buffer and does not raise the data busy until the free capacity of the data buffer becomes equal to or greater than the maximum block length, and when it becomes equal to or greater than the maximum block length, the data busy is raised and transfer can be accepted. .

Then, in the step, if the transferred block length is larger than the maximum block length, the actually transferred block length is adopted as the maximum block length from next time onwards.

Therefore, the effect of reducing the number of retries and shortening waiting time is produced.

(g) Description of other embodiments In the above embodiment, in the EOT mode, the number of write-related commands that can be stored is gradually reduced each time a write-related command is received from the host. Often, the number may be gradually decreased each time a plurality of instructions are executed on the drive side.

Further, the drive control section 2 and the command data prefetch control section may be integrated, and the drive 1 may also have a tape buffer.

Furthermore, there is no normal EOT mode, and logical
It may be only the EOT mode, and the maximum block length MAXL may not be changed depending on the reception block, but may be changed in steps.

Although the present invention has been described above with reference to examples, the present invention can be modified in various ways according to the gist of the present invention.
These are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, the number of prefetching of write-related instructions is determined by the early warning area.
Since there is no need to limit EWA, a large number of instructions can be prefetched until near EOT, which has the effect of allowing streaming to be maintained for a long time, contributing to improved performance.

Further, since the tape warning area TWA can be made long, the number of blocks that can be written to the TWA becomes large, and an effect that the command given to the TWA can be reliably executed is produced.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is an overall configuration diagram of an embodiment of the invention, Fig. 3 is a main part configuration diagram of the configuration shown in Fig. 2, and Fig. 4 is a data transfer diagram of the configuration shown in Fig. 2. An operation explanatory diagram, FIG. 5 is a flowchart of the startup process of an embodiment of the present invention, FIG. 6 is a flowchart of the initialization process of FIG. 5,
FIG. 7 is a flowchart of write-related processing for the host according to an embodiment of the present invention, FIG. 8 is a flowchart of read-related processing for the host, FIG. 9 is a flowchart of startup processing for the drive, and FIG. 10 is a write/write processing flowchart for the drive. A read processing flowchart, FIG. 11 is an explanatory diagram of the overall operation, FIG. 12 is an explanatory diagram of instruction prefetch control, and FIG. 13 is an explanatory diagram of the prior art. In the figure, 1...Magnetic tape drive unit, 2...Drive control unit, 3...Command/data prefetch control unit, CBUF...Instruction buffer, 34...Data buffer.

Claims (1)

[Scope of Claims] 1. A magnetic tape drive unit having a magnetic head and a magnetic tape drive mechanism; a buffer unit capable of preemptively storing a plurality of commands given from a higher level; In a magnetic tape device comprising a control unit that controls a magnetic tape drive unit and executes the instruction, the control unit detects the vicinity of the end area of the magnetic tape run by the magnetic tape drive unit, and then performs a write operation. A magnetic tape device comprising: counting the running distance of the magnetic tape from the time when the vicinity of the end area is detected during the execution of a system command, and deeming that the tape end area has been detected when the counted value reaches a certain value. instruction preemption control method. 2. A magnetic tape drive unit having a magnetic head and a magnetic tape drive mechanism; an instruction prefetch control unit having a buffer unit that can preemptively store a plurality of commands given from a higher level; The magnetic tape device includes a drive control unit that controls a magnetic tape drive unit and executes the instructions, and the instruction prefetch control unit manages the number of instructions that can be stored in the buffer unit and executes write-related instructions. During execution, the running distance of the magnetic tape is counted based on a detection signal indicating the vicinity of the end area of the magnetic tape from the drive control unit, and when the counted value reaches a certain value, it is considered that the tape end area has been detected. An instruction prefetch control device for a magnetic tape device, characterized in that it is configured as follows.