JPH0453091A - Random access memory - Google Patents

Abstract

PURPOSE:To accelerate access without enlarging circuit scale by selecting a row having a bit number which is the integral multiple of the number of bits in a write data. CONSTITUTION:A row selection part 2 selects the row of a memory cell part 1 by decoding the high-order bit of an address signal. At that time, the row composed of the number, which is the integral multiple of the number of bits in the write data, of bits is selected. An input buffer part 6 outputs the row so that the row can be distributed to be the integral multiple of the number of bits in the write data. On the other hand, a column selection part 5 selects by the row selection part 2. Namely, the desired column is selected from the row composed of plural columns. A column input/output circuit 4 writes the plural columns of write data, which are applied from the input buffer part 6 through an input data control part 3, while adding those data to the column of the memory cell part 1 selected by the column selection part 5. Then, the data read out of the column of the memory cell part 1 selected by the column selection part 5 is added to an output buffer part 7.

Description

[Detailed Description of the Invention] [Summary] Regarding a random access memory that enables high-speed access, the present invention aims to "speed up access without increasing the circuit scale, and is composed of a plurality of memory cells. a cell section, a row selection section that selects a row of the memory cell section, an input data control section, an insertion output circuit that inputs and outputs data to and from the memory cell section, and a column selection section of the memory cell section. comprising a column selection section, an input buffer section, and an output buffer section,
The row selection section is configured to select a row of the memory cell section having a number of bits that is an integral multiple of the number of bits of the write data, using the upper bit of the address signal, and the input buffer section selects a row of the memory cell section that has a number of bits that is an integral multiple of the number of bits of the write data. The column selection section has a configuration in which the number of bits is distributed and output as an integral multiple of the number of bits and added to the input data control section;
The apparatus is configured to select columns corresponding to the number of bits of the write data in the row selected by the row selection section.

(Industrial Application Field) The present invention relates to a random access memory that enables high-speed access.

Random access memories are capable of writing data to and reading data from arbitrary addresses, and various configurations are known. Such random access memories are also applied to elastic memories and the like in communication systems, and as communication speeds have improved in recent years, there has been a demand for faster memories and lower power consumption.

[Conventional technology]

A CMOS static random access memory has been adopted as a conventional random access memory that has a relatively low power consumption structure and operates at a relatively high speed. Random access memories of this kind are manufactured with various bit configurations, for example, write data and read data are configured with 4 bits per word,
When 4 bits of storage capacity is required, 4 (bit)
A random access memory with x1024 (word) configuration will be used. In that case, a 10-bit address signal is used, and data is written or read in units of 4 bits.

In addition, random access memory with a storage capacity of IK bits is 4
It is also known to have a total storage capacity of 4 bits.

[Problem to be solved by the invention]

The address signal is decoded to write or read data to a predetermined address in the memory, and the decoding processing time of the address decoder increases in accordance with the number of bits of the address signal. That is, the decoding processing time of the address decoder in a small capacity memory is shorter than that in a large capacity memory. As mentioned above, in order to access a memory with a storage capacity of 4 bits, a 10-bit address signal is required, but in order to access a memory with a storage capacity of IK bits, a 6-bit address signal is required. Therefore, the access operation can be speeded up.

However, in order to realize a desired storage capacity by using a plurality of small-capacity memories, there is a disadvantage that the circuit scale becomes larger than when using one memory having the desired storage capacity.

An object of the present invention is to speed up access without increasing the circuit scale.

[Means to solve the problem]

The random access memory of the present invention selects a row whose number of bits is an integral multiple of the number of bits of write data.
This is intended to increase the speed of operation by reducing the number of bits of the address signal for row selection, and will be explained with reference to FIG.

A memory cell section 1 composed of a plurality of memory cells, a row selection section 2 that selects rows of the memory cell section 1, an input data control section 3, and an insertion section that inputs and outputs data to and from the memory cell section 1. An output circuit 4, a column selection section 5 for selecting columns of the memory cell section 1, an input buffer section 6, and an output buffer 1
The row selection section 2 is configured to select a row of the memory cell section 1 having a number of bits that is an integral multiple of the number of bits of write data, based on the upper bit of the address signal.

Furthermore, the input buffer section 6 is configured to distribute and output the write data so that the number of bits is an integral multiple of the number of bits, and then adds the divided data to the input data control section 3. Further, the column selection section 5 is configured to select the column -t [the number of bits of the write data in the row selected by the row selection section 2] using the lower bits excluding the upper bits of the address signal applied to the row selection section 2.

In addition, the memory cell section 1 is a dual port memory cell section,
The configuration includes a row selection section, an input data control section, one column input/output circuit, one column selection section, a one-person buffer section, and an output buffer section, corresponding to the ports.

[Effect]

The row selection section 2 decodes the upper bits of the address signal to select a row of the memory cell section 1. At this time, the row selection section 2 selects a row whose number of bits is an integral multiple of the number of bits of the write data. Configure. Therefore, compared to a configuration in which as many rows as the number of write data bits are selected, the number of bits of the address signal to be decoded can be reduced, and the decoding operation time in the row selection section 2 can be shortened. can.

The input buffer section 6 distributes and outputs the number of bits of the write data so as to be an integral multiple of the number of bits. For example, in the case of four times the number of bits of the write data, each bit of the write data is distributed to four.

Further, the column selection section 5 selects a column corresponding to the number of bits of write data in the row selected by the row selection section 2. That is, a desired column in a row consisting of a plurality of columns is selected.

In addition, the column input/output six circuits 4 receive multiple columns of write data added from the input buffer section 6 via the input data control section 3.
Writing is performed in addition to the 10 columns of memory cell sections selected by the column selection section 5. Further, the data read from the 10 columns of memory cell sections selected by the column selection section 5 is added to the output sofa section 7.

Further, the memory cell section 1 is a dual port memory cell section, and data can be written into one port and read out from the other port asynchronously. In this case as well, the bit configuration of the row selected by the row selection section corresponding to the port is an integral multiple of the number of bits of the write data, and the number of bits of the address signal to be decoded in the row selection section is reduced. Decoding processing time can be shortened.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which 10 is a memory section, 11 is a memory cell section, 12 is a row selection section, and 13 is a block diagram of an embodiment of the present invention.
14 is an input data control section, 14 is a column input/output six circuit, 15 is a column selection section, 16 is an input buffer section, 17 is an output buffer section,
21 is an address register, 22 is a decoder, 23 is a delay circuit (DL), 24 is a selector, 25 is a latch circuit, 2
6 to 29 are AND circuits.

A case is shown in which the memory cell section 11 has a 16 (bit) x 256 (word) configuration and write data has a 4-bit configuration. Therefore, a 10-bit address signal is applied to the address register 21, the upper 8 bits of which are applied to the row selection section 12, and the 256 bits of the memory cell section 11 are
A row selection is made. In addition, the lower two bits of the address signal excluding the above-mentioned eight bits are applied to the column selection section 15 and also applied to the decoder 22, the decoded output signals are applied to AND circuits 26 to 29, and the write enable signal WE is applied to the column selector 15. Corresponding write enable signal WEO~WE
3 is added to the memory cell section 11. Further, the decoded output signal is delayed by the delay circuit 23 according to the latch timing by the latch circuit 25, and is applied to the selector 24.

The input cover sofa section 16 stores 4 bits of write data in 4 bits.
The number of bits is doubled, that is, it is distributed into four columns and input to the input data control unit 13. The four columns of write data added from the human data control unit 13 to the six column input/output circuits 14 are as follows:
Write data is added to the memory cell section 11 according to the column selection by the column selection section 15, and written into the column selected by the write enable signals WEO to WE3.

FIG. 3 is an explanatory diagram of the distribution of write data, in which the write data is distributed into four columns and the write enable signal W corresponding to the column is
This shows the function of writing write data into the memory cell section 11 using EO to WE3, and the write data of 4 bits is written to the gate circuits 30-1 to 30-4 corresponding to each column.
...33-1 to 33-4, one of the AND circuits 26 to 29 is opened by the decoded output signal obtained by decoding the lower two bits of the address signal by the decoder 22, and the write enable signal WE is output in the column. They become corresponding write enable signals WEO to WE3 and are written into the memory cell section 11 as column-corresponding data DO to D3.

For example, in the memory cell section 11 shown in FIG. 4, the address signal is "o o o o o o i 1. Oi
”, by decoding the upper 8 bits “ooooooil” in the row selection unit 12, the third row indicated by arrow a among the 0th to 255th rows is selected, and the lower 2 bits 01” are decoded. By decoding by 22,
A write enable signal WEI is output from the AND circuit 27. At that time, since the column selection section 15 selects the first column among the 0th to 3rd columns, the write enable signal WE
At timing I, data D1 is written into the shaded position of the memory cell section 11.

Therefore, the row selection unit 12 does not select 1024 rows, but selects 1/4 of 256 rows, thereby reducing the decoding time. Furthermore, since the column selection section 15 selects four columns, its decoding processing time is shorter than that of the row selection section 12. For example, in CMO3 static random access memory, 4 (bits) x 1024 (words)
If the access time is 25 ns, if the access time is 25 ns, if the 16 (bit) x 256 (word) configuration is used as in the above embodiment, the row selection time will be shortened, and 1
An access time of 8 ns was obtained.

Further, when the address signal is as described above, data of 3016 bits DO to D is read from the third row of the memory cell section 11. When this one row of data is latched from the insertion output circuit 14 to the latch circuit 25 via the output buffer section 17, the selector 24 is controlled by the decode output signal of the decoder 22, and the data D1 of the first column is will be output as read data.

Further, when data is not read from the memory cell section 11, the column selection section 15 may select a column and read only the data D1 of the first column.

In that case, the selector 24 can be omitted.

FIG. 5 is an explanatory diagram of the operation of the embodiment of the present invention, in which (a) is an address signal, and (c) to (e) are lower two of the address signal.
The decoded output signal obtained by decoding the bits by the decoder 22 or the column selection signal from the column selection section 15; , (g) indicate data read from the memory cell section 11, and (1) indicate read data selected by the column selection section 15 or selector 24.

The address signal sequentially changes from 0 to 255, and the memory cell section 1
When selecting the 0th to 255th rows of 1, the 4-bit write data is distributed to 4 columns, resulting in a total of 16 bits of data, and is sequentially selected by the column selection unit 15 from the O column to the 3rd column. Ru.

Therefore, when the address signal is "0", the 0th row.

Data D0 is written to the 0th column by the write enable signal WEO shown in ((to). Also, the address signal "1"
At this time, data D is written to the Oth row and first column by the write enable signal WEI shown in (5), and when the address signal is "2", data D is written to the Oth row and second column. but(
When the address signal is "3", data D is written in the 0th row and 3rd column by the write enable signal WE3 shown in (j).

Similarly, when the address signal is "4", the first row.

Data D4 is written to the 0th column by the write enable signal WEO shown in (g), and when the address signal is "5", data D is written to the 1st row and 1st column as shown in (5). It is written by the write enable signal WEI, and when the address signal [6] is applied, it is written to the first row and third column by the write enable signal WE3 shown in data D1 (i).

In the case of a read operation, when the address signal is 10'' to 3, data D0 to D is read from the 0th row of the memory cell section 11.
is being published one after another. By selecting these 16-bit data D0 to D by the selector 24 or by having the column selection section 15 perform column selection, as shown in (1,),
Data D0 to D can be output corresponding to address signals "0" to "3". Also, the address signal is "4" to "7"
”, data D4~ from the first row of the memory cell section 11
D is output one after another, and by selecting columns by the selector 24 or the column selection section 15, data D4 to D can be output in correspondence to address signals "4" to "7".

FIG. 6 is a block diagram of main parts of a dual-port random access memory according to another embodiment of the present invention, in which 41 is a memory cell section, 42.52 is a row selection section, 43.53 is an input data control section, and 44 .54 is a column input/output path, 45.55 is a column selection section, 46.56 is an input buffer section, 47. ．． 57
This is the Kaba Sofa Club.

As described above, the upper bits of the address signal are input manually to the row selection units 42 and 52, and a row having a number of bits that is an integral multiple of the number of bits of the write data is selected. Further, the column selection section 45.55 receives the lower bits excluding the upper bit added to the row selection section 42.52 of the address signal, and selects a column consisting of the number of bits of the write data.

In addition, the input buffer sections 46.56 distribute the write data into integral multiples of the number of bits thereof, and input the data to the input data control section 43.56.
53. For example, input buffer section 4
6 is written into the memory cell section 41 according to the address signals applied to the row selection section 42 and the column selection section 45, and the write data input to the row selection section 52 and the column selection section 55 are written to the memory cell section 41 according to the address signals applied to the row selection section 52 and the column selection section 55. Accordingly, data can be read from the memory cell section 41 and output from the output buffer section 57 as read data.

FIG. 7 is a block diagram of another embodiment of the present invention, 60
61 is a write address counter, 62 is a read address counter, 63 and 64 are decoders, 65 is a delay circuit (DL),
66 to 69 are AND circuits, 70 is a latch circuit, and 71 is a selector.

As in the previous embodiment, the memory section 60 has a 16 (bit) x 256 (word) memory cell section, and the write address counter 61 counts the write clock signal WCK and outputs a 10-bit address signal. The read address counter 62 counts the read clock signal RCK and outputs an address signal of 10 bits.

The upper 8 bits of the 10-bit write address signal and read address signal are sent to the row selection section 42.5 of the memory section 60.
2 (see FIG. 6), and row selection of the memory cell section 41 is performed. The lower two bits of the write address signal are decoded by the decoder 63 and sent to AND circuits 66-6.
Added to 9. The lower two bits of the read address signal are decoded by the decoder 64 and applied to the selector 71 via the delay circuit 65.

As described above, the write data will be distributed to four times the number of bits, and the write enable signal WE will be distributed to the AND circuits 66 to 66 by the decoded output signal of the decoder 63.
9 becomes a column-corresponding write enable signal WEO-WE3, and write data is written in the row specified by the upper 8 bits of the write address signal and in the column specified by the lower 2 bits of the write address signal.

In addition, 16 bits of data are read from the row specified by the upper 8 bits of the read address signal, and the latch circuit 70
The selector 71 outputs the data of the column specified by the lower two bits of the read address signal.

Therefore, while writing data using a write address signal synchronized with write clock signal WCK, data can be read using a read address signal synchronized with read clock signal RCK, which is asynchronous with write clock signal WCK. Even in that case, the number of bits to be decoded in the row selection units 42, 52 can be reduced, so the decoding processing time can be shortened.

The present invention is not limited to the above-mentioned embodiments; the number of bits of the write data can be 8, 16°32, etc., and the case where the number of bits is 4 is shown as an integer multiple. However, the multiple can be increased, such as 5 times, 8 times, etc., depending on the storage capacity.

C. Effects of the Invention] As explained above, in the present invention, the row selection unit 2 selects a row of memory cell parts having a number of bits that is an integral multiple of the number of bits of write data using the upper bits of the address signal. The input buffer section 6 is configured to distribute the write data so that the number of bits is an integral multiple of the above, and the column selection section 5 selects a row by using the lower bits excluding the upper bits added to the row selection section 2 of the address signal. The structure is such that a column corresponding to the number of bits of write data in the row selected by the selection unit 2 is selected, and when the number of bits of write data is n, a memory of n (bits) x m (words) is configured. In the case, l×n
A memory of (bint)Xm/l (words) can be used. In that case, the row selection unit 2 selects m,
/ I! , rows, the decoding processing time can be reduced compared to the case where m rows are selected. That is, there is an advantage that high-speed access is possible without increasing the circuit scale.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a diagram explaining the distribution of write data.
FIG. 4 is an explanatory diagram of the memory cell section, FIG. 5 is an explanatory diagram of the operation of an embodiment of the present invention, FIG. 6 is a block diagram of main parts of a dual-port random access memory, and FIG. 7 is an explanatory diagram of another embodiment of the present invention. FIG. 2 is a block diagram of an embodiment. 1 is a memory cell section, 2 is a row selection section, 3 is an input data control section, 4 is an insertion output circuit, 5 is a column selection section, 6 is an input buffer section, and 7 is an output buffer 7 section.

Claims (2)

[Claims] (1) a memory cell section (1) composed of a plurality of memory cells, a row selection section (2) that selects a row of the memory cell section (1), an input data control section (3), and the a column input/output circuit (4) that inputs and outputs data to and from the memory cell section (1), a column selection section (5) that selects columns of the memory cell section (1), and an input buffer section (6); an output buffer section (7), and the row selection section (2) selects a row of the memory cell section (1) having a number of bits that is an integral multiple of the number of bits of the write data, according to the upper bit of the address signal. The input buffer unit (6) has a configuration to distribute and output the write data so as to have a number of bits that is an integral multiple of the number of bits and add it to the input data control unit (3), The selection section (5) uses the lower bits excluding the upper bits to be added to the row selection section (2) of the address signal.
A random access memory characterized in that the random access memory is configured to select columns corresponding to the number of bits of the write data in the row selected by the row selection unit (2). (2) The memory cell section (1) is a dual-port memory cell section, and includes a row selection section, an input data control section, a column input/output circuit, a column selection section, an input buffer section, and an output buffer section corresponding to the ports. 2. The random access memory according to claim 1.