JPH0453237A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the deformation of lead, etc., while forming a fine pattern with high precision by a method wherein, after bonding a semiconductor chip to a metallic base to be resin-molded, the metallic base is etched away to form a wiring pattern. CONSTITUTION:A wiring pattern is formed on a metallic base 10 by plating (Au plated layer 14) a non-etching metal in the state of the metallic base 10 on whose surface and rear surface resist patterns 12 are formed. Successively, the resist patterns 12 are peeled off, a semiconductor chip 16 is bonded to a die-bonding part 18 and then the semiconductor chip 16 is wire-bonded to wire- bonding parts 20. Next, one side surface only of the metallic base 10 on which the semiconductor chip 16 is mounted is resin-sealed 22. After finishing the resin-molding process, the metallic base 10 exposed from the molded resin 22 is etched away. At this time, specific wiring pattern can be formed using the exposed Au plated layer 14 in the outer surface of the metallic base 10 as an etching pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor chip and circuit components are physically sealed with resin.

(Prior art) The applicant previously manufactured semiconductor chips and circuit components together once a month.
12) proposed a method for manufacturing a semiconductor device to be mounted (Japanese Patent Application No. 12-23-134).

This method of manufacturing a semiconductor device involves forming a wiring pattern on a metal base using a non-etchable metal such as gold, bonding a semiconductor chip to the metal base, and wire bonding the wiring pattern and the semiconductor chip. A method of sealing one side of a metal base mounted with a resin side with a resin, and etching away the metal base portion exposed from the resin sealing part to leave the wiring pattern,
After wire bonding, one side of the metal base on which the semiconductor chip is mounted is sealed with resin, and the metal base is etched in a predetermined pattern from the exposed side. This is a method of forming wiring patterns on a metal base.

(Problem to be solved by the invention) I. The method of using the metal base as a mounting base for a semiconductor chip has the advantage that a normal metal etching method can be used because the metal base is etched to produce a product.

However, the conventional method described in Section 12 has the following problems.

■ In the case of a method in which the metal base is finally completely removed by etching, leaving only a wiring pattern made of non-etchable metal such as gold, the remaining wiring pattern must have a certain degree of strength, so The film thickness is required to be at least 100% thick. As the non-etchable metal, an expensive metal such as gold is used, which increases the cost.

(2) In the case of a method in which a wiring pattern is created by etching a metal base and using the metal base itself as a conductor, it is difficult to position the pattern because the wire bonding portion and the wiring pattern must be formed separately.

Therefore, the present invention was devised to solve the above two problems, and its purpose is to easily integrate a semiconductor chip and circuit components, and to reduce the number of manufacturing steps. It is possible to reduce the manufacturing cost to 1, and to form wiring patterns with high precision.
It is an object of the present invention to provide a method for manufacturing a conductor device.

(Means for Solving the Problems) The present invention has the following configuration to achieve the object "1.1".

That is, a plating layer whose surface layer is made of a non-etchable metal is provided according to the wiring pattern to be formed on both sides of a metal base, and necessary circuit components such as semiconductor chips are mounted on the metal base, and the circuit on the metal base is The present invention is characterized in that one side on which components are mounted is molded with resin, and a wiring pattern is formed on the sealing resin by etching the metal base using the plating layer as a protective film during etching.

Further, one or more conductor layers are further provided on the -1- layer of the wiring pattern via an electrical insulating layer.

Further, a plating layer whose surface layer is made of a non-etchable metal is provided according to the wiring pattern to be formed on both surfaces of the metal base, and required circuit components such as semiconductor chips are mounted on the metal base. One side on which the circuit component is mounted is molded with a resin with an insertion hole through which an external connection pin is inserted, and a conductive thin film is formed on the opposite side of the sealing resin to the side to which the metal base is bonded, The metal base is etched using the plating layer as a protective film during etching, the conductor thin film is etched according to a predetermined pattern, and a pin is inserted into the insertion hole to connect the metal base and the conductor thin film. .

Further, as the external connection terminal, the end of the wiring pattern may be extended to the side of the sealing resin, a pin may be erected by connecting to the wiring pattern, or a bump may be formed by connecting to the wiring pattern. is useful.

Further, as a method of connecting the semiconductor chip and the metal base, a method of connecting by wire bonding ink or a method of connecting by a flip chip method can be used.

Furthermore, it is useful to use electrolytic copper foil as the metal base, and to use the rough side of the electrolytic copper foil as the mounting surface for the circuit component.

(Embodiments) Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

The manufacturing method according to the present invention can be applied to manufacturing various types of semiconductor devices. Manufacturing methods for several types will be explained below.

Figure 1 does not show an example of application to a flat package type semiconductor device.

The manufacturing method of the present invention is characterized in that a required wiring pattern is formed in advance on a metal base using non-etchable gold, and then a semiconductor chip is mounted and resin is coated.

FIG. 1(a) shows a metal base 10 used in manufacturing.

The material of the metal base 10 is not particularly limited as long as it can be easily dissolved and removed by etching. In the embodiment, electrolytic copper foil is used as the metal base 10. The electrolytic copper foil is formed on a rough surface having an uneven shape on which copper grows, and this rough surface is used as the side to be bonded to the sealing resin.

This is to improve adhesion with the sealing resin.

First, a predetermined wiring pattern is formed on the metal base 10 using a non-etchable metal.

Here, the wiring pattern refers to connecting a semiconductor chip to a metal base 1.
0, a wire bonding part for connecting a semiconductor chip to a metal base, a conductor layer part such as a circuit pattern part for connecting a semiconductor device to a lead frame or a mounting board. do.

The non-etchable metal may be any metal that is not attacked by the etching solution used to dissolve and remove the metal base 10. In the embodiment, gold is used as the non-etchable metal. Note that the plating layer] 4 may be a plurality of laminated layers, and in this case, the surface layer of the plating layer may be made of a non-etchable metal.

FIG. 1<b> shows a state in which a resist I pattern 12 is formed on a metal base 10 according to a wiring pattern. Since the wiring pattern is formed in a predetermined pattern on the metal base i-0 as described in "2," the resist pattern]-
2 is the metal base 1 except for the part forming the wiring pattern.
Coat the surface of 0. A wiring pattern can be formed on the metal base JO by plating the non-etchable metal with the resist pattern 12 formed on the front and back surfaces of the metal base 10.

In the example, since the metal base 10 is used, the resist 1
- After forming the pattern]-2, the metal base 10 is etched, and the etching is performed after making the 1-square side of the metal base]-◯ a smooth surface. Gold is used as the non-etchable metal.

FIG. 1(c) shows a state in which a gold plating layer 14 is formed on the metal base ]-0f as described above.

Subsequently, the semiconductor chip 16 is mounted on the metal base 1-0. Therefore, the resist pattern 1-2 is peeled off, the semiconductor chip 16 is bonded to the die attachment part 1-8, and the wire bonding part 20 and the semiconductor chip 1-6 are wire-bonded. The wire bonding portion 20 has good bonding properties because the rough surface of the metal base 10 is smoothed and gold plated.

Next, the semiconductor chip 16 is sealed with resin. Figure 1(d)
is the state after resin sealing. In the case of resin sealing, only one side of the metal base 10 on which the semiconductor chip 1G is mounted is sealed as shown in the figure. 22 is a sealing resin.

After resin sealing, the metal base 10 exposed from the resin 22 is etched at ↓ζf1. At this time, since the gold plating layer 14 exposed on the outer surface of the metal base JO acts as an etching pattern, the gold plating layer 14, that is, the metal base 10 is etched according to the wiring pattern, thereby forming a semiconductor having a predetermined wiring pattern. A device is obtained.

FIG. 1(0) shows a semiconductor device which has been reduced by 1% in this manner.

In the semiconductor device of this embodiment, the connection lead 24 is extended outside the sealing resin 22. For example, the connection lead 24 is connected to the inner lead 26 of the lead frame as shown in the figure. It can be used as

FIG. 1(f) shows a type formed to be mounted on a board, in which leads 25 formed in a gull wing shape are connected and a resist coat 1 is used to protect the wiring pattern.
This is an example in which 27 to 27 are provided.

FIG. 2 shows an example in which bumps are formed as external connection terminals.

A pattern 12 is provided on the resist 1 on the metal base 10, and after etching, gold plating is applied to form a gold plating layer 14 in a predetermined pattern. As shown in FIG. 2(a), the semiconductor chip 16
are connected by wire bonding and sealed with resin (
Figure 2(b)).

Next, the metal base 1-0 is etched to form a predetermined wiring pattern.

When forming bumps, the exposed surface of the wiring back-up is coated with a protective coating, the portion of the protective coating 28 where the bumps are to be formed is etched to form a hole leading to the wiring pattern, and the bumps are formed by solder plating, bonding, or flow. Alternatively, there is a method in which the bumps 30 are formed by forming a hole at the bump formation location using a screen printing method and applying a protective coating 28.

Although FIG. 3 shows a type in which bumps are formed as external connection terminals, as in FIG. This has the advantage that the planar space of the semiconductor device can be effectively used as a bump forming portion, and the overall size of the semiconductor device can be reduced.

In the semiconductor devices of the above embodiments, the semiconductor chip and the metal base are connected by wire bonding, but the same applies to the case where the connection is made by the flip-chip method.

FIG. 4 shows an embodiment in which semiconductor chips I6 are connected by the flip-chip method. Gold plating layer 1 on metal base 10
4 (FIG. 4(a)), after connecting the semiconductor chip i6, sealing with resin, and etching the metal base (FIG. 4(b)). FIG. 4 shows the state in which it is connected to the lead frame 11 with a lead 24.

FIG. 5 shows an example of a semiconductor device in which a semiconductor chip 16 is mounted by the flip-chip method and bumps 30 are formed.

There are various methods for mounting semiconductor devices, such as using connection leads as shown on the north side, forming connection bumps, and providing exposed terminals for external connections. Appropriate types can be manufactured according to these mounting methods.

The semiconductor device shown in each of the embodiments in Section 2 has the following characteristics due to its manufacturing method.

That is, by resin-sealing one side of the metal base 10, even including the protective coating 28, the semiconductor device can be formed thinner than a conventional resin-sealed semiconductor device.

The gold plating layer 14 is used as an etching pattern, and the main part of the conductor layer is the metal base 10.
There is no need to make the film W very thick, which is advantageous from the viewpoint of cost 1.

When providing the gold plating layer 14 on the metal base 10, patterns can be formed on the front and back sides of the metal base 10 at the same time, which eliminates pattern misalignment and enables accurate pattern formation compared to the case where patterns are formed on the front and back sides in separate processes. I can do it.

In the case of a semiconductor device in which the connection leads 24 extend from the sealing resin 22, the connection leads 24 are bent into a predetermined shape before etching the metal base 10, and then the metal base 10 is etched. It's okay.

According to this method, deformation of the connection lead 24 can be prevented.

<1) G package type> FIG. 6 shows a method of manufacturing the PGΔ package type. P
In the G△ package type, a gold plating layer 14 is renumbered on the metal base 10, and after mounting the semiconductor chip 6, the metal base 10 is etched and wired as shown in Fig. 6(a)). A pattern is formed and pins 32 are soldered (FIG. 6(b)).

A pattern for forming holes for connecting pins 32 by etching is formed in advance on the gold plating layer 14.

FIG. 7 shows another embodiment of the [)GΔ package type. In this embodiment, the pin 32 is transparently provided on the side of the sealing resin 22. The semiconductor device of this embodiment has a method of molding the pins 32 integrally with the sealing resin 22 by insert molding when the semiconductor chip 16 is sealed with resin, and a method of inserting the pins 32 during resin sealing. A method such as forming an insertion hole and inserting and connecting the pin 32 in a subsequent process can be used.

After connecting the pins 32, a predetermined wiring pattern is formed by etching the metal base 10.

Multi-layer package type> - JZ Although the semiconductor devices of each example have one layer of wiring pattern (conductor layer), it can also be used to manufacture a multi-layer package type semiconductor device with multiple conductor layers. can.

FIG. 8 shows an example of manufacturing a multilayer package type semiconductor device.

FIG. 8(a) shows a state in which the semiconductor chip 1-6 is wire-bonded, resin-sealed, and the metal base 10 is etched to form a wiring pattern. The manufacturing method up to this point is the same as the above example. As a result, the conductor layer of the ]-th layer is formed.

Next, an insulating layer 34 is formed on the first conductive layer 2 using an electrically insulating material, and the insulating layer 34 is etched to provide a hole for forming a via, or vias are formed using a screen printing method. A hole is provided at the location, and the hole is filled with a conductive material to form a via 36 (FIG. 8(b)).

Next, a conductor layer 38 is formed on the insulating layer 34, and a predetermined pattern is formed by etching or the like.

As a method for forming the conductor layer 38, known methods for forming a conductor layer, such as sputtering, vapor deposition, and plating, can be used.

As shown in FIG. 8(a), it is possible to form a semiconductor device having multiple conductor layers by using the method of the present invention, in which the semiconductor chip 16 is exposed to the outside on its back side. This is due to the fact that any wiring pattern can be formed. Therefore, according to the method described in -1-, it becomes possible to easily provide more conductor layers by interposing an insulating layer in between.

Note that when providing a terminal for external connection, the above-described method such as bump formation may be used.

FIG. 9 is an example of a semiconductor device having two conductor layers.

In manufacturing this semiconductor device, first, when forming the gold-plated layer 4 as shown in FIG.
In addition, an insertion hole 40 for inserting the pin 32 when sealing the semiconductor chip 16 with resin is provided and molded.

Next, a conductive thin film 42 is formed on the lower surface of the sealing resin 22,
After forming a predetermined resist pattern on the conductive thin film 42, the conductive thin film 42 and the metal base 10 are etched to form a conductive layer having a predetermined wiring pattern on the front and back surfaces of the sealing resin 22.

Next, the pin 32 is inserted into the insertion hole 40 to establish an electrical connection between the conductor layers on the front and back surfaces of the sealing resin 22. As a result, a semiconductor device having two conductor layers is obtained, as shown in FIG. 9([)].

FIG. 10 shows another embodiment of a semiconductor device having conductor layers on the front and back surfaces of the sealing resin 22, respectively. In the semiconductor device of this embodiment, a gold plating layer 14 is provided in a predetermined pattern on the metal base 10 on which the semiconductor chip 1-6 is mounted, and the semiconductor chip 1-6 is mounted and wire bonded.
A metal base 10 provided with a gold plating layer of a predetermined pattern]4
are formed separately, the two metal bases are inserted into a mold, and the two metal bases are integrally sealed with resin (Fig. i-0 (a)).
) After that, the front and back conductor layers can be manufactured by etching the gold plating layer 14 as an etching pattern.

Note that even in the case of a type of semiconductor device in which two of these conductor layers are provided, the conductor layers on one side or both sides may be formed in multiple layers in the same manner as the example shown in FIG.
It is J-Noh.

In the above description, an example has been shown in which the semiconductor chip 16 is connected by wire bonding, but the same is true when the semiconductor chip 16 is mounted by the flip-chip method as shown in FIG. 4 described above.

In addition, in each of the embodiments described in -h, an example was shown in which the semiconductor chip was fixed with a fluoride resin, but since the wiring pattern is formed by etching the metal base, any wiring pattern can be formed, and therefore the semiconductor chip It is extremely easy to mount other necessary circuit components together with the 1. By mounting other circuit components, it is possible to manufacture a variety of electronic components for a variety of uses.

Hereinafter, the present invention has been variously explained using preferred embodiments; however, the present invention is not limited to these embodiments, and may be modified in many ways without departing from the spirit of the invention. ) of course.

(Effects of the Invention) According to the method for manufacturing a semiconductor device according to the present invention, the following remarkable effects are achieved.

■ The semiconductor chip is bonded to the metal base, resin molded, and then the metal base is etched to form the wiring pattern, which prevents deformation of the leads, etc.

■ Because the metal base is held in place by the stab-retaining resin,
A thin metal base can be used, so that fine patterns can be formed with high precision.

■ Etching is performed after resin sealing, eliminating the need for tie bars.

■ Patterns are formed on the front and back sides of the metal base at the same time, so pattern misalignment between the front and back sides of the metal base can be eliminated.

(2) Since a non-etchable metal is used as an etching pattern, it is not necessary to form it so thickly, and costs can be reduced when using expensive metals such as gold.

(2) The entire planar space of the semiconductor device can be effectively used as a space for external connections such as bumps.

(2) It can be applied to the manufacture of various types of semiconductor devices, and can also be applied to multilayer semiconductor devices having multiple conductor layers.

■ In addition to semiconductor chips, other circuit components can be mounted at the same time, making it possible to manufacture a variety of electronic devices.

(2) When electrolytic copper foil is used as the metal base, the adhesion between the sealing resin and the wiring pattern is improved, and peeling can be prevented and the reliability of the device can be improved.

[Brief explanation of the drawing]

1 to 5 are flat package type semiconductor devices manufactured by the manufacturing method according to the present invention, FIGS. 6 and 7 are PGΔ package type semiconductor devices, and FIGS. 8, 9, and 10 are multilayer semiconductor devices. FIG. 2 is an explanatory diagram showing an example of manufacturing a package type semiconductor device. 10... Metal base, 12... Resist 1 to pattern, 14... Gold plating layer, 16... Semiconductor chip, 20... Wire bonding part,
22... Sealing resin, 28... Protective coating, 29... Adhesive, 30... Bump,
331-... Insulating film; 34... Insulating layer, 36... Via, 38... Conductor layer, /I
-0...Through hole, 42...Conductor thin film.

Claims (1)

[Claims] 1. A plating layer whose surface layer is made of a non-etchable metal is provided according to a wiring pattern to be formed on both sides of a metal base, and required circuit components such as semiconductor chips are mounted on the metal base. , one side of the metal base on which the circuit component is mounted is molded with resin, and the metal base is etched using the plating layer as a protective film during etching to form a wiring pattern on the sealing resin. A method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of providing one or more conductor layers above the wiring pattern with an electrical insulating layer interposed therebetween. 3. A plating layer whose surface layer is made of a non-etchable metal is provided according to the wiring pattern to be formed on both sides of the metal base, and required circuit components such as semiconductor chips are mounted on the metal base, and the circuit on the metal base is One side on which the component is mounted is molded with a resin with an insertion hole through which an external connection pin is inserted, and a conductive thin film is formed on the side of the sealing resin opposite to the side to which the metal base is bonded. A semiconductor characterized in that the metal base is etched using a plating layer as a protective film during etching, the conductor thin film is etched according to a predetermined pattern, and a pin is inserted into the insertion hole to connect the metal base and the conductor thin film. Method of manufacturing the device. 4. The method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that an end portion of the wiring pattern is extended to the side of the sealing resin as an external connection terminal. 5. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein a pin is provided upright in connection with a wiring pattern as an external connection terminal. 6. The method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that a bump is formed by connecting to a wiring pattern as an external connection terminal. 7. Claims 1, 2, and 3, characterized in that the semiconductor chip and the metal base are connected by wire bonding.
7. The method for manufacturing a semiconductor device according to 4, 5 or 6. 8. Claims 1, 2, 3, and 4, characterized in that the semiconductor chip and the metal base are connected by a flip-chip method.
, 5 or 6. The method for manufacturing a semiconductor device according to . 9. Claim 1, 2, 3, 4, 5, 6, 7 or 8, characterized in that an electrolytic copper foil is used as the metal base, and the rough side of the electrolytic copper foil is used as the mounting surface for the circuit component. A method of manufacturing the semiconductor device described above.