JPH0453263A - Semiconductor memory circuit device - Google Patents

Abstract

PURPOSE:To enable the content of a memory loop of a memory cell to be easily inverted and a write operation to be executed more easily a compared with a conventional one by a method wherein a resistive element or a resistive element connected to a transistor in parallel is inserted between the ground terminal of an inverter circuit which forms the memory loop of a memory cell and the ground terminal of a chip. CONSTITUTION:The ON-state resistances of an NMOS transistor and a PMOS transistor are represented by R and 2R. Provided that the resistance of a resistive element 4 is represented by Rg and an NMOS transistor 1b and a PMOS transistor 2a are not provided, the potential of a nodal point A is represented by a formula, VDDX(R+ Rg)/(3R+Rg), conforming to voltage division by resistors and becomes higher than VDD/3 in a conventional circuit. The potential of a nodal point B is equal to VDD/2. As the potential of the nodal point A becomes higher than that in a conventional circuit, the NMOS transistor 1b is lessened in ON-state resistance. Therefore, the potential of the nodal point B becomes lower than usual. By this setup, the PMOS transistor 2a is made to decrease in ON-state resistance. As mentioned above, the potential of the nodal point A becomes higher than that of the nodal point B more easily than usual, so that a normal write operation cab be expected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a RAM memory cell composed of basic cells of a gate array.

[Conventional technology]

FIG. 5 is a circuit diagram showing an example of a conventional memory cell connection, and FIG. 6 is a circuit diagram showing a memory cell used in FIG. In FIG. 5, IAl, 8.2A, and 2B are bit lines, 3 is a memory cell, GL is a cell ground as a ground for an inverter circuit, and GND is a chip ground. In addition, in Fig. 6, 1a to 1d are NMO3
) transistors, 2a to 2d8iPMos transistors, WLl and WL2 are word lines, VDD is a power line, A and B are nodes, and transistors la, 2a and 1b and 2b are bare, respectively, forming an inverter circuit. . In FIG. 6, the same or equivalent parts as in FIG. 5 are given the same reference numerals.

The inverter circuits shown in FIG. 6 each have their output connected to the input of the other inverter circuit, forming a storage loop. NMOS transistors lc, ld constitute the first access means to this storage loop,
PMO3 transistors 2c and 2d constitute a second access means for this to loop. In other words, when word line WL1 becomes high level, NMO3I-RANGES 1c and 1d are turned on, and bit line pair IA
, 1B and the storage loop become ready to exchange data. Also, when word line WL2 becomes low level health,
PMO3) The transistors 2C and 2d are turned on, and data can be exchanged between the pins 1 to 2A and 21-3 and the loop 4y.

FIG. 7 is a simplified circuit diagram for writing to the memory loop from the access means of the memory 2. FIG. 7 shows a case where opposite data is written to a storage loop in which the node is at a low level and the node B is at a high level. It is assumed that the bit line pair is ideally given a power supply level and a ground level. Since the voltage to the node B is low level and the node B is high level, transistors Ia and 2b are on and transistors 2a and lb are off. Also, a transistor 2c constituting a second access means
, 2d are on.

FIG. 8 shows the on-state transistor of FIG. 7 as an on-resistance. In a CMOS gate array, when the channel widths of the NMOS transistor and the PMOS transistor are made the same, 1) the on-resistance of the MO3I transistor is approximately twice that of the NMO3h transistor;

In FIG. 8, the on-resistance value of the NMO3I- transistor is shown as R, and the on-resistance value of the PMO3+- transistor is shown as 2R. Assuming that NMO3+- transistor 1b and PMO3+ transistor 2a do not exist, if van is shifted from the voltage of power supply line VDD, the potential at node A becomes VDD/3 due to resistance division, and the potential at node B becomes VIID/2. . In reality, the potential at the node A turns the NMO3I transistor 1b on to some extent (not completely on, so the on-resistance is high), and the potential at the node B turns the PMOS transistor 2a on to some extent.

Therefore, the potential to the node will be higher than V[lD/3,
The potential at node B becomes lower than ■ゎゎゎ/2.

When the potential to the node becomes higher than the potential at node B, the contents of the storage loop are reversed and desired data has been written. However, unless the transistor 2a1b is turned on sufficiently, the contents of the loop 1a will not be inverted, and normal writing cannot be performed.

[Problem to be solved by the invention]

”As a double series, conventional semiconductor devices 1. In the a circuit device, the ground terminal of the inverter circuit that constitutes the ta loop of the memory cell is directly connected to the ground terminal of the semiconductor device (chip), and depending on the characteristics of the I transistor, the contents of the jp loop may be inverted. Sometimes this did not occur and normal writing could not be performed.

The present invention G:1 has been made in view of the above points, and its object is to provide a semiconductor memory circuit device which can perform normal writing regardless of the characteristics of the transistor.

[Failure to solve the problem]

In order to achieve this objective, the present invention provides a resistance element in which a resistance element or a transistor is connected in parallel between the ground terminal of the inverter circuit and the ground terminal of the chip, which constitute the storage loop of the memory cell. It was designed to be inserted.

[Effect]

In the semiconductor device 1QIi1] path device according to the present invention, the contents of the memory loop of the memory cell can be easily inverted, and writing can be performed more easily than in the past.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor memory circuit device according to the present invention. As shown in the figure, a resistance element 4 is inserted between a common ground terminal (cell ground) for a plurality of memory cells and a ground terminal of the semiconductor device. In FIG. 1, the same or equivalent parts as in FIG. 5 are given the same reference numerals.

FIG. 2 is a simplified circuit diagram when writing to the storage loop from the second access means of the memory cell in the circuit of FIG. 1. The figure shows a case where opposite data is written to a storage loop in which node A is at a low level and node B is at a high level. It is assumed that the level of the power supply voltage VDD and the ground level are ideally applied to the bit line pair.

FIG. 3 shows the transistor 1a in the on state of FIG.
2b, 2c, and 2t3 are shown as on-resistances. In CM OS Kate I/I, NM○
When the channel widths of the S transistor and the I)MOS transistor are made the same, the on-resistance of the PMO3) transistor is approximately twice that of the NMO3) transistor. In Figure 3, the on-resistance values of the NMO3) transistor are R, P
The on-resistance value of the MO5I transistor is expressed as 2R. Further, the following description will be made assuming that the resistance value of resistance element-4 is Rg.

Assuming that NMO31, transistor l b and I) Mos1 to transistor 2a do not exist, the potential to the node C1, l
VonX D? by resistor division? +R, g)/(3R4-Rg), which is ■ in the case of the conventional circuit. , /3. Further, the potential of node B becomes VDD/2. In reality, the potential at the node turns NMO3l transistor]b into an on state to some extent (it is not completely on, so the on-resistance is high), and the potential at node I3 turns on transistor l)M
The O3I-transistor 2a is also turned on to some extent. Since the potential to the node is higher than in the conventional circuit (see FIG. 8), the on-resistance of the NMOS+- transistor 1b is reduced. Therefore, the potential at node B is lower than before. This also reduces the on-resistance of the PMO3) transistor 2a. Due to the above-described operation, the potential to the node becomes higher than the potential at node B, compared to the conventional case, and a normal write operation can be expected.

FIG. 4 is a circuit diagram showing another embodiment of the present invention. In the figure, 1e is NMO3+-landisk. N
MO3I-transistor 1C is connected in parallel to resistance element 4. During a write operation, NMO3I-transistor 1e is turned off by signal WE, and the circuit of FIG. 4 becomes equivalent to the circuit of FIG. 1, allowing easy writing. During read operation, NMO3+- transistor 1e
is set to the on state. This reduces the inserted resistance value isometrically. When the resistance value decreases, the output impedance of the inverter circuit forming the loop in the memory cell described in 4.1 decreases, and the read speed increases.

〔Effect of the invention〕

As explained above, in the present invention, a resistive element or a transistor is connected in parallel between the ground terminal of the inverter circuit constituting the memory loop of the memory cell and the 1,000-knob ground F'J:ii 7-. By inserting a resistor element, the contents of the memory cell's loop 41 can be easily reversed, making writing easier than before, and making it easier to write data than before when configuring a memory cell using the basic cell of a gate array. This has the effect of making it possible to wait for a long write operation.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a half-metal two-body memory circuit device according to the present invention, FIG. 2 is a simplified circuit diagram of the circuit of FIG. 1 during a write operation, and FIG. 2 is an equivalent circuit diagram, FIG. 4 is a circuit diagram showing another embodiment of the present invention, FIG. 5 is a circuit diagram showing a conventional semiconductor memory circuit device, and FIG. 6 is a memory used in the semiconductor memory circuit device. The cell circuit diagram, Figure 7, is a simplified circuit diagram of the circuit in Figure 5 during write operation, and Figure 8
The figure is an equivalent circuit diagram of FIG. 1 person, I 2A, 2B... Node line, 3... Memory cell, 4... Resistance element, GL, GND... Ground, 1 a to 1 d -NMOS h transistor,
2a-2d...l) MO3h run sister, VDD...
Electric 'ti, line, AB...node.

Claims (1)

[Claims] In a semiconductor memory circuit device in which a memory cell of a static RAM is constructed using basic cells of a CMOS gate array, a resistive element or a transistor is provided between a ground terminal of an inverter circuit that constitutes a memory loop of the memory cell and a ground terminal of a chip. 1. A semiconductor memory circuit device characterized by inserting a resistance element connected in parallel.