JPH0453840B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor manufacturing technology, and particularly to a semiconductor manufacturing technology that can obtain a semiconductor material with few micro defects.

[Background Art] Generally, in a semiconductor manufacturing process such as silicon (Si) crystal manufacturing, ingot annealing (600 to 650° C.) is sometimes performed to eliminate oxygen donors. Generally, for crystals with a diameter of 100 mm or less, the ingot annealing method as shown in Figure 1 is used.
For crystals with a diameter of 125 mm or more, the wafer annealing method shown in Figure 2 is used.

As the diameter of a single crystal ingot increases, its heat capacity increases and cracks are more likely to occur due to rapid cooling.Currently, crystals with a diameter of 125 mm or more are annealed in wafer form. The purpose of this annealing is to eliminate oxygen donors and reduce variations in resistivity in the longitudinal direction and cross section of the ingot, and to promote nucleation of microdefects.

By the way, the mainstream material for semiconductor devices currently in use is silicon crystal, and its growing methods include the Czyochralski method (CZ method, pulling method) and the floating zone method (FZ method, zone melting refining method).
There is. Currently, most wafers used for silicon devices, mainly LSI, are grown using the CZ method.

In the CZ method, polycrystalline silicon is melted in a quartz crucible, and the seed crystal immersed in the melt is rotated relative to the crucible while the seed crystal is pulled up to grow a crystal. In crystals grown by the CZ method, micro defects (precipitation of oxygen) are nucleated in each part of the single crystal ingot due to temperature fluctuations at the solid-liquid interface during growth or differences in heat radiation in the furnace after growth. is changing.

Further, the nucleation degree also varies depending on the oxygen concentration.

Therefore, there is an element of variation in the bulk quality of wafers sliced from a single ingot. For example, a crystal in which oxygen easily precipitates has a high microdefect density. Since micro defects serve as centers for dislocation generation, the critical stress at which slips occur is reduced. Therefore, the wafer with higher microdefect density
Slips and warpage are likely to occur during heat treatment in the LSI process, reducing mask transfer accuracy in the photolithography process. On the other hand, the introduced thermal stress dislocations deteriorate device characteristics and cause a decrease in yield.

In recent years, there has been significant progress in the integration and performance of devices, and the problem of crystal defect control caused by micro defects has become one of the biggest concerns in terms of process.

In solid-state imaging devices, the presence of crystal defects causes white spot defects in images, which is the biggest cause of yield decline.

Figure 3 shows the relationship between warpage and microdefect density of a φ100 wafer mounted using a CMOS 5μm process. It can be seen that the higher the microdefect density, the greater the amount of warpage. Figure 3 measures the warpage of a wafer extracted after completing the _N2 annealing process.

Micro defect density is 40μm after oxidation at 1000℃ for 16 hours
This is a value measured in depth.

For reference, the correlation between warpage and microdefect density obtained through forced heat treatment simulation is shown in the fourth section as an experimental result.
As shown in Fig. and Fig. 5.

This warpage evaluation experiment performed two-stage forced heat treatment. The inner diameter of the quartz tube of the heat treatment furnace used for this warpage evaluation was 150 mm, and two-stage forced heat treatment (),
() was conducted under the following conditions.

Forced heat treatment () 1000℃, 20min (holding) Wafer spacing: 5mm Input/output speed: 20cm/min Forced heat treatment () 1000℃, 20min (holding) Wafer spacing: 5mm Input/output speed: 35cm/min Note that in this experiment, each Since the initial warpage of the wafer is subtracted from the amount of warpage due to heat treatment, the warpage represents the net value of compositional deformation due to forced heat treatment.

If two-stage heat treatment is performed at 800°C-1000°C, the density of minute defects will increase, making it easier to warp.

The broken lines in FIGS. 4 and 5 represent the results obtained with comparison wafers taken from ingots grown under different growth conditions.

These results show that, for example, if the oxygen concentration in the crystal changes, the nucleation and growth of micro defects will differ, and the ease with which slips will occur will differ.

As described above, warping due to thermal stress strongly depends on the quality of the single crystal, especially on the state of oxygen precipitation (microdefect density).

In Figure 3, if the warpage exceeds ~70μm, the CMOS will be 5μm.
It is also known that the transfer accuracy in the photoetching process deteriorates, and the device yield deteriorates. In the future, as higher integration progresses, there will be a need to make them smaller.

In order to satisfy these demands, in the device process, furnace cooling (ramping) is becoming more and more popular during heat treatment. Meanwhile, from 800-900℃
If ramping is performed, oxygen precipitation nuclei are likely to occur, and micro defects are likely to grow, resulting in a decrease in the strength of the crystal. Therefore, there is an increasing demand for homogeneous crystals that are less likely to cause oxygen to precipitate during heat treatment, that is, have fewer microdefect nuclei.

[Object of the Invention] An object of the present invention is to provide a semiconductor manufacturing technique that can reduce the number of microdefect nuclei in a semiconductor material.

Another object of the present invention is to provide a semiconductor manufacturing technique that can prevent cracks from occurring in the crystal of a semiconductor material.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, by heating an ingot of a semiconductor material with radiant heat, rapidly cooling it to a predetermined temperature, and holding it at that predetermined temperature for a predetermined period of time, it is possible to prevent the formation of microdefect nuclei (nuclei of oxygen precipitation) and to prevent cracks in the ingot. can be prevented from occurring.

[Embodiment] FIG. 6 is a schematic cross-sectional view showing an embodiment of a semiconductor manufacturing apparatus according to the present invention.

In this embodiment, the annealing heat treatment furnace has a vertical furnace structure composed of a transparent quartz bell jar 1, and a lid 2 is provided on the top of the quartz bell jar 1.

Inside this quartz bell gear 1, there is a gas inlet 3.
A non-oxidizing atmospheric gas 4, for example an inert gas such as nitrogen or argon gas, is supplied from the tank.

On the other hand, an ingot 5 made of, for example, a single crystal of silicon is charged inside the quartz bell gear 1, and this ingot 5 is fixed with a chuck 7 above the quartz bell gear 1, and is heated at 0 to 30 r.p.
supported for rotation at a speed of m. The seed crystal 5a remains in the upper part of the ingot 5 of this embodiment, and the seed crystal 5a is not separated from the grown ingot 5, which is one of the features of this embodiment.

Further, in the apparatus of this embodiment, a radiant heat source is used as a heat source for annealing, and this radiant heat source is composed of an infrared lamp 6. The infrared lamp 6 is arranged on the outer peripheral side of the quartz bell gear 1, and by turning the power on and off, the ingot 5 can be heated and annealed without contact, and can be rapidly cooled.

Next, the operation when a silicon single crystal ingot is annealed according to this embodiment will be explained.

First, as shown in FIG. 6, while the ingot 5 supported in a non-contact manner in the quartz bell jar 1 is rotated by a rotating means (not shown), the ingot 5 is heated by infrared rays 6a from an infrared lamp 6, for example.
Heat to 1200-1350℃ and hold for several hours to anneal. In order to improve the annealing effect, it is desirable that the heating temperature be higher.

FIG. 7 shows an example of annealing at two annealing temperatures of 1200°C and 1350°C.

After performing annealing for a predetermined time at these annealing temperatures, the output of the infrared lamp 6 is reduced to rapidly cool. The temperature program during this rapid cooling is shown in FIG.

The temperature program in Figure 7 starts with 10
Cool at a cooling rate of ~15°C/min, then approximately 1100°C
By rapidly cooling from 300°C to 300°C at a cooling rate of 25 to 100°C/min, rapid cooling is performed at two stages of cooling rates.

In this rapid cooling operation, the effects of suppressing the re-formation of nuclei of micro defects in the ingot 5 at 1100°C to 650°C and suppressing the re-formation of oxygen donors at 650°C to 400°C are obtained.

Further, the reason why the temperature is temporarily maintained at 300°C is to prevent cracks from occurring in the ingot 5 due to thermal distortion caused during rapid cooling.

Note that when the temperature is 300° C. or lower, further rapid cooling can be performed after a predetermined period of time, and the cooling rate in this case can be set to a different cooling rate from the two-stage rapid cooling described above.

According to this embodiment, since the silicon single crystal ingot 5 can be annealed at high temperature in a non-contact state, the nuclei of minute defects (oxygen precipitation, ) can be dissolved in solid solution. In addition, since it uses a radiation heating method using an infrared lamp 6, it is possible to cool the crystal more rapidly than in a normal resistance heating method.

Therefore, it is possible to suppress the process in which supersaturated oxygen aggregates during cooling and becomes the nucleus of micro defects. A silicon wafer sliced from such a single crystal ingot 5 and subjected to mirror processing is less prone to oxygen precipitation even in the LSI process, and therefore has extremely few occurrences of minute dislocation loops and oxidation-induced stacking faults.

Currently, a method of examining the microdefect density in the bulk is used as a single crystal evaluation method. In this method, the wafer is oxidized at 1000℃ for 10 hours, and the surface is
After mirror polishing to 40 μm, etching was performed using light etchant for 5 minutes. The number of defects at a specified location is determined and converted to volumetric density (pieces/cm ³ ).

According to this method, the level of general crystals is 10 ⁷
In contrast, the method of this embodiment (experimental results of wafer annealing) achieves a level of 10 ^{5 particles} /cm ³ or ^less . Nowadays, as the temperature of LSI processes is being lowered, crystals are being used under increasingly severe conditions, and this embodiment is extremely useful for this purpose.

[Effects] (1) The ingot annealed according to the present invention has very few nuclei of micro defects (nuclei of oxygen precipitation), and it is possible to obtain good specially manufactured semiconductor devices with a high yield.

(2) By rapidly cooling the ingot to a predetermined temperature after annealing and holding the ingot at that predetermined temperature for a predetermined period of time, it is possible to prevent the occurrence of cracks in the ingot.

Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.

For example, the rate of quenching the ingot can be varied depending on the annealing temperature and the type of semiconductor material.

Further, the method of the present invention can be applied not only to ingots but also to sliced wafers.

Furthermore, a high frequency coil or the like can also be used as a radiant heat source in addition to an infrared lamp.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to the application field of annealing of silicon single crystal ingots, which is the background of the invention, but the present invention is not limited thereto. , for example, gallium-arsenide (Ga-As),
It can also be applied to - group compound semiconductors such as gallium-phosphide (Ga-P) or - group compound semiconductors. For example, the annealing temperature in that case is
It is desirable to set the temperature to 0.85Tk to 0.95Tk (Tk: melting point, expressed as absolute temperature).

[Brief explanation of the drawing]

Figure 1 shows the steps of the ingot annealing method, Figure 2 shows the steps of the wafer annealing method, and Figure 3 shows the relationship between wafer warpage and microdefect density after N ₂ annealing. Figure 4 is a diagram showing the relationship between wafer warpage and microdefect density due to forced heat treatment, Figure 5 is a diagram showing the relationship between wafer warpage and microdefect density due to another forced heat treatment, and Figure 6
The figure is a schematic sectional view showing an embodiment of the semiconductor manufacturing apparatus according to the present invention, and FIG. 7 is a diagram showing a temperature program for annealing and rapid cooling in the present invention. 1...quartz bell jar (furnace), 2...lid, 3...
...Gas inlet, 4...Atmospheric gas, 5...Ingot, 5a...Seed crystal, 6...Infrared lamp (radiant heat source), 6a...Infrared rays, 7...Chick.

Claims (1)

[Claims] 1. A semiconductor manufacturing method in which a semiconductor material is annealed at a high temperature, characterized by heating an ingot of the semiconductor material with radiant heat to anneal it, then rapidly cooling it to a predetermined temperature, and holding the ingot at the predetermined temperature for a predetermined period of time. A semiconductor manufacturing method. 2. The semiconductor manufacturing method according to claim 1, wherein the cooling is performed at different cooling rates in multiple stages depending on the temperature of the rapidly cooled ingot. 3. A semiconductor manufacturing apparatus for annealing semiconductor materials at high temperatures, characterized in that an ingot of the semiconductor material is held in a furnace in a non-contact state, and a radiant heat source is provided for heating the ingot in a radiant state. 4. The semiconductor manufacturing apparatus according to claim 3, wherein the radiant heat source is an infrared lamp.