JPH0454005A - Pll type fm demodulation circuit - Google Patents

Pll type fm demodulation circuit

Info

Publication number
JPH0454005A
JPH0454005A JP16284390A JP16284390A JPH0454005A JP H0454005 A JPH0454005 A JP H0454005A JP 16284390 A JP16284390 A JP 16284390A JP 16284390 A JP16284390 A JP 16284390A JP H0454005 A JPH0454005 A JP H0454005A
Authority
JP
Japan
Prior art keywords
circuit
voltage controlled
intermittent
pll
loop filter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16284390A
Other languages
Japanese (ja)
Inventor
Haruo Sakata
坂田 晴夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Faurecia Clarion Electronics Co Ltd
Original Assignee
Clarion Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clarion Co Ltd filed Critical Clarion Co Ltd
Priority to JP16284390A priority Critical patent/JPH0454005A/en
Publication of JPH0454005A publication Critical patent/JPH0454005A/en
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To reduce the operating time at the 2nd application of an FM modulation wave by intermitting the connection between a loop filter and a voltage controlled oscillator circuit in response to the interruption of the FM modulation wave with a detection signal from an amplitude detector and keeping a control voltage of the voltage controlled oscillator circuit at a prescribed value. CONSTITUTION:An electronic switch 4 intermite in response to a pulse from a pulse shaping circuit 3 to connect a loop filter 11 and a capacitor C alternately. That is, When an output from the shaping circuit 3 is present, the electronic switch 4 connects an output of the filter 11 to a voltage controlled oscillator circuit 12 to apply an intermittent FM modulation wave to the oscillation circuit 12 and connects the capacitor C to a loop of a PLL circuit 1. Thus, the control voltage of the voltage controlled oscillator circuit 12 is kept to a voltage just before the intermittent FM modulation wave is OFF. As a result, the operating time when a 2nd intermittent FM modulation wave is applied is reduced, resulting that the intermittent FM modulation wave is demodulated.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 この発明はPLL型FMul調回路に関する。[Detailed description of the invention] <Industrial application field> The present invention relates to a PLL type FMul adjustment circuit.

〈従来の技術〉 PLL型F Mlj[J回路ti F M変調信号ヲ位
相Jt較回路に加えて、電圧制御発振回路からの信号と
の位相比較の出力をループフィルタに加えて、ベースバ
ンド信号として出力すると共に電圧制御発振回路をFM
変調して位相比較回路にフィードバックする楕成になっ
ている。
<Prior art> PLL type F Mlj [J circuit ti In addition to the phase Jt comparison circuit for the F M modulation signal, the output of the phase comparison with the signal from the voltage controlled oscillation circuit is added to the loop filter, and is output as a baseband signal. FM output and voltage controlled oscillation circuit
It has an elliptical configuration that modulates and feeds back to the phase comparator circuit.

このt!am回路に加えるT” M変調波は、第6図の
(a)に示すように時間軸に対して連続な変調波が一般
的であるが、用途によっては(b)に示すようなTのパ
ルスでゲー1−した形の間欠的なFM散調波髪入力とす
る場合もある。
This t! The T''M modulated wave applied to the am circuit is generally a continuous modulated wave with respect to the time axis as shown in Figure 6 (a), but depending on the application, the T''M modulated wave as shown in (b) is used. An intermittent FM scattering wave input in the form of a pulsed signal may also be used.

〈発明が解決しようとする課題〉 しかしこのような間欠的なFM変調波を上記したPLL
mFMtM#4回路に加えた場合、復調回路が十分に応
答できずに第2図の従来例に示すような出力波形となる
欠点があった。
<Problem to be solved by the invention> However, the above-mentioned PLL cannot handle such intermittent FM modulation waves.
When added to the mFMtM#4 circuit, there was a drawback that the demodulation circuit could not respond sufficiently, resulting in an output waveform as shown in the conventional example shown in FIG.

本発明は上記した従来技術の欠点を解決するためになさ
れたもので、間欠的FM変調波に対しても十分対応する
PLL型FM変!#l器を提供することを目的とする。
The present invention was made in order to solve the above-mentioned drawbacks of the prior art, and is a PLL type FM modulation system that can sufficiently cope with intermittent FM modulation waves! The purpose is to provide #1 equipment.

〈課題を解決するための手段〉 この目的のために本発明は、位相比較回路とループフィ
ルタと電圧制御発振回路とから成るPLLループを形成
し、所定のFM変調波を復調するPLL回路と、所定周
期のパルス信号によりゲートされた間欠的なFM変調波
を入力し、これを振幅検波して検波信号を出力する振幅
検波器と、前記ループフィルタと電圧制御発振回路の間
に介装され、前記検波信号に基づいて該ループフィルタ
と電圧制御発振回路との接続を断続切換する切換回路と
を備えたことを基本的な特徴とするものである。
<Means for Solving the Problems> For this purpose, the present invention provides a PLL circuit that forms a PLL loop consisting of a phase comparison circuit, a loop filter, and a voltage controlled oscillation circuit, and demodulates a predetermined FM modulated wave; interposed between the loop filter and the voltage controlled oscillation circuit, an amplitude detector that inputs an intermittent FM modulated wave gated by a pulse signal of a predetermined period, performs amplitude detection of the wave, and outputs a detected signal; A basic feature of the present invention is that it includes a switching circuit that switches connection between the loop filter and the voltage controlled oscillation circuit on and off based on the detected signal.

く作用〉 振幅検波器からの検波信号によりループフィルタと電圧
制御発振回路との接続はFM変調波の間欠に応じて断続
される。接続が断の時にはループフィルタのキャパシタ
ンスのみが電圧制御発振回路に接続され、ia電圧制御
発振回路制御電圧を所定の値に保持する。そのため次に
FM変調波が加った時の動作時間を短縮する。
Effect> The connection between the loop filter and the voltage controlled oscillation circuit is disconnected according to the intermittency of the FM modulated wave by the detection signal from the amplitude detector. When the connection is disconnected, only the capacitance of the loop filter is connected to the voltage controlled oscillation circuit, and the ia voltage controlled oscillation circuit control voltage is maintained at a predetermined value. Therefore, the operation time when the FM modulated wave is applied next time is shortened.

く実施例〉 以下本発明の一実施例を図面に基づいて説明する。Example An embodiment of the present invention will be described below based on the drawings.

第1図においてPLL回路1は位相比較回路10と例え
ばラフフィルタ等のループフィルタ11と電圧制御発振
回路12から構成されており、従来のものと変わるとこ
ろはない。ループフィルタ11の出力(illHま高イ
ンピーダンスバッファアンプ5を介してベースバンド信
号として出力されると共に、電子スイッチ4を介して電
圧制御発振回路12にフィードバックされている。電子
スイッチ4はループフィルタ11と電圧制御発振回路1
2の間に介装されており、更に正確には第3図に示すよ
うに積分回路であるループフィルタ11の抵抗Rとキャ
パシタンスCの間に電子スイッチ4は介装された構成に
なっている。
In FIG. 1, a PLL circuit 1 is composed of a phase comparator circuit 10, a loop filter 11 such as a rough filter, and a voltage controlled oscillation circuit 12, and there is no difference from the conventional one. The output of the loop filter 11 (illH) is output as a baseband signal via the high impedance buffer amplifier 5, and is also fed back to the voltage controlled oscillation circuit 12 via the electronic switch 4. Voltage controlled oscillation circuit 1
More precisely, as shown in FIG. 3, the electronic switch 4 is interposed between the resistor R and capacitance C of the loop filter 11, which is an integrating circuit. .

間欠FM変調波はPLL回路1に入力されると共に振幅
検波器2にも入力されるように構成されている。振幅検
波器2は所定周期のパルス信号によりゲートされたこの
間欠FM変調波を振軸°検波して更にパルス整形回!!
83により波形整形して第2図の上段に示すパルス波形
を出力するように構成されている。このパルス整形回路
3の出力のオンオフはそのまま間欠FM変調波のオンオ
フ(信号部と無信号部)に対応している。
The intermittent FM modulated wave is input to the PLL circuit 1 and also to the amplitude detector 2. The amplitude detector 2 detects this intermittent FM modulated wave gated by a pulse signal of a predetermined period, and further performs pulse shaping! !
83 to output the pulse waveform shown in the upper row of FIG. 2. The on/off of the output of the pulse shaping circuit 3 directly corresponds to the on/off of the intermittent FM modulated wave (signal portion and non-signal portion).

前記した電子スイッチ4はこのパルス整形回路3からの
パルスに応答して断続し、電圧制御発振回路12に対し
てループフィルタ11とキャパシタンスCを交互に接続
するように構成されている。
The electronic switch 4 described above is configured to be turned on and off in response to pulses from the pulse shaping circuit 3, and to alternately connect the loop filter 11 and the capacitance C to the voltage controlled oscillation circuit 12.

即ち、パルス整形回路3からの出力がオンの時は電子ス
イッチ4はループフィルタ11の出力し電圧制御発振回
路12に接続して間欠FM変調波を電圧制御発振回路1
2に供給し、またキャパシタンスCをPLL回路1のル
ープに接続する。パルス整形回路3からの出力がオフの
時は間欠FM変調波は無信号であるから、この時にはキ
ャパシタンスC1,−PLL回路回路用−プから切り離
して電圧制御発振回路12のみに接続し、キャパシタン
スCに蓄積された電荷を電圧制御発振口wT12に供給
するように構成されている。
That is, when the output from the pulse shaping circuit 3 is on, the electronic switch 4 outputs the loop filter 11 and connects it to the voltage controlled oscillation circuit 12 to transmit the intermittent FM modulated wave to the voltage controlled oscillation circuit 1.
2 and also connects the capacitance C to the loop of the PLL circuit 1. Since the intermittent FM modulated wave has no signal when the output from the pulse shaping circuit 3 is off, at this time, the capacitance C1 is disconnected from the PLL circuit circuit and connected only to the voltage controlled oscillation circuit 12, and the capacitance C1 is disconnected from the PLL circuit circuit. It is configured to supply the charges accumulated in the voltage controlled oscillation port wT12.

上Ke !子スイッチ4としては種々の構成を採用する
ことが可能であるが、この実施例では第4図に示すよう
にダイオードブリッジを用いている。
Upper Ke! Although various configurations can be adopted as the child switch 4, in this embodiment, a diode bridge is used as shown in FIG. 4.

以上の構成において1間欠FM変調波はPLL回路1に
入力すると共に、振幅検波器2に人力し、パルス整形回
路3を介して第2図の上段に示すパルスが電子スイッチ
4に供給される。t、〜t2間では電子スイッチ4はオ
ンになり、l) L L回路1のループが形成され、高
インピーダンスバッファアンプ5からは第2図の中段に
示す波形が出力される。即ちFM変調波がt1〜t2間
では忠実にFM復調される6次ぎにt2〜t1間では電
子スイッチ4はオフになり、PLL回路1のループが切
断されキャパシタンスCのみが電圧制御発振回路12に
接続する。この時キャパシタンスCにはt。
In the above configuration, one intermittent FM modulated wave is input to the PLL circuit 1 and also input to the amplitude detector 2, and the pulse shown in the upper part of FIG. 2 is supplied to the electronic switch 4 via the pulse shaping circuit 3. Between t and t2, the electronic switch 4 is turned on, and a loop of the LL circuit 1 is formed, and the high impedance buffer amplifier 5 outputs the waveform shown in the middle part of FIG. That is, the FM modulated wave is faithfully FM demodulated between t1 and t2. Then, between t2 and t1, the electronic switch 4 is turned off, the loop of the PLL circuit 1 is cut off, and only the capacitance C is connected to the voltage controlled oscillation circuit 12. Connecting. At this time, the capacitance C is t.

時点の電位に対応する電位が存在するため、他に電荷の
リークがない限りt2〜t3間では、電圧制御発振回路
12の制御電圧はt2時点の電圧が保存される。次ぎに
t、〜t4間では電子スイッチ4がオンとなりPLL回
路1のループが形成され、出力波形の電位はB点から0
点に移動しF M復調を続ける。以下同様な動作を繰り
返し、電子スイッチ4がオンの時だけFM復調を行う。
Since there is a potential corresponding to the potential at time, the voltage at time t2 is maintained as the control voltage of the voltage controlled oscillation circuit 12 between t2 and t3 unless there is any other charge leakage. Next, between t and t4, the electronic switch 4 is turned on and a loop of the PLL circuit 1 is formed, and the potential of the output waveform changes from point B to 0.
point and continue FM demodulation. Thereafter, similar operations are repeated, and FM demodulation is performed only when the electronic switch 4 is on.

また電子スイッチ4がオフの時は所定の電位が維持され
、次のオンの時に動作時間が短くなるから間欠的なFM
変調波の復調が可能になる。
Also, when the electronic switch 4 is off, a predetermined potential is maintained, and when the electronic switch 4 is turned on, the operating time is shortened, so intermittent FM
It becomes possible to demodulate the modulated wave.

なお、必要であれば適当なゲート手段を用いて電子スイ
ッチ4がオンの時の出力だけを取り出すようにしても良
い。
Note that, if necessary, an appropriate gate means may be used to extract only the output when the electronic switch 4 is on.

第5図に他の実施例を示す。この実施例では入力するF
M変調波が第6図の(a)に示すように連続する変調波
の場合、これをスイッチパルス発生器7により電子スイ
ッチャ8を断続させて間欠的なFM変調波に変換するよ
うに構成している。
FIG. 5 shows another embodiment. In this example, input F
When the M modulated wave is a continuous modulated wave as shown in FIG. 6(a), the electronic switcher 8 is turned on and off by the switch pulse generator 7 to convert it into an intermittent FM modulated wave. ing.

この構成の場合電子スイッチ4はスイッチパルス発生器
7の出力をパルス整形回路3で波形整形したものを用い
ている。他の構成は第1図の構成と同じである。
In this configuration, the electronic switch 4 uses the output of the switch pulse generator 7 whose waveform is shaped by the pulse shaping circuit 3. The other configurations are the same as those shown in FIG.

以上説明したように上記構成によれば、間欠的なFM変
調波が電圧制御発振回路12に与えられていない時はル
ープフィルタ11のキャパシタンスCを電圧制御発振回
路12のみに供給するから。
As explained above, according to the above configuration, when the intermittent FM modulated wave is not applied to the voltage controlled oscillation circuit 12, the capacitance C of the loop filter 11 is supplied only to the voltage controlled oscillation circuit 12.

電圧制御発振回路12の制御電圧な間欠FM変調波がオ
フとなる直前の電圧に保持することが出来。
The control voltage of the voltage controlled oscillation circuit 12 can be maintained at a voltage just before the intermittent FM modulated wave is turned off.

その結果への間欠的なFM変調波が加わった時の動作時
間を短くすることが出来る。その結果間欠的なFM変調
波の復調が可能になる。
The operation time when intermittent FM modulated waves are added to the result can be shortened. As a result, intermittent demodulation of FM modulated waves becomes possible.

〈発明の効果〉 以上説明したように本発明のPLL型F M ttht
調回路は1位相比較回路とループフィルタと電圧制御発
振回路とから成るPLLループを形成し、所定のFM変
調波を復調するPLL回路と、所定周期のパルス信号に
よりゲートされた間欠的なFM変調波を入力し、これを
振幅検波して検波信号を出力する振幅検波器と、前記ル
ープフィルタと電圧制御発振回路の間に介装され、前記
検波信号に基づいて該ループフィルタと電圧制御発振回
路との接続を断続切換する切換回路とを有しているため
、間欠的なFM変調波の復調が可能になる効果がある。
<Effects of the Invention> As explained above, the PLL type FM ttht of the present invention
The modulation circuit forms a PLL loop consisting of a single phase comparison circuit, a loop filter, and a voltage controlled oscillation circuit, and includes a PLL circuit that demodulates a predetermined FM modulation wave, and an intermittent FM modulation gated by a pulse signal of a predetermined period. an amplitude detector that inputs a wave, performs amplitude detection on the detected signal, and outputs a detected signal; and an amplitude detector that is interposed between the loop filter and the voltage controlled oscillation circuit, and that operates based on the detected signal between the loop filter and the voltage controlled oscillation circuit. Since it has a switching circuit that switches the connection between the two and on and off, it has the effect of making it possible to demodulate the FM modulated wave intermittently.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すブロック図、第2図は
その動作説明図、第3図はループフィルタ11の回路図
、第4図は電子スイッチ4の一例を示す回路図、第5図
は他の実施例を示すブロック図、第6図はFM変調波の
説明図である。 1 : PLL回路、2:振幅検波器、3:パルス整形
回路、4:電子スイッチ、5:高インピーダンスバッフ
ァアンプ1.7:スイッチパルス発生器、8:電子スイ
ッチャ、1o:位相比較回路、11:ループフィルタ、
12:@圧制御発振回路。 特許出願人   クラリオン株式会社 代理人     弁理士 高 橋 清
1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of its operation, FIG. 3 is a circuit diagram of the loop filter 11, FIG. 4 is a circuit diagram showing an example of the electronic switch 4, and FIG. FIG. 5 is a block diagram showing another embodiment, and FIG. 6 is an explanatory diagram of FM modulated waves. 1: PLL circuit, 2: Amplitude detector, 3: Pulse shaping circuit, 4: Electronic switch, 5: High impedance buffer amplifier 1.7: Switch pulse generator, 8: Electronic switcher, 1o: Phase comparison circuit, 11: loop filter,
12:@Pressure control oscillation circuit. Patent applicant: Clarion Co., Ltd. Representative: Patent attorney Kiyoshi Takahashi

Claims (1)

【特許請求の範囲】 位相比較回路とループフィルタと電圧制御発振回路とか
ら成るPLLループを形成し、所定のFM変調波を復調
するPLL回路と、 所定周期のパルス信号によりゲートされた間欠的なFM
変調波を入力し、これを振幅検波して検波信号を出力す
る振幅検波器と、 前記ループフィルタと前記電圧制御発振回路の間に介装
され、前記検波信号に基づいて該ループフィルタと電圧
制御発振回路との接続を断続切換する切換回路と、 を有することを特徴とするPLL型FM復調回路。
[Claims] A PLL circuit that forms a PLL loop consisting of a phase comparator circuit, a loop filter, and a voltage controlled oscillation circuit and demodulates a predetermined FM modulated wave; FM
an amplitude detector that inputs a modulated wave, performs amplitude detection on the modulated wave, and outputs a detected signal; and an amplitude detector that is interposed between the loop filter and the voltage controlled oscillation circuit, and that performs voltage control with the loop filter based on the detected signal. A PLL type FM demodulation circuit comprising: a switching circuit that switches connection with an oscillation circuit on and off; and a PLL type FM demodulation circuit.
JP16284390A 1990-06-22 1990-06-22 Pll type fm demodulation circuit Pending JPH0454005A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16284390A JPH0454005A (en) 1990-06-22 1990-06-22 Pll type fm demodulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16284390A JPH0454005A (en) 1990-06-22 1990-06-22 Pll type fm demodulation circuit

Publications (1)

Publication Number Publication Date
JPH0454005A true JPH0454005A (en) 1992-02-21

Family

ID=15762301

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16284390A Pending JPH0454005A (en) 1990-06-22 1990-06-22 Pll type fm demodulation circuit

Country Status (1)

Country Link
JP (1) JPH0454005A (en)

Similar Documents

Publication Publication Date Title
GB1256188A (en) Generator for producing ultrasonic oscillations
US4618967A (en) Radio receiver
JPH0454005A (en) Pll type fm demodulation circuit
US3204195A (en) Oscillator frequency stabilization during loss of afc signal
GB1419562A (en) Method of generating a phase-modulated rectangular wave
JP2710104B2 (en) Transmission device
JPS6232716A (en) Waveform shaping circuit
JPS58137308A (en) Pulse counting type frequency discriminator
JP2626193B2 (en) FM demodulator
JPS636949Y2 (en)
SU1244768A1 (en) Device for pulse-phase controlling of converter
JPH033830U (en)
JPH03101043U (en)
JPH0270106A (en) Phase difference detection circuit
JPH03121409U (en)
JPH0172737U (en)
JPH0415308U (en)
JPH0357644U (en)
JPS54159210A (en) Emphasis circuit of fm modulator and demodulator
JPS588636B2 (en) SECAM Irosingou Fukuchiyou Cairo
JPH0480119U (en)
JPH02101283U (en)
JPS5483354A (en) Data reproduction circuit
JPH0429221U (en)
JPS5923656B2 (en) PLL circuit synchronization judgment signal forming circuit