JPH0454632A - Arithmetic control ic and information processor - Google Patents

Abstract

PURPOSE:To realize plural operations which necessitate a table and a buffer provided in a memory by using one external memory in common by plural arithmetic circuits, since the external memory is connected selectively to each arithmetic control circuit by a selector circuit. CONSTITUTION:When an instruction for executing a first operation is issued to a control circuit 103 from a CPU through a bus 101, the control circuit 103 applies an actuation to an arithmetic circuit 104. The arithmetic circuit 104 executes an arithmetic processing to data inputted through the bus 101. Subsequently, in the case it is necessary to execute buffering to an intermediate value generated in the midst of its processing, the arithmetic circuit 104 issues a write enable signal to a RAM 102 through a selector 110 and sets it to a write state. The control circuit 103 controls the processing by operating selectors 108 - 112 in said arithmetic processing. In such a way. plural operations which necessitate a table and a buffer provided in a memory can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic control IC that executes various arithmetic operations, and particularly relates to an image processor that executes image arithmetic processing.

[Prior Art] In recent years, as memories have become faster and cheaper, it has become common practice to provide a table in memory and perform various calculations with reference to this table.

That is, as described in Japanese Unexamined Patent Publication No. 60-65332, output data from an arithmetic circuit that performs arithmetic processing is input directly to the address line of the memory, and output data from the memory is input to the arithmetic circuit. Configure for direct input.

When executing a calculation, the calculation circuit directly accesses the calculation table provided in the memory in advance to obtain the calculation result.

In this way, according to this technology, a large amount of data can be processed at high speed and complex arithmetic processing can be realized with a simple circuit.

[Problems to be Solved by the Invention] According to the above-mentioned conventional technology, it is necessary to prepare separate memories for each operation.

However, if this conventional technology is applied to, for example, executing arithmetic processing that requires multiple tables on - LSIs, a separate memory must be connected for each arithmetic processing. , it becomes inefficient.

Furthermore, since address lines and data lines are required for each memory, the number of external signal pins of the LSI increases, causing a problem that implementation becomes impossible due to the limitation of the number of external signal pins.

A similar problem also occurs when arithmetic processing requires a buffer rather than a tape.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an arithmetic control IC that can perform a plurality of arithmetic operations that require tables and buffers provided in memory.

[Means for Solving the Problems] In order to achieve the above object, the present invention selectively uses a plurality of arithmetic circuits that perform arithmetic operations and a plurality of arithmetic circuits.

A first arithmetic control IC is provided, characterized in that it has a selector circuit connected to an external memory.

In order to achieve the above object, the present invention also provides a plurality of arithmetic circuits that perform arithmetic operations using an arithmetic table provided in an external memory, an address terminal to the external memory, and data to two or more of the arithmetic circuits. a selector circuit that selectively connects a data input terminal from an external memory connected to the input and a data output from one of the two or more arithmetic circuits to an address terminal for the external memory; A second arithmetic control IC is provided.

In addition, in this second arithmetic control IC, the external memory is a rewritable memory, and a data setting circuit outputs data of a calculation table used by the two or more arithmetic circuits, and table data outputted by the data setting circuit. an address generation circuit that generates an address for storing the data, and a data output terminal to an external memory connected to the data output from the data setting circuit, and the selector circuit is configured to select one of the two or more arithmetic circuits. The data output from the arithmetic circuit or the address output generated by the address generation circuit may be selectively connected to the address terminal for the external memory.

Further, in order to achieve the above object, the present invention provides a plurality of arithmetic circuits that perform arithmetic operations using an external memory as a data buffer, an address terminal to the external memory, a data output terminal to the external memory, and two or more A data input terminal from an external memory connected to a data input to the arithmetic circuit of the above, and a data output from any one of the two or more arithmetic circuits are selectively connected to the data input terminal to the external memory. A selector circuit connected to an output terminal and an address of an external memory that stores output data of the two or more arithmetic circuits or reads input data to the two or more arithmetic circuits to the address terminal for the external memory. A third arithmetic control IC is provided, characterized in that it has an address generation circuit.

Furthermore, in order to achieve the above object, the present invention provides one or more first type arithmetic circuits that perform arithmetic operations using an arithmetic table provided in an external memory, and an external memory that is used as a data buffer to perform an arithmetic operation. one or more second type arithmetic circuits, an address terminal to an external memory, data input to the one or more first type arithmetic circuits, and data input to the one or more second type arithmetic circuits; reading a data input terminal from a connected external memory and an address of an external memory that stores output data of the one or more second type arithmetic circuits, or input data to the one or more second type arithmetic circuits; an address generation circuit that selectively outputs an address of an external memory;
a selector circuit that selectively connects data output from one of the one or more first type arithmetic circuits or an address generated by an address generation circuit to an address terminal to the external memory; and a data output terminal to an external memory connectable to the data output from the one or more second type arithmetic circuits.
provides arithmetic control ICs.

Note that in the fourth arithmetic control IC, the external memory is a rewritable memory, and a data setting circuit that outputs table data used by the one or more first type arithmetic circuits to the external memory; a second selector circuit that selectively connects the data output from one of the first type arithmetic circuits or the data output from the data setting circuit to a data output terminal to the external memory; and the address generating circuit is configured to generate an address of an external memory that stores output data of the one or more second type arithmetic circuits, or an external memory that reads input data to the one or more second type arithmetic circuits. memory address, or
The address of the external memory storing the table data output by the data setting circuit may be selectively output.

In addition, the present invention particularly provides that, in the fourth arithmetic control IC, the first type arithmetic circuit performs image density conversion processing, and the second type arithmetic circuit performs 90'' rotation processing of the image. An image processor characterized by the following is provided as a fifth arithmetic control IC.

In addition, the present invention also provides a memory for storing two or more calculation tables used by the calculation control IC and the calculation circuit of the calculation control IC, or a memory used as a data buffer for the two or more calculation circuits. Alternatively, the present invention also provides an information processing device characterized in that it includes one or more arithmetic circuits that store one or more arithmetic tables and a memory used as a data buffer.

[Function] According to the first arithmetic control IC according to the present invention, the selector circuit selectively connects the external memory to each arithmetic control circuit, so that one external memory is shared by a plurality of arithmetic circuits. be able to.

Further, according to the second arithmetic control IC according to the present invention, the two or more arithmetic circuits output data to the external memory from the address terminal for the external memory via the selector circuit, and use this data as an address to externally output the data to the external memory. Since data read from the memory can be received from the data input terminal from the external memory, one external memory can be used as each calculation table.

Further, according to the third arithmetic control circuit according to the present invention, the two or more arithmetic circuits store the output data in the external memory via the selector, and convert the read data into the data from the external memory. Since data can be received from the input terminal, one external memory can be used as a data buffer for each.

Further, according to the fourth arithmetic control IC according to the present invention, when using the arithmetic table in the external memory, the selector circuit controls how data is output from the first type arithmetic circuit that uses the arithmetic table. Alternatively, when using external memory as a data buffer, the address generated by the address generation circuit,
An address for storing output data of a second type arithmetic circuit that uses an external memory as a data buffer is connected to an address terminal to the external memory. Further, the data output from the one or more second type arithmetic circuits is connected to the data output terminal when the data is stored in the external memory.

Therefore, one external memory is used as a calculation table for the one or more first type arithmetic circuits, and also as a calculation table for the one or more first type arithmetic circuits.
The type of arithmetic circuit can be used as a data buffer.

Furthermore, if the 2.4 arithmetic control IC is provided with a data setting circuit, it becomes possible to dynamically change the table in the external memory.

(Margin below) [Example code] An embodiment of the present invention will be described below.

First, a first embodiment of an arithmetic control IC according to the present invention will be described.

FIG. 1 shows the configuration of an arithmetic operation control IC according to the first embodiment.

The illustrated example is an example in which the arithmetic control IC according to the present invention is applied to an information processing device or the like, in which one memory is used as a buffer memory and a table to perform a plurality of arithmetic processes.

In the figure, 100 indicates an arithmetic control IC, and 101 is a bus, which connects the arithmetic control IC 100 to other circuits (not shown), a main memory, a CPU, etc. 102 is a random access memory that is used only by the arithmetic control IC, can be written and read in synchronization with the operation clock of the arithmetic control IC, and is directly connected to the arithmetic control IC without a bus. (hereinafter referred to as ``RAM'').

Among the arithmetic control ICs, 103 is a control circuit that collectively controls the arithmetic control ICs. Reference numeral 104 denotes an arithmetic circuit that actually performs a first arithmetic operation that requires a buffer memory, which is a function of the arithmetic control IC. Reference numeral 105 denotes an arithmetic circuit that actually performs a second arithmetic operation that requires an arithmetic table memory, which is a function of the arithmetic control IC. 106 is a data setting circuit for loading table data into the RAM 102 when the RAM 102 is used as a table; 107 is a RAM
When using 102 as a buffer memory, or as a RAM
an address counter that controls an address when loading table data to 102;

108.109.110.111.112 is a selector for selecting data.

Next, the operation of the arithmetic control IC according to the first embodiment will be explained.

First, a case will be described in which the calculation control IC 100 executes the first calculation requiring the buffer memory IJ.

First, when a CPU or the like issues an instruction to perform a first operation to the control circuit 103 via the bus 101, the control circuit 103 activates the operation circuit 104.

Arithmetic circuit 104 performs arithmetic processing on data input via bus 101 .

If it is necessary to buffer intermediate values generated during the processing, the arithmetic circuit 104 issues a write enable signal to RA and M2O3 through the selector 110 to set them in the write state.

Further, subsequently, the address counter 107 is activated. Next, data to be buffered is sequentially written to the address specified by the address counter 107 through the selector 111 into the RAM 102 through the selector 112.

Further, when reading buffered data, the arithmetic circuit 104 activates the address counter 107 and sequentially reads the written data according to the address indicated by the address counter 107.

Then, when the final result of the calculation process is obtained, selector 1
08 to the bus 101.

In the above arithmetic processing, the control circuit 103 selects the select 9
The process is controlled by operating 108.109.110.111.112.

Next, a case will be described in which the calculation control IC 100 executes a second calculation that requires table calculation.

First, similarly to the first operation, when an instruction to perform the second operation is issued to the control circuit 103, the control circuit 103 sends table data necessary for the operation processing to the data setting circuit 106. An instruction is issued to load the file into the RAM 102.

In response to this, the data setting circuit 106 activates the address counter 107, similar to the first calculation, and
According to the data input through 01, table data is written through the selector 112 to the address of the RAM 102 indicated by the address counter.

Next, the control circuit 103 instructs the arithmetic circuit 105 to start up.

The activated arithmetic circuit 105 performs arithmetic processing on data input via the bus 101.

When the calculation process requires calculation using the calculation table, the input data is inputted to the address of the RAM 102 through the selector 111.

Then, according to the previously written table data, a calculation result corresponding to the input data is output from the RAM 102 and input to the calculation circuit 105.

Based on the calculation result, the calculation circuit 105 further performs calculation, and finally outputs the final calculation result to the bus 101 through the selector 108.

Through the processing of the arithmetic circuit 105, the control circuit 103 selects the selectors 108.109.110.111.112.
Control processing by manipulating .

As explained above, according to the first embodiment, an arithmetic control IC that performs a plurality of arithmetic operations can be realized by using one random access memory as a buffer memory and an arithmetic table.

Next, a second embodiment of the arithmetic control IC according to the present invention will be described.

FIG. 2 shows the configuration of the calculation control IC according to this embodiment.

The illustrated example is an example in which the arithmetic control IC according to the present invention is applied to an information processing device or the like, in which one memory is used as a plurality of operation tables to perform a plurality of arithmetic processes.

In the figure, 101 and 102 indicate a bus and a RAM, respectively, as in the first embodiment.

200 indicates an arithmetic control IC.

In the arithmetic control IC, 103 is a control circuit, and 2
01 is a data setting circuit for loading table data into the RAM 102, and 202 is an arithmetic circuit that actually performs a first arithmetic operation, which is a function of the arithmetic control IC.

203 is an arithmetic circuit that actually performs the second arithmetic operation, which is a function of the arithmetic control IC.

Both arithmetic circuits 202 and 203 perform arithmetic operations using arithmetic tables.

204 and 205 are selectors.

Next, the operation of the arithmetic control IC according to the second embodiment will be explained.

First, a case will be described in which the calculation control circuit 200 executes the first calculation.

As in the first embodiment, when an instruction to perform the first operation is issued to the control circuit 103, the control circuit 103 activates the data setting circuit 201.

The activated data setting circuit 201 creates table data based on the data input from the bus 101. In this case, the data setting circuit 201
04, the address of the RAM 102 and write data are specified at the same time.

Next, the control circuit 103 activates the arithmetic circuit 202.

The activated arithmetic circuit 202 performs arithmetic processing on data input via the bus 101 .

When the calculation process requires calculation using the calculation table, input data is inputted to the address of the RAM 102 through the selector 204.

Then, according to the previously written table data, a calculation result corresponding to the input data is output from the RAM 102 and input to the calculation circuit 105.

Based on the calculation result, the calculation circuit 202 further performs calculation, and finally outputs the final calculation result to the bus 101 through the selector 205.

On the other hand, when the calculation control IC 200 performs the second calculation,
The control circuit 103 switches the selectors 204 and 205 to execute a second calculation requiring a different calculation table according to the same procedure as the first calculation.

As described above, according to the embodiment of Mizuo 2, it is possible to realize an arithmetic control IC that uses one memory as a plurality of arithmetic tables and performs a plurality of arithmetic processes.

Note that when the arithmetic control IC includes a plurality of arithmetic circuits that require buffer memory, it is provided with a selector that selects data to be buffered by the arithmetic circuits as necessary. R the data to ring
By storing the information in AM, it is possible to realize an arithmetic control IC that can use one memory as a buffer for a plurality of arithmetic operations executed by a plurality of arithmetic circuits.

Next, a third embodiment of the arithmetic control IC according to the present invention will be described.

FIG. 3 shows the configuration of the calculation control rc according to the third embodiment.

The illustrated example is an example in which the arithmetic control IC is an image processor, and one memory directly connected to the circuit is used for multiple purposes such as a buffer memory for 90° image rotation and an image density conversion table. This is an example of how it can be used.

In the figure, 101 and 102 indicate a bus and a RAM, respectively, as in the first embodiment.

Reference numeral 300 indicates an image processor which is an arithmetic control IC according to the third embodiment.

In the image processor 300, 103 is a control circuit; 301 is an input data conversion circuit that converts transmitted data input from a bus into data suitable for processing; 3;
02 is an output data conversion circuit that converts processed data into data suitable for output.

303 is an address counter that manages addresses in the row direction when the memory is used as a buffer memory for 90° rotation, 304 is an address counter that manages addresses in the column direction, and 305 is the address and input indicated by the address counters 303 and 304. A selector selects one of the addresses designated by the data conversion circuit and designates the address of the RAM 102, and 306 is an inverter that inverts the signal.

307 and 308 are OR circuits.

Next, the operation of the image processor according to the third embodiment will be explained.

First, a case will be described in which the present image processor performs 90@ rotation processing on an image.

FIG. 4 shows the relationship between the RAM storage area and address counters 303 and 304 according to the third embodiment.

In addition, in the present third embodiment, 90' rotation processing means 1
It is assumed that the image is rotated by 90 degrees in blocks divided by addresses of 6×16 bit width.

It is also assumed that address counters 303 and 304 are each 16-bit counters.

First, as in the first embodiment, when a command to perform a 90'' rotation is issued to the control circuit 103 via the bus, the control circuit issues a write enable signal to the RAM 102 and sets it to the write state. do.

Next, the control circuit 103 fixes the row/column signal to lH1 and outputs the address counter 304 through the OR circuit 308.
Input the enable signal to.

On the other hand, the address counter 303 is counted up through the OR circuit 307 by the carry of the address counter 304.

Therefore, in this case, address counter 304 becomes the lower bit and address counter 306 becomes the upper bit.

That is, it is output from the input data conversion circuit.

Image data for each pixel is passed through a selector 305 controlled by a control circuit 103 to an address counter 3.
03,304, the RA shown in Figure 4 is added to the specified address.
It will be written one line at a time on M.

Next, when reading out an image, the matrix signal is l L +
Fixed to.

In this case, the relationship between address counters 303 and 304 is reversed from that at the time of writing, with address counter 303 serving as the lower bit and address counter 304 serving as the upper bit.

Therefore, when the address counters 303 and 304 read out the data written in the RAM 102 according to the address outputted via the selector 305, the fourth
The data is read out one column at a time on the memory shown in the figure.

Therefore, in the relationship between write order and read order,
The image has been rotated by 90''.

The output data conversion circuit 302 outputs the image data read from the RAM 102 to the bus 101.

Next, a case will be described in which the image processor performs image density conversion processing.

When a command to perform image density conversion is issued, the control circuit 10
3 inputs the table data input from the bus 101 to the address counter 3 via the input data conversion circuit 301.
03 and 304 and write them into the RAM 102.

Next, image data to be actually subjected to density conversion is taken into the input data conversion circuit 301 from the bus 101.

Data for density conversion is stored in the RAM via the selector 305.
102 address line.

Then, data corresponding to the input density value outputted from the RAM is taken into the output data conversion circuit 302, and the data taken in by the output data conversion circuit is converted into a form suitable for transmission and outputted to the bus 101.

Therefore, according to the third embodiment, an image processor can be realized in which one memory directly connected to one circuit can be used as a buffer memory for 90@ image rotation and an image density conversion table. Note that other conversion processing such as gamma conversion can be similarly implemented.

As explained above, according to the embodiments of the present invention,
A plurality of arithmetic circuits of an arithmetic control IC and one memory are directly connected by controlling selectors of data lines, address lines, and write enable lines.

In other words, it is possible to realize an arithmetic control IC that controls a single memory as a table or buffer memory for multiple arithmetic processes, so there is no need to connect a unique memory to each arithmetic circuit, so there are fewer external pins and the board without getting too big,
Since memory directly connected to multiple operations can be used, efficient operation control can be achieved.

In the third embodiment, if the number of bins of the arithmetic control IC is sufficient, two RAMs are provided and the rotation buffer memory is configured as a double buffer to speed up the 90° rotation process. In this case, the density conversion table may be provided in one of the RAMs.

Further, if the table data used for calculation is fixed, the data setting circuit is not necessary, and the memory may be a ROM.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide an arithmetic control IC that can realize a plurality of arithmetic operations that require tables and buffers provided in memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the arithmetic control IC according to the first embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the arithmetic control IC according to the second embodiment of the present invention, and FIG. FIG. 4 is a block diagram showing the configuration of an arithmetic control IC according to a third embodiment of the present invention. FIG. 4 is an explanatory diagram showing the relationship between the storage area of the RAM and the address counter according to the third embodiment. 100...Arithmetic control IC1101...Bus, 102
...RAM, 103...Control circuit, 104...Arithmetic circuit, 105...Arithmetic circuit, 106...Data setting circuit, 107...Address counter, 108...Selector, 109... selector, 110... selector, 111... selector, 112... selector, 20
0... Arithmetic control IC1201... Data setting circuit,
202... Arithmetic circuit, 203... Arithmetic circuit, 204
...Selector, 205...Selector, 300...
Image processor, 301... Input data conversion circuit, 302... Output data conversion circuit, 3o3... Address counter, 3o4... Address counter, 305
... Selector, 306 ... Inverter, 307 ・
OR circuit, 308-OR circuit. Figure 4 Applicant: Hitachi, Ltd. Agent/Patent Attorney Tomi 1) Axis row address

Claims (1)

[Claims] 1. A plurality of arithmetic circuits that perform arithmetic operations;
An arithmetic control IC characterized by comprising a selector circuit selectively connected to an external memory. 2. A plurality of arithmetic circuits that perform arithmetic operations using an arithmetic table provided in an external memory, an address terminal to the external memory, and a data input terminal from the external memory that connects to data input to two or more of the arithmetic circuits. and a selector circuit that selectively connects data output from one of the two or more arithmetic circuits to an address terminal for the external memory.
. 3. The arithmetic control IC according to claim 2, wherein the external memory is a rewritable memory, and includes a data setting circuit that outputs data of an arithmetic table used by the two or more arithmetic circuits, and a data setting circuit. The selector circuit includes an address generation circuit that generates an address for storing table data to be output, and a data output terminal to an external memory that is connected to the data output from the data setting circuit. An arithmetic control IC, wherein data output from one of the arithmetic circuits or an address output generated by an address generation circuit is selectively connected to an address terminal connected to the external memory. 4. Using an external memory as a data buffer, connect to a plurality of arithmetic circuits that perform arithmetic operations, an address terminal to the external memory, a data output terminal to the external memory, and data input to two or more of the arithmetic circuits. a selector circuit selectively connecting a data input terminal from an external memory and a data output from one of the two or more arithmetic circuits to a data output terminal to the external memory; and an address generation circuit that outputs an address of an external memory, which stores output data of the above arithmetic circuits or reads input data to the two or more arithmetic circuits, to an address terminal for the external memory. Arithmetic control IC. 5. One or more first type calculation circuits that perform calculations using a calculation table provided in an external memory, and one or more second type calculation circuits that perform calculations using the external memory as a data buffer.
from an external memory connected to the first type arithmetic circuit, the address terminal to the external memory, the data input to the one or more first type arithmetic circuits, and the data input to the one or more second type arithmetic circuits. a data input terminal, and an address of an external memory for storing output data of the one or more second type arithmetic circuits;
or an address generation circuit that selectively outputs an address of an external memory from which input data to the one or more second type arithmetic circuits is read, and one or more of the one or more first type arithmetic circuits. Data output from the circuit, or
A selector circuit selectively connects the address generated by the address generation circuit to the address terminal for the external memory, and data to the external memory connectable to the data output from the one or more second type arithmetic circuits. An arithmetic control IC characterized by having an output terminal. 6. The arithmetic control IC according to claim 5, wherein the external memory is a rewritable memory, and a data setting circuit that outputs table data used by the one or more first type arithmetic circuits to the external memory. , data output from any one of the one or more first type arithmetic circuits;
or a second selector circuit that selectively connects the data output from the data setting circuit to a data output terminal to an external memory;
The address of an external memory that stores the output data of the second type arithmetic circuit, or the address of an external memory that reads the input data to the one or more second type arithmetic circuits, or the data setting circuit outputs. An arithmetic control IC characterized by selectively outputting an address of an external memory storing table data. 7. The arithmetic control IC according to claim 5 or 6, wherein the first type arithmetic circuit performs image density conversion processing, and the second type arithmetic circuit performs 90° rotation processing of the image. Characteristic calculation control IC. 8. Used by the arithmetic control IC according to claim 1, 2, 3, 4, 5, 6, 7 or 8, and the arithmetic circuit of the arithmetic control IC.
A memory that stores two or more calculation tables, a memory that is used as a data buffer for two or more calculation circuits, or a memory that stores one or more calculation tables and that is used as a data buffer for one or more calculation circuits. An information processing device characterized by: