JPH0454994B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a MOS transistor having a network structure.

[Background technology]

When using a MOS transistor for power control, the withstand voltage (breakdown voltage) between source and drain
A high BV _DS is desirable, and a low on-resistance R _ON is desirable. In a vertical N-channel MOS transistor, the breakdown voltage is mainly determined by the specific resistance value ρ _N- and the thickness t _N- of the N ^- layer in the drain region, and in order to increase the breakdown voltage, both the specific resistance value and the thickness must be adjusted. It needs to be bigger. However, in this case, the on-resistance inevitably increases.

Therefore, it is necessary to minimize the on-resistance within the range that provides the target withstand voltage, or conversely, maximize the withstand voltage within the range that provides the target on-resistance. Various transistor structures and transistor arrangements have been proposed.

One of these is the so-called mesh structure shown in Figure 1. This one is N ⁺
An N ^- layer is formed on the surface of the shaped substrate to form the drain region 1.
A gate electrode 2 is formed in a lattice shape on the front side of the gate electrode 2 as shown by diagonal broken lines in FIG.
Source regions 3 are formed in portions corresponding to the mesh. The gate electrode 2 is covered with an oxide film 4,
A drain electrode 6 is formed on the back surface of the N ⁺ layer of the drain region 1, on which the source electrode 5 is formed. In the figure, 7 represents a cell.

The channel width W is proportional to the length of the outer periphery of the cell per unit area. Therefore, according to this structure, the transistor density can be increased and the channel width W can be increased. As the channel width increases, the W/L value (L is the channel length) increases, and the on-resistance decreases.

By the way, if the cell size is Ls and the cell spacing is _L.sub.G , then in the above mesh structure, as the transistor density is increased, the cell spacing _L.sub.G becomes smaller. Therefore, the area of the portion of the drain region 1 through which electrons flow decreases, and the resistance of the N ⁻ layer increases. This causes an increase in the on-resistance, so as long as the structure shown in FIG. 1 is used, there is a limit to increasing the transistor density and reducing the on-resistance.

[Purpose of the Invention] Therefore, the present invention provides a vertical MOS for power control.
An object of the present invention is to provide a novel mesh structure transistor in which on-resistance does not increase even when the transistor density is increased.

[Disclosure of the invention]

In order to achieve the above object, this invention
In a MOS transistor, the drain region is formed by forming an N ^- layer on the surface side of an N ⁺ type substrate.
A P region is formed in a lattice shape on the surface portion of the N ⁻ layer, and an N ⁺ layer for a source region is formed in a lattice shape along the lattice shape on the surface portion of the P region. The gate electrode is installed in the mesh area with an insulating film in between, and the end of the gate electrode is located above the surface of the P region between the N ^- layer and the N ⁺ layer. Features.
This will be described in detail below based on drawings showing examples thereof.

As shown in Figure 2, the MOS according to this invention
In the type transistor, an N ^- layer is formed on the surface side of an N ⁺ type silicon single crystal substrate, and a drain region 11 is configured. N ^- of drain region 11
A P region 17 is formed in a square lattice shape on the surface portion of the layer, and an N ⁺ layer 12 for a source region is formed in a square lattice shape along the lattice shape on the surface portion of the P region 17. , a square gate electrode 14 covered with a SiO ₂ oxide film 13 is placed in the area corresponding to the mesh, as shown by the diagonal broken line in Figure A, that is, the end of the electrode is located in the P region between the N ^- layer and the N ⁺ layer. 17
It is placed above the surface. Although not shown, each gate electrode is connected to an external terminal by a suitable wiring method. The surface and gaps of the oxide film surrounding each gate electrode are covered with a source electrode 15, while a drain electrode 16 is formed on the back surface of the N ⁺ layer in the drain region 11. In the figure, 17 represents a P region surrounding the source region 12.

In this transistor, electrons are transferred to the source electrode 1
5→lattice-shaped source region (N ⁺ ) 12→channel (P)→square drain region (N ⁻ , N ⁺ )→drain electrode 16.

〔Effect of the invention〕

As can be seen from this structure, in order to increase the transistor density in this MOS transistor, it is sufficient to increase the ratio of cell spacing to cell size L _G /L _S . Even if this is done, the cell interval L _G does not become smaller. Therefore, the transistor density can be increased without increasing the drain resistance, and therefore the W/L value can be increased.

Conventionally, since the cell shape was square, the P layer was formed in the N layer in the cell portion as shown in FIG. That is, convex spherical PN junctions 8 are formed at the four corners of the cell. This spherical contact is similar to other
The withstand voltage is lower than that of PN junctions (cylindrical or planar), which has been an obstacle to achieving high withstand voltage. However, according to the configuration of the present invention described above, since the P region 17 surrounding the source region 12 is formed in a lattice shape, such a convex spherical surface junction does not occur. In this respect as well, the MOS transistor of the present invention is advantageous in obtaining a high breakdown voltage.

Length of outer periphery per unit area (channel width W
is proportional to this) is the longest triangle has,
The more polygonal the shape, the shorter it becomes. In this sense, a hexagonal cell (with a gate electrode in a hexagonal lattice) was not necessarily effective in conventional structures. However, according to the present invention, as shown in FIG. 4, the P region 17 is formed in a hexagonal lattice shape, and therefore the source region is formed in a tortoiseshell lattice shape, and the hexagonal gate electrode 14 is formed in the mesh. By being arranged as shown by the diagonal broken line, the effective drain area can be increased, and the on-resistance does not increase.

[Brief explanation of the drawing]

FIG. 1a is a plan view of a conventional square mesh structure MOS transistor, FIG. 1b is a sectional view taken along the line - in FIG. 1a, and FIG. 2b is a sectional view taken along the - line in FIG. 2a, FIG. 3 is a perspective view showing the PN junction surface of the conventional example, and FIG. 4 is a hexagonal mesh structure MOS type according to the present invention. FIG. 2 is a plan view of a transistor. 11...Drain region, 12...Source region,
13... Oxide film, 14... Gate electrode, 17...
cell.

Claims (1)

[Claims] 1 The surface side portion of the N ⁺ type substrate is formed as an N ⁻ layer to constitute a drain region, the P region is formed in a lattice shape on the surface portion of the N ⁻ layer, and the lattice shape is formed on the surface portion of the P region. for the source area along
The N ⁺ layer is formed in a lattice shape, and the gate electrode is placed in the mesh portion of the lattice via an insulating film, and the end of the gate electrode is on the surface of the P region between the N ^- layer and the N ⁺ layer. A MOS type transistor installed above.