JPH0455587U - - Google Patents
Info
- Publication number
- JPH0455587U JPH0455587U JP9887190U JP9887190U JPH0455587U JP H0455587 U JPH0455587 U JP H0455587U JP 9887190 U JP9887190 U JP 9887190U JP 9887190 U JP9887190 U JP 9887190U JP H0455587 U JPH0455587 U JP H0455587U
- Authority
- JP
- Japan
- Prior art keywords
- under test
- ram
- write
- signal output
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第１図及び第２図は、本考案の一実施例を示す
構成ブロツク図、第３図はグラウンドバウンスと
言われる現象の説明図である。
１……被試験用ＲＡＭ、２……書き込み読み出
し制御部、３……アドレス信号出力部、４……デ
ータ線負荷制御部、５……波形記録部。
1 and 2 are block diagrams showing an embodiment of the present invention, and FIG. 3 is an explanatory diagram of a phenomenon called ground bounce. DESCRIPTION OF SYMBOLS 1... RAM under test, 2... Write/read control section, 3... Address signal output section, 4... Data line load control section, 5... Waveform recording section.
Claims (1)
データの書き込み及び読み出しを実行する書き込
み読み出し制御部と、 この書き込み読み出し制御部が出力するレベル
指示信号に従つて前記被試験用ＲＡＭに与えるア
ドレス信号のレベルを可変するアドレス信号出力
部と、 前記被試験用ＲＡＭのデータ線に書き込み読み
出し制御部が出力する指示信号に従つて電流ソー
スを接続するデータ線負荷制御部と、 被試験用ＲＡＭ内の出力波形を記録する波形記
録部と を備えたＲＡＭ試験装置。 (2) アドレス信号出力部に代えて、被試験用Ｒ
ＡＭに与えるライト信号のレベルを可変にするラ
イト信号出力部を設けると共に、 被試験用ＲＡＭのデータ線を電源レベルにプル
アツプする抵抗を設けた請求項(1)記載のＲＡＭ
試験装置。[Scope of claim for utility model registration] (1) Any address for the RAM under test,
a write/read controller that writes and reads data; an address signal output unit that varies the level of an address signal applied to the RAM under test in accordance with a level instruction signal output from the write/read controller; A RAM equipped with a data line load control section that connects a current source to the data line of the RAM under test according to an instruction signal output by a write/read control section, and a waveform recording section that records the output waveform in the RAM under test. Test equipment. (2) In place of the address signal output section, use the R under test
The RAM according to claim (1), further comprising a write signal output section that varies the level of the write signal applied to the AM, and a resistor that pulls up the data line of the RAM under test to a power supply level.
Test equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9887190U JPH0455587U (en) | 1990-09-20 | 1990-09-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9887190U JPH0455587U (en) | 1990-09-20 | 1990-09-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0455587U true JPH0455587U (en) | 1992-05-13 |
Family
ID=31840373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9887190U Pending JPH0455587U (en) | 1990-09-20 | 1990-09-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0455587U (en) |
-
1990
- 1990-09-20 JP JP9887190U patent/JPH0455587U/ja active Pending
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