JPH0456414A - phase synchronization signal generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase synchronization signal generator that generates a clock signal synchronized with a synchronization trigger signal.

[Prior Art] ■In a video memory that stores a video signal in a semiconductor memory, in order to create a sampling clock synchronized with the horizontal synchronization signal of the input video signal, conventionally a third
A phase synchronized signal generator with the configuration shown in the figure is used. This operation will be explained using FIG. Now, input terminal 15 is “
When the level is “H”, the NAND gate 16 and the delay time τ
A square wave pulse with a period of 2 is outputted to the output terminal of the inverter 18 by the delay line 17 having a period of 2.

When a synchronization trigger signal is inputted to the input terminal 15 to reach the "L" level for a certain pulse width T from the front edge (or rear edge) of the horizontal synchronization signal (Fig. 4 (1)), the NAND gate is activated during the time T1. The output of inverter 16 is forced to the "H" level, and therefore the output terminal of the inverter 18 becomes the "L" level (FIG. 4 (2)). Next, the input terminal 15 is T.

Immediately after the lapse of time, the output of the NAND gate 16 changes to the "L" level (therefore, the output terminal of the inverter 18 goes to the "H" level) and outputs a square wave pulse with a period of 2τ again. Therefore, if T1 and τ are constant, a sampling clock signal with period 2 synchronized with the horizontal synchronizing signal is output to the output terminal of the inverter 18.

■On the other hand, in a laser beam printer (hereinafter referred to as LBP), a laser beam is scanned and irradiated onto a photosensitive drum at a constant speed, and printing toner adheres only to the irradiated area, which is then transferred to the paper surface. To form text and image information on paper, a beam detect (BD) mirror is mechanically placed at a constant position between the photosensitive drum and the laser beam scanning direction, and the laser beam is always placed at the BD mirror position. In order to generate a synchronized clock signal that modulates the laser beam by converting the reflected light into an electrical pulse signal (BD pulse) using a phototransistor, a conventional phase synchronization signal generation method as shown in Fig. 5 is used. using a device.

The output of the NFV crystal oscillator 19, which oscillates at n times the synchronous clock frequency fv, is input to the clock inputs of a 1/n counter 20, a D-type flip-flop (DFF) 21, and a 1/N counter 22. The BD pulse is input to the data input of the leaf F21, and the Q output of the DFF21 is input to the reset input of the l/n counter 20 and the reset input of the 1/N counter 22, respectively. Also, the Q output of the 1/N counter 22 is DF
It is input to the reset input of F21. Now BD pulse is “
When changing from “L” to “H” level, maximum delay time 1/nf
At v, the Q output of the DFF 21 becomes "H" level, resetting the 1/n counter 20 and changing the 1/N counter 22 from the reset state to the count mode. When the output clock signal of the NFV crystal oscillator 19 is counted by N, 1/
The N counter 22 becomes "H" level, resets the DFF 21, and puts the 1/n counter 20 into counting mode. On the other hand, the 1/N counter 18 is reset and the DFF 21
from reset mode to operation mode and wait for the next BD pulse. In this way, the output of the 1/n counter 20 becomes
A synchronous clock signal synchronized with the BD pulse is output.

The amount of synchronization jitter between the BD pulse and the VIDEO clock signal is 1/nfv.

[Problems to be Solved by the Invention] However, the above conventional example had the following drawbacks.

In the case of the above example 0, the frequency accuracy of the synchronized clock signal is determined by the delay time τ of the delay line 17, so
Not only does it require expensive components such as a pulse delay line, but it also requires adjustment by selecting taps and the like. Furthermore, since the threshold level of the NAND gate 16 is generally not stable depending on temperature and power supply voltage, it has been difficult to ensure frequency stability.

In the case of the above example (2), the amount of synchronous jitter of the synchronous clock signal is determined by the counter value n of the 1/n counter 20, and L
In the BP system, n=8 is generally set so that there is no problem with the print data on the paper. 240DP
I (For Dot/1nchJ machine, the synchronization clock frequency is ~1.55MHz, and for the original clock signal ~
It uses a 12.4MHz crystal oscillator. Future LB
There is a demand for higher resolution for P as well, and 600DPI (Do
t/1nch) machine, the synchronization clock frequency is proportional to the square of the resolution ratio from the horizontal stripe resolution balance condition, and is approximately 9.7MHz (= 1.55MHz x (600/24
0) and 2), and the original clock frequency reaches ~77.6 MHz, requiring a high-frequency crystal oscillator. In this case, even crystals can no longer oscillate without using overtones, making it difficult to put them into practical use due to the need for adjustment and cost.

Also, countermeasures against unnecessary radiation in high-frequency oscillation were a major problem.

An object of the present invention is to provide a phase synchronization signal generator that solves the above-mentioned problems.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a phase synchronized signal generator that generates a synchronized clock signal synchronized with a synchronized trigger signal, which has a variable frequency that can stop oscillation according to the synchronized trigger signal. an oscillator, a reference oscillator having the same oscillation frequency as a synchronized clock signal, and a first phase comparison for controlling the oscillation frequency of the variable frequency oscillator by comparing the phases of an output signal of the reference oscillator and an output signal of the variable frequency oscillator. The vessel and
a continuous phase variable device that outputs a signal for continuously varying the phase of the output signal of the reference oscillator with respect to the output signal of the variable frequency oscillator when the first phase comparator is not operating; and a second phase comparator that compares the phases of the output signal of the frequency oscillator and the output signal of the continuous phase variable oscillator and synchronizes the output signal of the continuous phase comparator with the output signal of the variable frequency oscillator. Features.

Furthermore, the present invention provides a phase synchronization signal generator that generates a synchronization clock signal synchronized with a synchronization trigger signal, which can start oscillation in synchronization with the synchronization trigger signal, and includes an oscillation means for generating a first clock signal, and a reference frequency and a phase variable means that changes the phase of the second clock signal based on the first clock signal and outputs it as a synchronized clock signal.

[Function] According to the present invention, the oscillation means generates the first clock signal in synchronization with the synchronization trigger signal, and the phase variable means generates the second clock signal from the reference oscillator based on the first clock signal. It changes the phase and outputs it as a synchronous clock signal. This reference oscillator is realized using an element capable of generating a highly accurate clock signal, such as a crystal oscillator. Therefore, a stable synchronous clock signal that is synchronized with the synchronous trigger signal can be obtained.

The oscillation means is preferably a variable frequency oscillation means whose frequency is variable based on a control signal, and the variable frequency oscillation means generates a first clock signal controlled to have the frequency of the second clock signal, as will be described later. The generation starts in synchronization with the synchronization trigger signal. Thereafter, as described above, the phase variable means changes the phase of the second clock signal based on the first clock signal, and outputs it as a synchronized clock signal after reaching a desired phase.

Note that the frequency of the first clock signal may be controlled to match the frequency of the second clock signal based on the first clock signal (or synchronous clock signal) in parallel with the output of the synchronous clock signal.

[Embodiment] Fig. 1 is an overall block diagram showing an embodiment of the present invention.
The figure is a timing chart explaining the operation.

The differential oscillation output A of the variable frequency oscillator (VCO) 2 can be stopped by the synchronization trigger signal shown in FIG. 2 2) formed by the rising edge of the external synchronization signal shown in FIG. and the phase comparator lO.

On the other hand, 90
The output signal C delayed (-90° phase) is
60°) is input to the variable block 9. variable block 9
The output differential bear F is input to the phase comparator 5 and the phase comparator 10 as well as to the gate circuit 14.

The switching control circuit 100 controls two switches (SW) as described later based on the human output signal information of the variable frequency oscillator 2.
6. Control ON and OFF of 12 (so that when one is ON, the other becomes OFF).

The phase comparator 5 stores the phase error voltage between the two input differential bears in the capacitor C1 only when the constant current source 7 is supplied with the switch (SW) 6 set to 0lln, and the error current generating circuit 4 generates the reference voltage. Vllll! An error current is generated between the current and the constant current source 3, and the oscillation frequency of the variable frequency oscillator 2 is controlled by the sum with the constant current source 3. When SW6 is set to F, the variable frequency oscillator 2 maintains the previous oscillation frequency.

Only when the switch 5W (12) is turned on and the constant current source 13 is supplied, the phase comparator 10 accumulates the phase error voltage of the two differential bears input to the capacitor C2, and the phase difference is ±90°. It is stable only when .

Phase error voltage output of phase comparator 10 and reference voltage VREF
2 is input to the all-phase variable block 9, and the phase of the output differential bear F is controlled to be 190' phase with respect to the output differential bear A of the variable frequency oscillator 2. Also 5
When W12 is OFF, the phase of the previous output differential bearer F is held. A trigger signal 26 for determining a phase variable region is manually input to all phase variable blocks 9.

FIG. 6 shows the variable frequency oscillator 2, with transistor Q2
HO2, Ql-Ql3, Q6-Q7. Q3-Q
IO, Q4-Qll, Ql2-Ql4, resistance R1←
If the conditions of input terminal 1 are set so that R2, R4-R5 are balanced and Q8 is turned on, the amplitude from between the emitter of Ql and the emitter of 013 is ΔV=R1・I2
The differential output bare A is oscillated. This becomes the oscillation frequency, which can be controlled by the phase error current ΔI based on the phase error voltage of the phase comparator 5. Input a synchronization trigger signal with the sole pulse width (tz-t+) from the front edge of the external synchronization signal to input terminal 1.The base of Q5 is in positive phase and the base of Q8 is in reverse phase. input.

The control voltages of SW6 and 5W12 from the switching control circuit 100 change in level at tl and t6, as shown in FIG. 2 (4). Before time t, the phase of differential output bear F of all phase variable block 9 is in a hold state (because 5
Because W12 is OFF and the phase comparator IO is not operating). At this time, the oscillation frequency of the output signal of the variable frequency oscillator 2 is stabilized in a state in which the phase is synchronized with a certain phase signal (differential output bare F) formed from the output signal of the crystal oscillator 8.

At time t1, the synchronous trigger signal goes to "H" level, the variable frequency oscillator 2 stops oscillating, SW6 is activated, the phase comparator 5 stops operating, and the hold voltage accumulated in the capacitor C1 causes tl The control current (T0 + ΔI
)It has become. On the other hand, the SWI 2 is turned on, and the phase comparator 10 starts comparing the phases of the differential output bear A of the variable frequency oscillator 2 and the differential output bear F of the all-phase variable block 9. At time t2, the variable frequency oscillator 2 starts oscillating again. At this time, the oscillation frequency is very close to the frequency of the crystal oscillator 80, and there is a phase shift that does not cause any problem until time t (on the contrary, if t6 is changed from time t1, variable frequency oscillator 2
). Furthermore, since t6 is set outside the effective screen of the image memory and LBP, it can be set in a relatively short time, and this requirement can be met. At time t6, variable frequency oscillator 2 is again controlled to be phase synchronized with the output signal of crystal oscillator 8. Since the control during this time is mostly just phase control, the control is sufficiently completed within the period of the synchronization signal, and it is possible to wait for the next synchronization signal.

The crystal oscillator 8 has a configuration shown in FIG. 7, including an input bias circuit 70, a 90° phase shifter 71, and an inverting comparator 7.
It consists of 2. Output of inverting comparator 72 (
The output of Q29/emitter) is fed back to the input terminal (Q17/base) provided with a capacitor C5 serving as a 90° phase shift via a crystal xl whose load capacitance is indicated by 06. The DC voltage of Q17/base is fixed at (■2°VB) by the input bias circuit 70, and the DC voltage of each of Q17/emitter (B output) and Q22/emitter (C output) is set to ■2.Output terminal Two types of oscillating sine wave outputs with a 90° phase difference are obtained.

The configuration of the total phase variable block 9 consists of a variable phase region selector 24 and a continuous phase variable device 25, as shown in FIG. FIG. 9 shows a circuit example of the continuous phase variable device 25. Sine waves having phases different by 90 degrees are input to the differential signal bears G and H. The phase error voltage from the phase comparator 10 and the reference voltage V*EF2 are input to E. Transistor Q34-
Q35. Q36-Q37. Q3g -039, Q4
0 HQ41. 044-045. Q42-Q43
, Q46-Q47. Q48→Q49, resistor R30-
R31, R32-R33, R34HR35, R36→R
37←R38-R39, R40HR41 is assumed to be balanced. Now, assuming that the potential difference between pair E is zero, a sine wave having the same phase as input differential pair G and an amplitude mainly determined by resistors R30 and R32 (R31 and R33) is output to differential output pair F.

However, when a potential difference occurs between the pair of E, this causes the collector current ratio of transistors Q38 and Q39 to become IQ3-z-/
IQ-zo and IQ-/-/IQ4.10 and IQ44
/C/IQ45/C, so at this time when the collector currents of transistors Q47 and 046 are unbalanced, input terminal G and input are connected to terminal H.
The vector addition phase of the two signals input manually becomes the phase of the differential output pair F. Therefore, as shown in 1) to 4) in Fig. 10, ±45°45° is applied around the phase of the differential input bear G.
Continuously variable.

For this purpose, assuming that the input levels of G and H are equal, R
34/R32<Ill/IIO. Further, as shown in FIGS. 1) to 4), by changing the type (90° or Oo) and polarity of the differential input pair G and H, the entire phase (0° to 360'') can be varied.

Next, the operation of the variable phase region selector 24 for selecting the phase variable regions 1) to 4) in FIG. 1O will be explained. 1) and 2) in FIG. 11 are signals that are binarized using the output signals B and C of the crystal oscillator 8, each with a phase delay of 45 degrees (-45 degrees). 3) to 6) are time t3 in the pulse of 3) in FIG. 2 of the differential output pair A of the variable frequency scattered oscillator 2.
4 shows four conditions for the phase for the crystal oscillation output. The differential output pair A of the variable frequency oscillator 2 is latched with the signals 1) and 2) in FIG. 11, and the two data outputs are latched at time t3 and held until t3 of the next cycle. Depending on the content of this data, in the case of Figure 11 3), the middle tube 1
O Select the area in Figure 4), Figure 11 4) Middle part 10 Figure 1),
Figure 11 5), Figure 11 2), Figure 11 6) #10
3) to ensure phase synchronization operation by the phase comparator IO.

The phase synchronization operation of the variable phase differential output pair F with respect to the differential output pair A of the variable frequency oscillator 2 can be sufficiently completed by time t6, and the differential ratio of the differential output pair A is 190° (or +9
0#, however, either one is determined), the differential output pair F is phase-controlled. At this time, the time t of the differential output bare A
The phase shift from 2 is minute, and therefore the phase of the synchronous trigger signal is maintained.

After time t6, the phase comparator 10 holds the phase output state immediately before 5W12 was turned off until time t1 of the next cycle. The time from time L6 to 1+ of the next cycle must necessarily include the effective screen area and is a relatively long time, but the phase comparator IO performs phase control, and like frequency control, there is no phase shift. Since there is no accumulation, LBP
Even with a relatively long synchronization period of ~2 rns as in the system, the phase shift can be suppressed to a non-problematic level by circuit design that compensates for leakage current mainly due to the base current of the transistor to the capacitor C2. Therefore, a signal whose phase is synchronized with the synchronization trigger signal is outputted to the differential output bare F during the period from time t6 to the next synchronization trigger signal.

Therefore, the gate circuit 14 is connected to the control input terminal 23 (Fig. 2 4).
When controlled by inputting the pulse of , the gate circuit 14 outputs a synchronous clock signal synchronized with the external synchronization signal (FIG. 2 1)) as shown in FIG. 2 5). Note that since time t6 is the time when the differential output bear A of the variable frequency oscillator 2 is counted from time t2, the edges of the output of the gate circuit 14 and the differential output bear F do not overlap at time t6 ( (phase synchronized to ±90°). Therefore, unnecessary and unstable pulses are not output from the gate circuit 14, and pixel misalignment in the LBP system and image memory can be prevented.

[Effects of the Invention] As explained above, according to the present invention, not only can the reference oscillator be made to have the same frequency as the synchronization clock signal, but also the amount of synchronization jitter can be suppressed from becoming a discrete large value.
Therefore, it is possible to provide a phase synchronization signal generator particularly suitable for severe requirements such as a video memory in which analog quantities are sampled and input to the memory.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a phase synchronization signal generator according to an embodiment of the present invention, Fig. 2 is a diagram showing a timing chart explaining the operation of the embodiment, and Fig. 3 is a diagram of a phase synchronization signal generator of the first conventional example. Figure 4 shows a timing chart explaining the operation of the conventional example; Figure 5 shows the phase synchronized signal generator of the second conventional example; and Figure 8 shows the phase synchronization signal generator of the second conventional example. Circuit diagram, Figure 9 is a circuit diagram of a continuous phase variable device, Figure 1θ is a vector diagram for explaining the operation of the circuit in Figures 8 and 9, and Figure 11 is a circuit diagram for explaining the operation of the circuit in Figure 8. FIG. 3 is a diagram showing a timing chart for explanation. 2... Variable frequency oscillator, 4... Phase error current forming circuit, 5.10... Phase comparator, 8... Crystal oscillator, 9... Full phase converter, 24... Variable phase Region selector, 25... Continuous phase variable device. Figure 1 t+t2ts+ta ↑6 Figure Figure Figure Figure Figure 10

Claims (1)

[Claims] 1) A phase synchronized signal generator that generates a synchronized clock signal synchronized with a synchronized trigger signal, including a variable frequency oscillator whose oscillation can be stopped by the synchronized trigger signal, and a variable frequency oscillator that has the same oscillation frequency as the synchronized clock signal. a reference oscillator; a first phase comparator that controls the oscillation frequency of the variable frequency oscillator by comparing phases of an output signal of the reference oscillator and an output signal of the variable frequency oscillator; and the first phase comparator stops operating. a continuous phase variable device that outputs a signal for continuously varying the phase of the output signal of the reference oscillator with respect to the output signal of the variable frequency oscillator when the output signal of the variable frequency oscillator is a second phase comparator for phase-comparing the output signal of the continuous phase comparator with the output signal of the variable frequency oscillator to phase-synchronize the output signal of the continuous phase comparator with the output signal of the variable frequency oscillator. 2) In a phase synchronization signal generator that generates a synchronized clock signal synchronized with a synchronization trigger signal, the oscillation means can start oscillation in synchronization with the synchronization trigger signal, and includes an oscillation means for generating a first clock signal and a second clock signal having a reference frequency. Phase synchronization signal generation characterized by having a reference oscillation means for generating a clock signal, and a phase variable means for changing the phase of the second clock signal based on the first clock signal and outputting it as a synchronization clock signal. vessel. 3) In the phase synchronization signal generator according to claim 2,
The oscillation means is a variable frequency oscillation means that generates a first clock signal whose frequency is variable based on a control signal, and the oscillation means is a variable frequency oscillation means that generates a first clock signal whose frequency is variable based on a control signal. A phase synchronization signal generator comprising a control means for outputting the control signal. 4) In the phase synchronization signal generator according to claim 3,
a first operation mode in which the control means controls the frequency of the first clock signal and the phase variable means outputs the synchronized clock signal; and A phase synchronization signal generator characterized by having a second operation mode in which the output of the clock signal is started in synchronization with the synchronization trigger signal, and a phase change operation of the second clock signal is performed by the phase variable means. .