JPH0456473B2 - - Google Patents
Info
- Publication number
- JPH0456473B2 JPH0456473B2 JP57035802A JP3580282A JPH0456473B2 JP H0456473 B2 JPH0456473 B2 JP H0456473B2 JP 57035802 A JP57035802 A JP 57035802A JP 3580282 A JP3580282 A JP 3580282A JP H0456473 B2 JPH0456473 B2 JP H0456473B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- diffusion
- impurity concentration
- substrate
- base region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
- H10D62/152—Source regions of DMOS transistors
- H10D62/153—Impurity concentrations or distributions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/393—Body regions of DMOS transistors or IGBTs
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は絶縁ゲート型電界効果トランジスタ
に係り、特に２重拡散絶縁ゲート型電界効果トラ
ンジスタの改良構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an insulated gate field effect transistor, and more particularly to an improved structure of a double diffused insulated gate field effect transistor.
一般的な２重拡散絶縁ゲート型電界効果トラン
ジスタ（以降DMOSと略記する）における素子
の構造を第１図に示す。図において、１はＮ型シ
リコン基板のドレイン層で、前記基板の一方の主
面から１つの拡散マスクを用いてＰ型およびN+
型不純物を各１回ずつ拡散する、いわゆる２重拡
散によつてベース領域２、ソース領域３が形成さ
れており、これで生ずる拡散差、特に基板の主面
に沿う部分がチヤンネル領域となる。そして、基
板の主面に沿う部分での不純物プロフアイルを第
２図に示す。DMOSにおいてはベース領域とド
レイン領域とでは前者の方が不純物濃度が大きい
ため、ドレイン電圧を増加すると生ずる空乏層は
主としてドレイン層の方へ伸び、ベース領域への
伸びは小さいため、パンチスルーによる耐圧劣化
を防ぐことができる。したがつて、高耐圧化を計
るためにはベース領域の全不純物量QBはできる
だけ大きい方がよい。しかし、一方で絶縁ゲート
型電界効果トランジスタ（以下IG−FETと略記
する）においては、ベース領域が反転してチヤン
ネルとなるしきい値電圧（以下VTHと略記する）
を適当な値にする必要があることからベース領域
の最大不純物濃度Na（max）を一定以上大きくす
ることは許されない。そこで、ソース領域の拡散
深さもおのずからきまつてくる。すなわち、第３
図に示すように、ソース（N+）領域の拡散の進
行にともなつて既に拡散されているベースＰ領域
を基板表面から押し込んで行くもので、この拡散
の進行によつてベース領域の不純物濃度は逐次低
下して行くため、その値がNa（max）に達するま
で拡散を停止できない。すなわち、第２図に示し
たベース領域の不純物プロフアイルになるまでソ
ース領域の拡散は続けられることになる。
FIG. 1 shows the structure of a typical double diffused insulated gate field effect transistor (hereinafter abbreviated as DMOS). In the figure, 1 is a drain layer of an N-type silicon substrate, and P-type and N +
The base region 2 and the source region 3 are formed by so-called double diffusion in which type impurities are diffused once each, and the difference in diffusion caused by this, particularly the portion along the main surface of the substrate, becomes a channel region. FIG. 2 shows the impurity profile along the main surface of the substrate. In DMOS, the impurity concentration is higher in the base region and drain region, so when the drain voltage is increased, the depletion layer that is generated mainly extends toward the drain layer, and the extension toward the base region is small, so the breakdown voltage due to punch-through Deterioration can be prevented. Therefore, in order to achieve high breakdown voltage, the total amount of impurities Q B in the base region should be as large as possible. However, on the other hand, in an insulated gate field effect transistor (hereinafter abbreviated as IG-FET), the threshold voltage (hereinafter abbreviated as V TH ) at which the base region is inverted and becomes a channel is high.
Since it is necessary to set Na(max) to an appropriate value, it is not allowed to increase the maximum impurity concentration Na(max) in the base region beyond a certain level. Therefore, the diffusion depth of the source region naturally becomes stricter. That is, the third
As shown in the figure, as the diffusion of the source (N + ) region progresses, the base P region that has already been diffused is pushed in from the substrate surface, and as the diffusion progresses, the impurity concentration in the base region increases. Since the value gradually decreases, diffusion cannot be stopped until its value reaches Na(max). That is, the diffusion of the source region continues until the impurity profile of the base region as shown in FIG. 2 is achieved.
叙上の背景技術にはNa（max）を一定値以下に
抑え、かつQBを大きくするのに好適する手段が
開発されておらず、解決する手段が強く要望され
ていた。
In the background art described above, a means suitable for suppressing Na(max) below a certain value and increasing Q B has not been developed, and a means to solve the problem has been strongly desired.
この発明は背景技術の問題点に対する解決手段
として２重拡散絶縁ゲート型電界効果トランジス
タの改良構造を提供する。
The present invention provides an improved structure for a double diffused insulated gate field effect transistor as a solution to the problems of the background art.
この発明はIG−FETのソース領域が２回の拡
散によつて形成された低不純物濃度層と高不純物
濃度層とからなると同時に低不純物濃度層で隣接
のベース領域に接していることを特徴とするIG
−FETである。
This invention is characterized in that the source region of the IG-FET is composed of a low impurity concentration layer and a high impurity concentration layer formed by two diffusions, and at the same time, the low impurity concentration layer is in contact with the adjacent base region. IG to do
−FET.
以下この発明を１実施例のIG−FETにつき図
面を参照して詳細に説明する。第４図はソース領
域１３の拡散形成を２回に行なう例を示す。すな
わち、低表面濃度で深い拡散を施してベース領域
に接する第１ソース領域層１３ａと、前記第１ソ
ース領域層１３ａ形成についてこれよりも充分に
高表面濃度でかつ、浅い拡散を施して第１ソース
領域層に接する第２ソース領域層１３ｂを備え
る。このIG−FETの基板の主面からの深さ方向
の不純物プロフアイルを第５図に太い実線１０Ｓ
−１０Ｂ−１０Ｄで示す。なお、図中に細線（実
線）で示す不純物プロフアイル線９Ｓ−９Ｂ−９
Ｄ（９Ｄと１０Ｄとは一致している）は従来例を
示す第２図を添えて相違点を明確にする。この発
明の実施例ではソース領域の拡散が２回に行なわ
れているため、図中破線で示す第１ソース拡散の
プロフアイル１０S′によつて、ベースの拡散不純
物濃度の特に基板表面に近い部分が拡散孔端から
の距離によつて低減される。すなわち、図の１点
鎖線で示された当初のベース領域濃度が２点鎖線
によつて示される如く傾斜が緩められている。こ
のため、Na（max）を得るための第２ソース拡散
１０Ｓは基板表面に近く（浅く）で達成できる。
Hereinafter, the present invention will be explained in detail with reference to the drawings for one embodiment of the IG-FET. FIG. 4 shows an example in which the diffusion formation of the source region 13 is performed twice. That is, the first source region layer 13a in contact with the base region is formed by performing deep diffusion with a low surface concentration, and the first source region layer 13a is formed by performing shallow diffusion with a sufficiently higher surface concentration than the first source region layer 13a. A second source region layer 13b in contact with the source region layer is provided. The impurity profile in the depth direction from the main surface of the substrate of this IG-FET is shown in Figure 5 as a thick solid line 10S.
-10B-10D. In addition, the impurity profile line 9S-9B-9 shown as a thin line (solid line) in the figure
D (9D and 10D are the same), the difference will be clarified with reference to FIG. 2 showing a conventional example. In the embodiment of the present invention, the diffusion of the source region is performed twice, so that the first source diffusion profile 10S' shown by the broken line in the figure reduces the diffusion impurity concentration of the base, especially in the portion near the substrate surface. is reduced by the distance from the diffusion hole end. That is, the slope of the initial base region concentration indicated by the dashed line in the figure has been loosened as indicated by the dashed double dotted line. Therefore, the second source diffusion 10S for obtaining Na(max) can be achieved close to (shallowly) the substrate surface.
次の実施例は第６図に示すように、ソース領域
１３とベース領域１２とをいずれも２回の拡散に
よつて形成するもので、不純物濃度のプロフアイ
ルは第７図に実線で示す如くなる。この実施例は
第７図に示した従来の不純物濃度のプロフアイル
を示す破線と比較して効果が明確に認められる。 In the next embodiment, as shown in FIG. 6, both the source region 13 and the base region 12 are formed by twice diffusion, and the impurity concentration profile is as shown by the solid line in FIG. Become. The effect of this example can be clearly seen when compared with the broken line showing the conventional impurity concentration profile shown in FIG.
この発明にかかるDMOSには次にあげる利点
がある。その一つはソースの拡散を２回以上行な
うことによりチヤンネルの全不純物量を増大さ
せ、ドレイン電圧印加時のベース層への空乏層の
伸びを小さくすることにより高耐圧化が可能にな
るとともにチヤンネル長をさらに短かくすること
により相互コンダクタンスを増大させることがで
き、大電流化が可能になる。
The DMOS according to this invention has the following advantages. One of them is to increase the total amount of impurities in the channel by diffusing the source two or more times, and by reducing the extension of the depletion layer to the base layer when drain voltage is applied, it is possible to achieve high breakdown voltage and to increase the channel impurity content. By further shortening the length, the mutual conductance can be increased, making it possible to increase the current.
次にはチヤンネル部のベース不純物濃度プロフ
アイルは（特にNa（max）付近）が均一化される
ためにVTHの制御性がよくなる。 Next, since the base impurity concentration profile in the channel portion (especially near Na(max)) is made uniform, controllability of V TH becomes better.
第１図は従来のDMOSの要部の断面図、第２
図はDMOSの不純物プロフアイルを示す線図、
第３図はDMOSの拡散形成を不純物プロフアイ
ルにつき説明するための線図、第４図以降はこの
発明にかかり、第４図は第１実施例のDMOSの
要部の断面図、第５図は第４図のDMOSの不純
物のプロフアイルを示す線図、第６図は第２実施
例のDMOSの要部の断面図、第７図は第６図の
DMOSの不純物プロフアイルを示す線図である。
１２……ベース領域、１３……ソース領域。
Figure 1 is a cross-sectional view of the main parts of a conventional DMOS, Figure 2
The figure shows a diagram showing the impurity profile of DMOS,
Fig. 3 is a diagram for explaining DMOS diffusion formation with respect to impurity profile, Fig. 4 and subsequent figures relate to the present invention, Fig. 4 is a cross-sectional view of the main part of the DMOS of the first embodiment, Fig. 5 is a diagram showing the impurity profile of the DMOS in Fig. 4, Fig. 6 is a cross-sectional view of the main part of the DMOS of the second embodiment, and Fig. 7 is a diagram showing the impurity profile of the DMOS in Fig. 6.
FIG. 3 is a diagram showing the impurity profile of DMOS. 12...base area, 13...source area.
Claims (1)
主面に選択的に２重拡散形成された基板と反対導
電型のベース領域と、前記ベース領域内に基板と
同導電型のソース領域とを具備した絶縁ゲート型
電界効果トランジスタにおいて、ソース領域が２
回の拡散によつて形成された低不純物濃度層と高
不純物濃度層とからなる同時に低不純物濃度層で
隣接のベース領域に接していることを特徴とする
絶縁ゲート型電界効果トランジスタ。1 The semiconductor substrate is the drain region, and 1 of this substrate
In an insulated gate field effect transistor comprising a base region of a conductivity type opposite to that of the substrate which is selectively double-diffused on the main surface, and a source region of the same conductivity type as the substrate within the base region, the source region is 2
1. An insulated gate field effect transistor comprising a low impurity concentration layer and a high impurity concentration layer formed by double diffusion, and the low impurity concentration layer is in contact with an adjacent base region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57035802A JPS58153368A (en) | 1982-03-09 | 1982-03-09 | Insulated gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57035802A JPS58153368A (en) | 1982-03-09 | 1982-03-09 | Insulated gate field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58153368A JPS58153368A (en) | 1983-09-12 |
| JPH0456473B2 true JPH0456473B2 (en) | 1992-09-08 |
Family
ID=12452045
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57035802A Granted JPS58153368A (en) | 1982-03-09 | 1982-03-09 | Insulated gate field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58153368A (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5950561A (en) * | 1982-09-17 | 1984-03-23 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS60196974A (en) * | 1984-03-19 | 1985-10-05 | Toshiba Corp | Conduction modulation type mosfet |
| JPH01128576A (en) * | 1987-11-13 | 1989-05-22 | Matsushita Electron Corp | Vertical mos field effect transistor |
| JPH01164068A (en) * | 1987-12-21 | 1989-06-28 | Hitachi Ltd | Semiconductor device |
| JPH0783121B2 (en) * | 1988-09-02 | 1995-09-06 | 三菱電機株式会社 | Field effect semiconductor device |
| JP2508818B2 (en) * | 1988-10-03 | 1996-06-19 | 三菱電機株式会社 | Method for manufacturing semiconductor device |
| ATE154469T1 (en) * | 1990-02-01 | 1997-06-15 | Fred L Quigg | MOSFET STRUCTURE WITH REDUCED CONTROL ELECTRODE CAPACITY AND MANUFACTURING METHOD |
| US5179032A (en) * | 1990-02-01 | 1993-01-12 | Quigg Fred L | Mosfet structure having reduced capacitance and method of forming same |
| US5121176A (en) * | 1990-02-01 | 1992-06-09 | Quigg Fred L | MOSFET structure having reduced gate capacitance |
| JP6469795B2 (en) * | 2017-09-21 | 2019-02-13 | アルディーテック株式会社 | Insulated gate field effect transistor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1133869B (en) * | 1979-10-30 | 1986-07-24 | Rca Corp | MOSFET DEVICE |
| JPS57134855U (en) * | 1981-02-17 | 1982-08-23 |
-
1982
- 1982-03-09 JP JP57035802A patent/JPS58153368A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58153368A (en) | 1983-09-12 |
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