JPH0456576A - image display device - Google Patents

Abstract

PURPOSE:To display a personal computer signal and a TV signal with one control circuit by providing a PLL circuit able to change an oscillating frequency depending on a horizontal scanning frequency and a data setting circuit to vary various setting to the display device. CONSTITUTION:A horizontal synchronizing signal H is fed to a PLL oscillation circuit 50' and a data setting circuit 61 controls a frequency division ratio of the PLL oscillation circuit 50' to obtain a reference clock required for a television pattern or a personal computer pattern or the like and the reference clock is fed to a horizontal counter 51 and a sampling clock generating circuit 70. The horizontal counter 51 is counted by using the reference clock generated by the PLL oscillation circuit 50' to generate the reference pulse for a pulse generating circuit 53. Then a sampling clock generating circuit 70 frequency- divides the reference clock to generate a sampling clock depending on the horizontal effective scanning period of the input video signal and the horizontal picture element of the picture display device. Thus, a picture of the television program and a picture of a personal computer or the like are displayed by one control circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a method for deflecting electron beams for each section in the vertical and horizontal directions when a screen is divided into a plurality of sections in the vertical and horizontal directions. The present invention relates to a device that displays a plurality of lines and displays an image as a whole.

2. Description of the Related Art The basic structure of a conventional image display device will be explained with reference to FIG.

This display element consists of a back electrode 1, a line cathode 2 as a beam source, a beam extraction electrode 3, a beam flow control electrode 4, a focusing electrode 5, a horizontal deflection electrode 6, a vertical deflection electrode 7, and a screen in order from the back to the anode side. A plate 8, etc. are arranged, and these are housed inside the vacuum container.

A line cathode 2 serving as a beam source is stretched horizontally so as to generate an electron beam distributed linearly in the horizontal direction.
A plurality of line cathodes 2 are further provided at intervals in the vertical direction (in this description, only seven line cathodes 2A to 2G are shown). In this configuration, the spacing between the line cathodes is 31 m and the number of line cathodes is 30, and the number of the line cathodes is 2i to 27. The distance between the line cathodes cannot be freely increased, but is regulated by the distance between the vertical deflection electrode 7 and the screen 8, which will be described later. As the configuration of these line cathodes 2, 10
An oxide cathode material is applied to the surface of a tungsten rod with a diameter of ~30 μm. As will be described later, the line cathodes are controlled to sequentially emit electron beams from the upper line cathode 2a to the lower line cathode 27 for a fixed period of time. The back electrode 1 has the function of suppressing the generation of electron beams from line cathodes other than the corresponding line cathode, and also has the function of pushing the electron beams only toward the anode. Although the vacuum container is not shown in FIG. 2, it is also possible to adopt a structure in which the back electrode 1 is used to integrate the back electrode 1 with the vacuum container. The beam extraction electrode 3 is a conductive plate 11 having a large number of through holes 10 provided at regular intervals in the horizontal direction facing each of the line cathodes 2a to 27.
The electron beam emitted from the line cathode 2 is extracted through the through hole 10 thereof. Next, the control electrode 4 is composed of a vertically long conductive plate 15 having a through hole 14 at a position facing each of the line cathodes 2a to 27, and a plurality of conductive plates 15 are arranged horizontally in parallel at predetermined intervals. ing. In this configuration, 120 conductive plates 15a to 15n for control electrodes are provided (only 8 are shown in FIG. 2).

The control electrode 4 controls the amount of passage of each of the electron beams divided horizontally by the beam extractor 8i3 in accordance with the picture elements of the video signal and in synchronization with the timing of horizontal deflection, which will be described later. . Is the convergence electrode 5 a control?
The electron beam is focused by a conductive plate 17 having a through hole 16 at a position opposite to each through hole 14 provided in the 1llt8i14.

The horizontal deflection electrode 6 is composed of a plurality of conductive plates 18' arranged vertically along both horizontal sides of the through hole 16, and each conductive plate has a horizontal deflection plate. Voltage is applied.

The electron beams for each picture element are each deflected in the horizontal direction, and sequentially irradiate the R, G, and B phosphors on the screen 8 to emit light. In this configuration, each electron beam is deflected by two trios. The vertical deflection electrode 7 is composed of a plurality of conductive plates 1919' arranged horizontally at vertically intermediate positions of the through holes 16, and a vertical deflection voltage is applied to the vertical deflection electrode 7, which deflects the electron beam vertically. deflected in the direction. In this configuration, the electron beam generated from one line cathode is deflected by eight lines in the vertical direction by a pair of electrodes 19 and 19'. Then, by the vertical deflection electrode 7 composed of 31 pieces, 30 lines corresponding to each of the 30 line cathodes
Pairs of vertical deflection conductors are constructed to draw 240 horizontal scanning lines in the vertical direction on the screen 8.

As explained above, in this configuration, a plurality of rods 6 for horizontal deflection and a plurality of poles 7 for vertical deflection are arranged in a comb shape. Furthermore, by setting the distance to the screen 8 longer than the distance between the horizontal and vertical deflection electrodes, it becomes possible to irradiate the screen 8 with the electron beam with a small amount of deflection.

This allows for horizontal and vertical deflection of the electrode path. I can do that.

As shown in FIG. 2, the screen 8 is constructed by coating the back surface of a glass plate 21 with phosphor 20 in a striped pattern. Although not shown, a metal back and carbon are also coated. The phosphor 20 is located in one through hole 1 of the control electrode 4.
By deflecting the electron beam passing through the phosphor 4 in the horizontal direction, two trios of phosphor pairs of the three colors R, C, and B are irradiated, and the phosphors are applied vertically in stripes.

In FIG. 2, the broken lines drawn on the screen 8 indicate the vertical divisions displayed corresponding to each of the plurality of line cathodes 2, and the two-dot chain lines indicate the sections corresponding to each of the plurality of control electrodes 4. Figure 3 shows an enlarged view of one section divided by dashed lines and two-dot chain lines, showing the horizontal divisions to be displayed. ,
The B phosphor has a width of 8 lines in the vertical direction.

In this example, the size of one section is 1 in the horizontal direction and 3 in the vertical direction.
It is.

Although the phosphors of each of the three colors R, G, and B are shown in stripes in Figure 3, they may also be arranged in a delta pattern.
However, when arranged in a delta shape, it is necessary to apply horizontal and vertical deflection waveforms that are compatible with the arrangement.

In FIG. 3, for convenience of explanation, the aspect ratio is different from the image displayed on the actual screen.

In addition, in this configuration, two trios of R, G, and B phosphors are provided for one through hole 14 of the control electrode 40;
It may be composed of one trio or three or more trios. However, one trio or three or more trios of R, G, and B video signals are sequentially provided to the control electrode 4, and horizontal deflection must be performed in synchronization with this.

Next, the operation of the drive circuit for driving this display element is as follows.
This will be explained with reference to FIG. First, a driving portion that irradiates the screen 8 with an electron beam to display an image will be explained.

The power supply circuit 22 is a circuit for applying a predetermined bias voltage to each electrode of the display element. Apply the DC voltage of ■8.

Next, the line cathode drive circuit and deflection signal generation circuit will be explained. In FIG. 5, 50 is a reference oscillator, 51 is a horizontal counter, 52 is a vertical counter, 53 is a pulse generation circuit, 54 is a line cathode drive pulse generation circuit, 55 is a line cathode selection circuit, 56 is a line cathode drive circuit, and 57 is the deflection memory, 5
8 is a D/A converter, 60 is a cathode counter, and 61 is a data setting circuit.

The operation of the line cathode drive circuit and deflection signal generation circuit configured as described above will be explained with reference to FIGS. 5 and 6.

First, FIG. 5 shows a basic circuit diagram of a conventional line cathode drive circuit and deflection signal generation circuit, in which various pulses are generated by the pulse generation circuit 53 using the clock generated by the reference oscillator 50 and the horizontal synchronization signal H. The vertical counter 52 is operated using the output of one pulse (IH pulse) a and the vertical synchronization signal ■ during one horizontal scanning period,
The output of the vertical counter 52 is sent to a pulse generation circuit 53 and a line cathode drive pulse generation circuit 54. The cathode counter 60 receives the IH pulse a generated by the pulse generation circuit 53.
The number of lines is counted using this as a clock, and the number of lines that one wire cathode has is counted. The number of lines that one line cathode has can be arbitrarily set by changing the preset value of the cathode counter 60 using the data setting circuit 61 and the present pulse b. In the following description, it is assumed that the present embodiment is preset to count 9 lines. The line cathode driving pulse generating circuit 54 generates a pulse C for determining the start timing of the line cathode and a pulse d for selecting the line cathode and sends them to the line cathode selection circuit 55. The line cathode selection circuit 55 is composed of a simple shift register, and c
, d are applied to the input terminal and clock terminal of the shift register, respectively, and a line cathode drive pulse as shown in FIG. 6 is generated as the output of the shift register.

These outputs (I to M) are amplified by a line cathode drive circuit 56 and supplied to the line cathodes as drive signals (2A to 27), respectively. The deflection memory 57 reads out waveform data for vertical and horizontal deflection using the pulse e generated by the pulse generating circuit 53, and passes the data through the D/A converter 58 to generate a vertical deflection signal as shown in FIG. v, v' and horizontal deflection signal h' can be obtained.

The vertical deflection data is, for example, 9 for one line cathode.
The beam is deflected in stages, resulting in a total of 270 lines per field and 540 lines per frame (taking into account overscan).
It enables image display with different numbers of lines such as PAL, SECAM (TV system), etc. The vertical deflection data differs depending on the number of deflection stages, and by storing the data in different areas of the deflection memory, it can be easily switched by simply selecting the area.

Note that since the number of lines per line cathode can be changed freely, the above line cathode drive circuit can be used even in the case of image display devices having different numbers of line cathodes.

Next, the modulation control portion of the electron beam will be explained.

First, in Fig. 4, signal input terminals 23R, '23G2
The R, G, and B video signals applied to 3B are applied to 120 sample-and-hold circuit sets 31a to 31n. Each sample hold group 31a to 31n is R
It is composed of six sample and hold circuits: one for G1, one for Bl, one for R2, one for G2, and one for B2. The sampling pulse generation circuit 34 has a horizontal period (63,5μ
s) during the horizontal display period (approximately 50 μs), the 12
Each R1 of 0 set of sample hold circuits 31a to 31n
720 pieces (120x6) corresponding to sample and hold circuits for G2, B2, CI, Bl, and R2
The sampling pulses Ral to Rn2 are sequentially generated.

Six of the 720 sampling pulses are applied to each of the 120 sample-and-hold circuit sets 31a to 31n, so that each sample-and-hold circuit set has the following effects:
R1°Gl, Bl, R2, G2 . for each two picture elements when one line is divided into 120 pieces. Each B2 video signal is individually sampled and held. 120 sample-held pairs of R1, Gl, Bl, R2, G
2. The video signal of B2 is transferred to 120 sets of memories 32a to 32n by the pulse L after the sample hold for one line is completed.
are transferred all at once and held here for the next one horizontal scanning period. The held signals are applied to 120 switching circuits 35a-35n. switching circuit 35
a to 35n are R1, G1. Bl, R2, G2
．． B2 individual input terminals and a common output terminal that sequentially switches and outputs the switching pulses rl, gl, b1 .B2 applied from the switching pulse circuit 36. r2. g2. Switching is controlled simultaneously by b2.

The switching pulses rl, gl, bl, r2, g2
．． b2 divides each horizontal period into 6, and divides each horizontal period into 6 horizontal display periods/6
The switching circuits 35a to 35n are switched R1,
C1, Bl, R2, G2. The B2 video signals are time-divided and sequentially output, and supplied to the pulse width modulation circuits 37a to 37n.

The output of each switching pulse circuit 35a to 35n is 1
20 sets of pulse width variation 1jI (hereinafter referred to as PWM) circuit 3
7a to 37n, R1, Gl, Bl, R2゜G
2. The pulse width is modulated according to the magnitude of each B2 video signal and output. The outputs of the pulse width modulation circuits 37a to 37n are individually applied to the 120 conductive plates 15a to 15n of the control electrode 4 of the display element as control signals for modulating the electron beam.

Next, horizontal deflection and display timing will be explained. R1°G1. in the switching circuits 35a to 35n. 'B
1. R2, G2. B2 video signal switching and electron beams R1, Gl, Bl, R by the horizontal deflection drive circuit 41
2, G2. The timing and order of switching the horizontal deflection to the B2 phosphor are synchronously controlled so that they completely match. As a result, when the electron beam is irradiating the R1 phosphor, the irradiation amount of the electron beam is controlled by the R1 control signal, and the following Gl, Bl, R2, G2 . B2 is controlled in the same way, and R1 and GIB1 of each picture element are controlled in the same way.
, R2, G2. B2 The light emission of each phosphor is the R1 of that picture element,
G1. B1. R2, G2. Each picture element is controlled by the B2 video signal, and each picture element is displayed by emitting light according to the input video signal. Such control is executed for 120 sets (2 pixels each) for one line, and
An image of 240 picture elements per line is displayed, and images are further displayed on the screen 8 by sequentially processing the 240 lines of one field starting from the upper line. Furthermore, the above operations are repeated for each field of the input video signal, and a television signal or the like is displayed on the screen 8.

Incidentally, the basic clock necessary for this configuration is supplied from a pulse generation circuit 39 shown in FIG. 4, and the timing is controlled by a horizontal synchronizing signal H1 and a vertical synchronizing signal (2).

Problems to be Solved by the Invention However, although the control circuit for the image display device described above is capable of handling video signals with different numbers of scanning lines (vertical scanning frequencies), it is possible to deal with video signals that differ significantly in the number of scanning lines (vertical scanning frequencies). It was not possible to display video signals such as personal computer signals and TV signals.

In view of the above-mentioned problems, the present invention provides a control circuit for an image display device that can be handled by changing the reference clock of the control circuit depending on the horizontal scanning frequency and controlling various settings from the outside. be.

Means for Solving the Problems In order to solve the above-mentioned problems, the image display device of the present invention includes a PLL (phased locked loop) circuit for generating a clock that is slightly different from the horizontal synchronization signal, and a It consists of a data setting circuit for changing various settings.

Effect of the Invention By having the above-described configuration, the present invention can display a personal computer signal and a TV signal using a single control circuit of an image display device.

Embodiment Hereinafter, an image display device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a basic drive circuit block diagram of an image display device in one embodiment of the present invention.

In FIG. 1, 50' is a PLL oscillator circuit that generates a clock longer than the horizontal synchronization signal H, 51 is a horizontal counter, 52 is a vertical counter, 53 is a pulse generation circuit, and 54 is a horizontal counter.
55 is a line cathode drive pulse generation circuit; 55 is a line cathode selection circuit;
56 is a line cathode drive circuit, 57 is a vertical/horizontal deflection memory, 58 is a D/A converter, 6o is a cathode counter, 61
70 is a data setting circuit, 70 is a sampling clock generation circuit, and 71 is a signal modulation circuit.

The operation of the image display device configured as described above will be described below with reference to FIG.

First, FIG. 1 shows the basic drive circuit of this image display device, in which a horizontal synchronizing signal H is applied to a PLL oscillation circuit 50', and a data setting circuit 61 controls the frequency division ratio of the PLL oscillation circuit 50'. As a result, a reference clock necessary for a television screen, a personal computer screen, etc. is obtained, and the reference clock is sent to the horizontal counter 51 and the sampling clock generation circuit 70. The horizontal counter 51 rotates the counter using the reference clock generated by the PLL oscillation circuit 50', and generates a reference pulse for the pulse generation circuit 53. The sampling pulse generation circuit 70 divides the frequency of the reference clock and generates a sampling clock determined by the horizontal effective scanning period of the input video signal and the horizontal picture elements of the image display device. Therefore, the clock oscillated by the PLL oscillation circuit 50' is an integral multiple of the sampling clock.

Next, the pulse generation circuit 53 generates pulses for controlling the signal modulation circuit 71, pulses for accessing the vertical and horizontal deflection memories 57, and clocks for the vertical counter 52 and the cathode counter 60.

Conventionally, two control circuits were required to display a TV or PC on a single image display device, but now the control circuit changes the reference clock proportionally depending on the horizontal scanning frequency of the input video signal and outputs control from the control circuit. By changing the pulse in proportion to the horizontal scanning frequency, a single control circuit can display on a television, personal computer, etc.

By providing an effect circuit of the invention and a data setting circuit for changing various settings, it is possible to display a personal computer signal and a TV signal using a single control circuit of an image display device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the basic drive circuit of an image display device according to an embodiment of the present invention, FIG. 2 is an exploded perspective view showing the basic structure of the image display device, and FIG. 3 is an enlarged view of the screen. FIG. 4 is a basic drive circuit diagram of an image display device, FIG. 5 is a block diagram of a conventional line cathode drive circuit and deflection signal generation circuit, and FIG. 6 is a timing diagram of various waveforms. 2...Line cathode, 3...Beam extraction electrode, 4...Beam regulation゛Ill! Extreme, 5...
...Focusing electrode, 6...Horizontal deflection electrode, 7.
... Vertical deflection electrode, 8 ... Screen plate, 20 ... Phosphor, 22 ... Power supply circuit, 23 ... Input terminal, 26. ...Line cathode drive circuit, 31a-31n...Sample hold circuit, 32a-32n...-Memory, 35a-3
5n...Switching circuit, 36...
Switching pulse generation circuit, 37...PWM
Circuit, 39...Pulse generation circuit, 40...
... Deflection signal generation circuit, 41 ... DMA controller, 42 ... Deflection memory, 43 ...
・D/A converter, 50'...PLL oscillation circuit,
51...Horizontal counter, 52...Old...Vertical counter, 53...Pulse generation circuit, 54...
... Line cathode drive pulse generation circuit, 55... Line cathode selection circuit, 56... Line cathode drive circuit, 57.
... Deflection memory, 58 ... D/A converter, 60 ... Cathode counter, 61 ...
- Data setting circuit, 70...Sampling clock generation circuit, 71...Signal modulation circuit. Name of agent: Patent attorney Shigetaka Awano

Claims (1)

[Claims] The screen surface is divided into a plurality of sections in the vertical and horizontal directions, an electron beam is generated for each section, and each electron beam is deflected in the vertical and horizontal directions for each section. This is a device that displays images on the computer, and is equipped with a PLL circuit that changes the oscillation frequency of the clock depending on the input video signal, and a data setting circuit that changes settings depending on the input video signal, and can handle PC signals, TV signals, etc. with one control circuit. An image display device characterized by displaying an image.