JPH0457295A - Electrically writable/erasable memory circuit - Google Patents

Abstract

PURPOSE:To enable efficient backup and to shorten time for it by continuously writing continuous data blocks while successively selecting plural writable/ erasable memories. CONSTITUTION:When address signals A6 and A7 are inputted through address control lines 21 and 22 from a CPU, an address decoder 15 decodes these signals and prepares a chip select signal 17 for designating one of EEPROM 11-14. Thus, the EEPROM 11 is selected and the data of 64 bytes are continuously written. Next, when the CPU sets the address signals A6 and A7 to L and H respectively, the address decoder 15 changes the signal 17 to L and holds the other signals at H. Thus, the EEPROM 12 is selected and the data are continuously written. Afterwards, the write operation is repeated similarly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory circuit, and relates to an electrically writable and erasable memory circuit used for various types of backup in digital communication and data transmission communication devices, for example.

[Conventional technology]

User-programmable read-only memory (F)
It's called ROM. ), electrically programmable and erasable memories (hereinafter referred to as EEPROMs) have come to be widely used. This EEPROM is a conventional erasable FR
Unlike OM (EPROM), it does not require ultraviolet light to erase and can be easily erased, so its use is expected to increase in the future, such as being used for backing up various information in communication devices that perform digital communication. Recently, control circuits and high voltage generation circuits necessary for writing and erasing are built into the device, making it possible to write and erase with the same timing as regular static random access memory (SRAM) using a single 5V power supply. There is. This EEP
In ROM, it takes a considerable amount of time to write inside the element, so in addition to writing and erasing in bytes, it is now possible to write and erase in consecutive pages of multiple bytes to achieve high speeds. The goal is to For example, a certain device is capable of writing and erasing 64 bytes of continuous data per page during one cycle IQms, making it possible to perform processing at several tens of times higher speed than conventional types.

[Problem to be solved by the invention]

In this way, recent EEFROMs have become capable of high-speed processing on a page-by-page basis, but due to the characteristics of the element, it is not possible to write the next page until one write cycle has elapsed. Ta.

FIG. 3 shows a conventional writing operation to an EEFROM. For example, the data write period t1 is 10m5.
Assuming that the memory circuit is configured with an EEPROM in which the write cycle t2 for each byte is 100 μs and the number of bytes per page k is 64 bytes, the time MT actually required to write data for one page is as follows (1) It becomes like the expression.

Tr = tz xk = 100 (μSol X64 [byte] = 6
．． 4 (msl...(1) However, the next page cannot be written until one write cycle 1 Qms has elapsed, so the time between writing one page and writing the next page is , there is a waiting time Tw as shown in equation (2) below.

T, = tl - T.

=3.6 [msl (2) Therefore, the time required to write 256 bytes of data, for example, is constrained by the data write cycle t1 as shown in the following equation (3).

10 (ms) x (256/64) = 40 [ms]
(3) This includes the waiting time Tw, which is originally a wasted time.

As described above, the conventional memory circuit using the EEFROM has a drawback that writing efficiency is low because there is a considerably long waiting time Tw in addition to the actual writing time.

SUMMARY OF THE INVENTION An object of the present invention is to provide an electrically writable and erasable memory circuit that can efficiently write data without waiting time.

[Means to solve the problem]

In the invention as claimed in claim 1, (i) a plurality of electrically programmable and erasable memories each capable of successively writing a predetermined number of bytes of data; and (ii) data from these electrically programmable and erasable memories. 1 item to be written
(1) electrically programmable and erasable memory selected by the electrically programmable and erasable memory selector;
The electrically writable and erasable memory circuit is provided with data writing means for continuously writing data by a predetermined number of bytes.

In the invention as claimed in claim 1, a plurality of electrically programmable and erasable memories capable of page writing are prepared, and each of these memories is sequentially and cyclically selected one by one to store a predetermined number of consecutive bytes of data. It is assumed that writing is performed so that the blocks are further consecutive to each other.

The invention according to claim 2 provides: (i) a plurality of electrically writable and erasable memory chips each having a page write mode in which data can be continuously written and erased for a predetermined number of bytes in a constant byte write cycle; , (ii) an address decoder that decodes a portion of a given address signal to create and output a chip select signal for sequentially and cyclically selecting the plurality of electrically programmable and erasable memory chips one by one. and (iii) data block writing in which data of a predetermined number of bytes is sequentially and continuously written as one block to each electrically programmable and erasable memory chip specified by the chip select signal output from this address decoder. an electrically programmable and erasable memory circuit.

In the invention as claimed in claim 2, a chip select signal is created by decoding a part of the address signal with an address decoder, and a plurality of electrically programmable and erasable memory chips are cyclically selected. Writing is performed on each memory chip so that consecutive data blocks of a predetermined number of bytes are further consecutive.

〔Example〕

The present invention will be described in detail with reference to Examples below.

FIG. 1 depicts an electrically programmable and erasable memory circuit in one embodiment of the present invention. This circuit has four EEPs that can write and erase pages in units of 64 bytes.
ROMs 1 to 14 are provided, and chip select signals 16 to 19 are inputted from the address decoder 15 to each chip select terminal C8.

This address decoder 15 is connected to an address line 21.2 from a central processing unit (CPU (not shown) of the main system).
Address signals As and At are inputted via the terminals 2 and 2, and one of the chip select signals 16 to 19 is generated and output based on the address signals As and At. Here, it is assumed that when the chip select signal becomes "L-level", the corresponding chip becomes active.

Further, each of the EEPROMs 1 to 14 is provided with a data terminal group of 8 bits and an address terminal group A of 15 bits. Among these, the data bus 24 from the main system (not shown) is branched into four and connected in parallel to the data terminal group of each EEPROM.
Backup data IOo-IOl is exchanged. On the other hand, the address bus 25 from the CPU is branched into four branches and connected in parallel to the address terminal group A of each EEPROM, and receives address signals A0 to A.

A6 to AH are inputted.

In this embodiment, in order to simplify the explanation, the so-called write enable signal used during writing is omitted; however, this signal causes the data bus 2 to
Of course, the directionality of the four directions can be switched.

The operation of the electrically programmable and erasable memory circuit configured as above will be explained with reference to FIG. Here, as in the conventional example, write cycle 1 (1 ms, byte write cycle 100 μs, E
The following description assumes that page writing is performed in units of 64 bytes to the EPROM.

When address signals A@, Aq are input from the CPU via the address control lines 21 and 22, the address decoder 1
5 decodes this and creates a chip select signal for designating one of the EEPROMs 11-14. For example, both 6 and A1 to the address signal *L s
When the signal is at the "L" level, the address decoder 15 changes the chip select signal 16 to "L" level and holds the others at "H" level.

As a result, the first EEPROMI 1 is selected, and 64 bytes of data are continuously written at a byte write cycle of 100 μs (FIG. 2a, period A).

The time Tr required for this is 6.4 as shown in equation (1).
It is ms.

Next, the CPU sends the address signals As and A, respectively.
When set to L''', #H11 level, the address decoder 15 changes the chip select signal 17 to the "L" level and holds the others at the "H" level.
EEPROMI 2 is selected, and 64 bytes of data are continuously written at a byte write cycle of 100 μs as before (period B in FIG. 2). The time required for this, T,
is also 5.4 ms.

Furthermore, the CPU sets the address signal All581 to “H”.
, "L" level, "H" level, and "H" level in sequence, the third and fourth EEPROM13.1
4 is selected, and 64 bytes of data are continuously written to each of them (Fig. 2 c, d).

When writing to the fourth EEFROM 14 is completed, C
The PU sets both address signals A6 and A1 to the "L" level again, and repeats the same write operation.

In this way, one of the four EEFROMs is selected cyclically, and for the selected EEFROM, 64
Byte page write operations are performed without waiting time.

For example, when writing 256 bytes of data, the time required for this is 25.6 ms, as shown in equation (4) below.

6, 4 [:ms] X (256/64) = 25.
6 [:=5) -- (4) Therefore, in this embodiment, writing is possible in about 40% shorter time than the conventional time required as shown in equation (3).

Note that in this embodiment, the byte write cycle was set to 100 μs, but if a memory chip with a smaller value is used,
Of course, the effect of time reduction becomes even more remarkable.

Further, in this embodiment, four EEFROMs are used, but the write cycle is 1. Byte write period t compared to
If 2 is much shorter, more memory chips can be used.

〔Effect of the invention〕

As explained above, according to the present invention, a plurality of electrically programmable and erasable memories capable of page writing are prepared, and these memories are sequentially selected so that consecutive data blocks of a predetermined number of bytes are further connected to each other. Since it is possible to write data continuously, there is no need to wait for the write waiting time as in the past (data can be written continuously. Therefore, efficient backup is possible and the time required for it can be shortened. effective.

[Brief explanation of the drawing]

1 and 2 are for explaining one embodiment of the present invention, of which FIG. 1 is a block diagram showing an electrically programmable and erasable memory circuit, and FIG. 2 is an electrical FIG. 3 is a timing diagram for explaining the operation of a conventional electrically programmable and erasable memory circuit.

Claims (1)

[Scope of Claims] 1) A plurality of electrically programmable and erasable memories each capable of continuously writing data for a predetermined number of bytes, and an object to which data is written from these electrically programmable and erasable memories. electrically programmable and erasable memory selection means that cyclically selects data one by one, and a predetermined number of bytes of data for each electrically programmable and erasable memory selected by the electrically programmable and erasable memory selection means. 1. An electrically programmable and erasable memory circuit, comprising: data writing means for continuously writing data. 2) A plurality of electrically programmable and erasable memory chips, each having a page write mode that allows data to be continuously written and erased for a predetermined number of bytes in a fixed byte write cycle, and a portion of a given address signal. an address decoder that generates and outputs a chip select signal for sequentially and cyclically selecting the plurality of electrically programmable and erasable memory chips one by one; and a chip select signal output from the address decoder. and a data block writing means for sequentially and continuously writing a predetermined number of bytes of data into each electrically programmable and erasable memory chip as one block. Possible memory circuit.