JPH0458007B2 - - Google Patents
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- Publication number
- JPH0458007B2 JPH0458007B2 JP58181715A JP18171583A JPH0458007B2 JP H0458007 B2 JPH0458007 B2 JP H0458007B2 JP 58181715 A JP58181715 A JP 58181715A JP 18171583 A JP18171583 A JP 18171583A JP H0458007 B2 JPH0458007 B2 JP H0458007B2
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- capacitance
- electro
- optical shutter
- ferroelectric substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/03—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels effect or Kerr effect
- G02F1/05—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels effect or Kerr effect with ferro-electric properties
- G02F1/0516—Operation of the cell; Circuit arrangements
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
Description
【発明の詳細な説明】
この発明は光シヤツタアレイ素子に関するもの
であり、特にその低容量化を図つたものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an optical shutter array element, and in particular is aimed at reducing the capacity thereof.
光シヤツタアレイの従来構造としては第1図に
示すようなものがある。 A conventional structure of an optical shutter array is shown in FIG.
図において、1は偏光子、2はPLZTのような
透明セラミクスよりなる電気光学効果を有する強
誘電体基板、3は検光子であり、強誘電体基板2
は偏光子1と検光子3間に配置されている。そし
て偏光子1と検光子3は光軸が直交するように配
置されている。強誘電体基板2の表面には、複数
の平行線状の電極4,5が一方側から他方側へ食
い込ませて互いに差し込んで状態で形成され、光
シヤツタアレイ素子が構成されている。この電極
4,5間に電圧を印加することによつて、電極
4,5間の領域において光が透過し、電圧の印加
を解除することによつて光を遮蔽することにな
る。 In the figure, 1 is a polarizer, 2 is a ferroelectric substrate made of transparent ceramics such as PLZT and has an electro-optic effect, 3 is an analyzer, and ferroelectric substrate 2
is arranged between the polarizer 1 and the analyzer 3. The polarizer 1 and the analyzer 3 are arranged so that their optical axes are perpendicular to each other. A plurality of parallel electrodes 4 and 5 are formed on the surface of the ferroelectric substrate 2 so as to be inserted into each other from one side to the other, thereby forming an optical shutter array element. By applying a voltage between the electrodes 4 and 5, light passes through the region between the electrodes 4 and 5, and by removing the voltage application, the light is blocked.
上記した強誘電体基板2について、その具体的
な構造を第2図に示す。 FIG. 2 shows the specific structure of the ferroelectric substrate 2 described above.
第2図に示した番号は第1図と対応しており、
図において、A領域が光シヤツタ部分に相当す
る。そして等価回路を第2図のB領域部分を拡大
した第3図にもとづいて示すと第4図のようにな
る。 The numbers shown in Figure 2 correspond to those in Figure 1.
In the figure, area A corresponds to the optical shutter portion. The equivalent circuit is shown in FIG. 4 based on FIG. 3, which is an enlarged view of area B in FIG. 2.
第4図において、容量C1とC2について説明す
ると次のとおりである。すなわち、容量C1は一
方側から他方側へ食い込ませて互いに差し込んだ
状態で形成した電極4,5間の容量で、この差し
込み領域は第2図のA領域に相当する光シヤツタ
アレイ素子の光スイツチングに関与する能動領域
である。また容量C2は同一方向から延びて形成
した電極、つまり電極4,4同志または電極5,
5同志間について、第2図のA領域を除いた引出
し部分間の容量である。 In FIG. 4, the capacitances C 1 and C 2 will be explained as follows. That is, the capacitance C1 is the capacitance between the electrodes 4 and 5 formed by inserting them into each other from one side to the other, and this insertion area is the optical switching area of the optical shutter array element corresponding to area A in FIG. It is an active area involved in In addition, the capacitance C 2 is formed by electrodes extending from the same direction, that is, electrodes 4 and 4, or electrodes 5 and 5.
This is the capacity between the drawer portions excluding area A in FIG. 2 for five comrades.
ここで、第3図、第4図の電極4,5のうち、
特に電極4a,5aについてみれば、電極4a,
5aの間の容量は、A領域の容量C1、電極4b
を介して生じる容量C1C2/(C1+C2)、電極5b
を介して生じる容量C1C2/(C1+C2)、および電
極4a,4b、電極5a,5bを除くその他の電
極4,5を介して生じる容量などが合成されたも
のである。 Here, among the electrodes 4 and 5 in FIGS. 3 and 4,
Especially when looking at the electrodes 4a and 5a, the electrodes 4a,
The capacitance between electrode 5a is the capacitance C 1 of area A, and the capacitance between electrode 4b
Capacitance C 1 C 2 /(C 1 +C 2 ) generated through electrode 5b
The capacitance C 1 C 2 /(C 1 +C 2 ) generated through the electrodes 4a, 4b and the capacitances generated through the other electrodes 4 and 5 other than the electrodes 5a and 5b are synthesized.
図示したような電極4,5の形成パターンによ
れば、電極4,5を同じ方向から延びて形成した
ものにくらべて、電極4,4同志、電極5,5同
志の間隔Dを秘録することができるため、容量
C2の値をある程度小さくすることができるため、
容量C2の値をある程度小さくすることができる。
これら容量C1,C2に関して言えば、電極4,5
の幅、電極4,5間の距離、電極4,5の引出し
部分の長さによつて変化するものの、概ね互いに
無視することができない程度の関係にある。 According to the formation pattern of the electrodes 4 and 5 as shown in the figure, the distance D between the electrodes 4 and 4 and between the electrodes 5 and 5 can be kept secret compared to the case where the electrodes 4 and 5 are formed extending from the same direction. Capacity
Since the value of C 2 can be reduced to some extent,
The value of capacitance C 2 can be reduced to some extent.
Regarding these capacitances C 1 and C 2 , electrodes 4 and 5
, the distance between the electrodes 4 and 5, and the length of the lead-out portions of the electrodes 4 and 5, but they are generally in a relationship that cannot be ignored.
一方、電気光学効果を有する強誘電体基板2に
は、PLZTのような透明セラミツクスが用いられ
るが、たとえば9/65/35(La/Zr/Ti)の比率
からなるものの比誘電率は室温100KHzにおいて
4600の値を有するため、上記した構造では容量
C1,C2は大きなものとなる。しかしながら、こ
のように電極4,5間の容量が大きくなるとスイ
ツチング速度が遅くなるという欠点があり、また
電源容量の負担が大きくなるなどの欠点が見られ
る。 On the other hand, a transparent ceramic such as PLZT is used for the ferroelectric substrate 2 having an electro-optic effect, but for example, the dielectric constant of a material made of a ratio of 9/65/35 (La/Zr/Ti) is 100 KHz at room temperature. in
Since it has a value of 4600, the above structure has a capacitance of
C 1 and C 2 will be large. However, when the capacitance between the electrodes 4 and 5 increases as described above, there are drawbacks such as a slow switching speed and an increase in the load on the power supply capacity.
したがつて、この発明は光シヤツタ部分を除い
た電気光学効果を有する強誘電体基板の領域に、
低誘電率の絶縁層を形成することにより、電極間
の容量を減少させ、低容量化を図つたものであ
る。 Therefore, the present invention includes a region of a ferroelectric substrate having an electro-optic effect excluding the optical shutter portion.
By forming an insulating layer with a low dielectric constant, the capacitance between the electrodes is reduced and the capacitance is lowered.
この発明の構成の概要を説明すれば次のとおり
であるすなわち、この発明にかかる光シヤツタア
レイ素子は基本的には、電気光学効果を有する強
誘電体基板の上に、複数の平行線状の電極を一方
側から他方側へ食い込ませて互いに差し込んだ状
態で形成し、この差し込み領域で光シヤツタ部分
を構成したものである。そしてその改良点は、光
イシヤツタ部分を除いた電気光学効果を有する強
誘電体基板の上の領域に、低誘電率の絶縁層を形
成し、この絶縁層の上に前記複数の平行線状の電
極を前記電気光学効果を有する強誘電体基板の端
縁側にまで延びるように、かつ前記複数の平行線
状の電極の先端を他方側の絶縁層に達するように
形成したことを特徴とする。 The outline of the structure of the present invention is as follows. That is, the optical shutter array element according to the present invention basically consists of a plurality of parallel linear electrodes on a ferroelectric substrate having an electro-optic effect. are formed so that they are inserted into each other from one side to the other, and this insertion area constitutes a light shutter portion. The improvement is that an insulating layer with a low dielectric constant is formed in the area above the ferroelectric substrate having an electro-optic effect, excluding the optical irradiator part, and the plurality of parallel linear lines are formed on this insulating layer. The present invention is characterized in that the electrodes are formed so as to extend to the edge side of the ferroelectric substrate having the electro-optic effect, and the tips of the plurality of parallel line electrodes are formed so as to reach the insulating layer on the other side.
この発明にかかる光シヤツタアレイ素子によれ
ば、電極が互いに差し込んだ状態で形成され、こ
の差し込み領域で光シヤツタを構成しており、し
かも光シヤツタ部分を除いた電気光学効果を有す
る強誘電体基板の上の領域に、低誘電率の絶縁層
を形成し、この絶縁層の上に複数の平行線状の電
極を電気光学効果を有する強誘電体基板の端縁側
にまで延びるように、かつ前記複数の平行線状の
電極の先端を他方側の絶縁層に達するように形成
しているから、光シヤツタ部分において、隣接す
る電極間で平行電界が形成されることになり、差
し込み領域の電極間で電圧印加のオン、オフを行
うことによつて電界がかかることになり、有効な
光のスイツチングを行うことができる。しかも、
電極の引出し部分や、電極間4,4間同志あるい
は電極5,5間同志の領域が存在しても、絶縁層
によつて低容量化が実現でき、スイツチング速度
の低下を抑制することができる。 According to the optical shutter array element according to the present invention, the electrodes are formed so as to be inserted into each other, and the insertion area constitutes an optical shutter, and a ferroelectric substrate having an electro-optic effect excluding the optical shutter portion is formed. An insulating layer with a low dielectric constant is formed in the upper region, and a plurality of parallel linear electrodes are formed on the insulating layer so as to extend to the edge side of the ferroelectric substrate having an electro-optic effect, and Since the tips of the parallel line electrodes are formed so as to reach the insulating layer on the other side, a parallel electric field is formed between adjacent electrodes in the light shutter area, and a parallel electric field is formed between the electrodes in the insertion area. By turning the voltage application on and off, an electric field is applied, and effective light switching can be performed. Moreover,
Even if there is a lead-out part of the electrodes or a region between the electrodes 4 and 4 or between the electrodes 5 and 5, the capacitance can be reduced by the insulating layer, and a decrease in switching speed can be suppressed. .
以下、この発明を一実施例にもとづいて詳細に
説明する。 Hereinafter, this invention will be explained in detail based on one embodiment.
第5図はこの発明にかかる光シヤツタアレイ素
子の一部を拡大した図であり、図に従つて説明す
ると、11は電気光学効果を有する強誘電体基
板、12a〜12c,13a〜13dは互いに差
し込んだ状態で形成された複数の平行線状の電
極、14は低誘電率の絶縁層である。この絶縁層
14は電極12a〜12c,13a〜13dの差
し込み領域である光シヤツタ部分Sを除いて強誘
電体基板11と電極12a〜12c,13a〜1
3dとの間に形成されている。また、電極12a
〜12c,13a〜13dの先端はそれぞれ対向
する絶縁層14に達するように形成されている。
絶縁層14としては低誘電率で形成の容易さを考
慮した場合、たとえばSiO2が選ばれる。 FIG. 5 is an enlarged view of a part of the optical shutter array element according to the present invention. To explain according to the figure, 11 is a ferroelectric substrate having an electro-optic effect, 12a to 12c, 13a to 13d are inserted into each other. A plurality of parallel line-shaped electrodes 14 formed in an open state are an insulating layer having a low dielectric constant. This insulating layer 14 is connected to the ferroelectric substrate 11 and the electrodes 12a to 12c, 13a to 1 except for the optical shutter portion S which is the insertion area of the electrodes 12a to 12c and 13a to 13d.
3d. In addition, the electrode 12a
The tips of ~12c and 13a~13d are formed so as to reach the opposing insulating layer 14, respectively.
For example, SiO 2 is selected as the insulating layer 14 considering its low dielectric constant and ease of formation.
具体例として、強誘電体基板11としてLa/
Zr/Tiの比率が9/65/35のPLZTからなり、厚
みが300μmの透明セラミツクスを用いた。この強
誘電体基板11の上に光シヤツタ部分Sを除いて
SiO2からなる絶縁層14を電子ビーム蒸着法に
より形成した。このSiO2膜の厚みは厚ければ厚
いほど好ましいが、あとで形成する電極と強誘電
体基板11との間に段差ができるため、この場合
3μmの厚みとした。次にAlを真空蒸着し、電極
幅60μm、電極間隔40μmになるようにAlをエツ
チングして電極12a〜12c、電極13a〜1
3dを形成した。 As a specific example, as the ferroelectric substrate 11, La/
A transparent ceramic made of PLZT with a Zr/Ti ratio of 9/65/35 and a thickness of 300 μm was used. On this ferroelectric substrate 11, except for the optical shutter portion S,
An insulating layer 14 made of SiO 2 was formed by electron beam evaporation. The thicker the SiO 2 film is, the better, but in this case there will be a step between the electrode that will be formed later and the ferroelectric substrate 11.
The thickness was 3 μm. Next, Al was vacuum-deposited and etched so that the electrode width was 60 μm and the electrode spacing was 40 μm.
3d was formed.
このようにして得られた光シヤツタアレイ素子
について、たとえば電極13b以外のすべての電
極を接地し、この電極13bと接地側との容量を
測定したところ、約290pFであつた。なお、比較
のためSiO2からなる絶縁膜を形成していない例
について同様に容量を測定したところ約570pFで
あつた。 Regarding the optical shutter array element thus obtained, for example, all electrodes other than electrode 13b were grounded, and the capacitance between electrode 13b and the ground side was measured and found to be about 290 pF. For comparison, the capacitance was similarly measured for an example in which no insulating film made of SiO 2 was formed, and it was approximately 570 pF.
こうした実測値などから計算すれば、電極12
bと電極13b間の容量C1は約130pFであり、一
方電極13bと電極13c間の容量C2は約10pF
の計算値が得られる。なお、SiO2からなる絶縁
膜を形成していない例では容量C2は約150pFとな
る。 If calculated from these actual measurements, the electrode 12
The capacitance C 1 between electrode 13b and electrode 13b is about 130 pF, while the capacitance C 2 between electrode 13b and electrode 13c is about 10 pF.
The calculated value is obtained. Note that in an example in which an insulating film made of SiO 2 is not formed, the capacitance C 2 is approximately 150 pF.
第6図はこの発明の他の実施例を示す。つま
り、光シヤツタ部分Sの高密度化を図り、電極1
2,13の強誘電体基板11の端縁側付近にボン
デイング部分を確保するために、第6図に示すよ
うに電極を強誘電体基板11の端縁側に向つて放
射状に形成する場合が考えられる。この場合、強
誘電体基板11の中央付近にある電極12,13
と中心位置から離れた電極12,1何のそれぞれ
の引出し部分の長さl1,l2に差ができることにな
り、この引出し部分間の容量C2についてバラツ
キが生じる。このような不都合に対してこの発明
によれば、容量C1に対して容量C2は非常に小さ
くなるため、全体としての容量のバラツキを小さ
くできるという利点を有する。 FIG. 6 shows another embodiment of the invention. In other words, the density of the optical shutter portion S is increased, and the electrode 1
In order to secure bonding portions near the edges of the ferroelectric substrates 11 in Nos. 2 and 13, it is conceivable that electrodes are formed radially toward the edges of the ferroelectric substrates 11 as shown in FIG. . In this case, the electrodes 12 and 13 near the center of the ferroelectric substrate 11
This results in a difference in the lengths l 1 and l 2 of the respective lead-out portions of the electrodes 12 and 1 that are located away from the center position, and variations occur in the capacitance C 2 between the lead-out portions. In order to overcome such disadvantages, the present invention has the advantage that the capacitance C 2 is much smaller than the capacitance C 1 , so that the variation in the capacitance as a whole can be reduced.
以上の実施例から明らかなようにこの発明にか
かる光シヤツタアレイ素子によれば、電極間に発
生する容量を減少させることができ、このことか
らスイツチング速度の高速化が図れるとともに、
電源の低容量化を実現することができる。 As is clear from the above embodiments, the optical shutter array element according to the present invention can reduce the capacitance generated between the electrodes, thereby increasing the switching speed.
It is possible to reduce the capacity of the power supply.
第1図は光シヤツタアレイの従来構造を示す概
略斜視図、第2図は電気光学効果を有する強誘電
体基板の平面図、第3図は第2図の部分拡大平面
図、第4図は第3図の等価回路図、第5図はこの
発明にかかる光シヤツタアレイ素子の一部平面
図、第6図は同じく他の光シヤツタアレイ素子の
実施例を示す概略平面図である。
11は電気光学効果を有する強誘電体基板、1
2a〜12c,13a〜13dは電極、14は絶
縁膜である。
FIG. 1 is a schematic perspective view showing the conventional structure of an optical shutter array, FIG. 2 is a plan view of a ferroelectric substrate having an electro-optic effect, FIG. 3 is a partially enlarged plan view of FIG. 2, and FIG. 3 is an equivalent circuit diagram, FIG. 5 is a partial plan view of an optical shutter array element according to the present invention, and FIG. 6 is a schematic plan view showing another embodiment of the optical shutter array element. 11 is a ferroelectric substrate having an electro-optic effect, 1
2a to 12c and 13a to 13d are electrodes, and 14 is an insulating film.
Claims (1)
複数の平行線状の電極を一方側から他方側へ食い
込ませて互いに差し込んだ状態で形成し、この差
し込み領域で光シヤツタ部分を構成した光シヤツ
タアレイ素子において、 光シヤツタ部分を除いた電気光学効果を有する
強誘電体基板の上の領域に、低誘電率の絶縁層を
形成し、この絶縁層の上に前記複数の平行線状の
電極を前記電気光学効果を有する強誘電体基板の
端縁側にまで延びるように、かつ前記複数の平行
線状の電極の先端が他方側の絶縁層に達するよう
に形成したことを特徴とする光シヤツタアレイ素
子。[Claims] 1. On a ferroelectric substrate having an electro-optic effect,
In an optical shutter array element in which a plurality of parallel line-shaped electrodes are inserted into each other from one side to the other, and the optical shutter part is formed in this insertion area, the electro-optic effect excluding the optical shutter part can be obtained. an insulating layer with a low dielectric constant is formed in a region on the ferroelectric substrate having the electro-optic effect, and the plurality of parallel line electrodes are formed on the insulating layer on the edge side of the ferroelectric substrate having the electro-optical effect. 1. A light shutter array element, characterized in that the plurality of parallel line electrodes are formed so as to extend up to 100 degrees and such that tips of the plurality of parallel line electrodes reach an insulating layer on the other side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18171583A JPS6073521A (en) | 1983-09-28 | 1983-09-28 | Optical shutter array element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18171583A JPS6073521A (en) | 1983-09-28 | 1983-09-28 | Optical shutter array element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6073521A JPS6073521A (en) | 1985-04-25 |
| JPH0458007B2 true JPH0458007B2 (en) | 1992-09-16 |
Family
ID=16105591
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18171583A Granted JPS6073521A (en) | 1983-09-28 | 1983-09-28 | Optical shutter array element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6073521A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4722597A (en) * | 1984-06-08 | 1988-02-02 | Matsushita Electric Industrial Co., Ltd. | Electrooptic shutter array element |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58107516A (en) * | 1981-12-22 | 1983-06-27 | Ricoh Co Ltd | Optical switching array |
-
1983
- 1983-09-28 JP JP18171583A patent/JPS6073521A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6073521A (en) | 1985-04-25 |
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