JPH0458329A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To detect the malfunction of a control circuit by performing the control in order to define only the parity of the arithmetic result of a valid computing element as the normal value among those arithmetic results of plural pipeline computing elements and also defining the parities of the arithmetic results of other invalid computing elements as the illicit parities. CONSTITUTION:The parities which undergo no inverted qualification are stored in the parity parts 29 and 39 only when the arithmetic results stored in the pipeline registers 23 and 33 of the final stage are valid, i.e., the signals show the valid state (= 1) in the registers 26 and 36. If the contents of the register 23 of the final stage which stores the arithmetic result of a pipeline computing element 2 are valid, a control circuit 5 inhibits the issue of instructions so as to evade the collision caused by a selection circuit 4 between the arithmetic results of both computing elements 2 and 3. Therefore the contents of the register 33 which stores the arithmetic result of the element 3 are invalidated. Thus the malfunction of the circuit 5 can be detected.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an arithmetic processing device that detects malfunction of an arithmetic control circuit.

Prior Art In an arithmetic device equipped with a plurality of pipeline arithmetic units, a selection circuit for selecting the arithmetic results of the plurality of arithmetic units, and a control circuit, it is attempted to improve the performance of the device by executing a plurality of arithmetic operations in parallel. In this case, it works as follows.

That is, the control circuit controls the issuance of instructions so that the operation results of each pipeline arithmetic unit do not collide with each other in the selection circuit. This control allows multiple parallel operations to be executed.

Parity pits are added to each data to detect malfunctions of arithmetic units and transfer errors during data transfer. Reliability is improved by performing an error check using this check circuit.

In such devices, the parity of the calculation results of the pipeline calculation unit has always been normal. Therefore, even if the selection circuit mistakenly selects an operation result from another pipeline arithmetic unit due to a malfunction of the control circuit, the parity of the incorrect operation result that is selected is normal. Therefore, the parity check circuit of the selection circuit could not detect the malfunction.

OBJECTS OF THE INVENTION An object of the present invention is to provide an arithmetic processing device that eliminates the conventional drawbacks and can detect malfunctions of control circuits.

Structure of the Invention The device of the present invention carries arithmetic pipeline registers that store arithmetic data or arithmetic results to be subjected to pipeline arithmetic processing, and a valid signal that indicates whether the contents of these arithmetic pipeline registers are valid or not. An operation valid signal carrying circuit (in the following embodiment, an operation valid signal carrying pipeline register) and an operation stored in the operation pipeline register when the valid signal carried by this operation valid signal carrying circuit indicates that it is not valid. The configuration includes a modification circuit that modifies the parity of the result.

Embodiment Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes a general-purpose register 1 for storing data, a data transfer bus 6 for transferring data from this general-purpose register 1, and a pipeline for data provided via this bus 6. A plurality of pipeline arithmetic units 2 and 3 that perform arithmetic processing, an arithmetic result transfer bus 7 that transfers the arithmetic results from these pipeline arithmetic units 2 and 3, and one of the arithmetic results from these buses 7 to the general-purpose register 1. A selection circuit 4 to send, an error detection circuit 14 that checks the parity of the selection result from the selection circuit 4 and detects errors, and a pipeline register in the pipeline arithmetic units 2 and 3 that generates a selection instruction signal to the selection circuit 4. It includes a control circuit 5 that generates a valid signal indicating whether the contents of 21 to 26 are valid or not, and a control signal bus 8 that transmits the signal from the control circuit 5 to the selection circuit 4 and the pipeline arithmetic units 2 and 3. .

The pipeline arithmetic unit 2 includes arithmetic pipeline registers 21, 22, and 23 that sequentially send and store arithmetic data, a parity modification circuit 28 that inverts and modifies the parity to be stored in the parity section 29 of this pipeline register 23, and these registers 21. ~23 contents are valid (for example, logic “1”)
Arithmetic valid signal carrying pipeline register 24゜2 which carries a valid signal indicating whether the signal is valid (“0”) or invalid (for example, logic “0”)
5 and 26, and the valid signal of register 25 are valid (
=1), the modifier circuit 28 selects and inputs the parity that is not inverted modified into the register 23, and when the valid signal of the register 25 indicates invalid (-0), the modifier circuit 28 selects and inputs the inverted modified parity to the register 23. The control circuit 27 includes a control circuit 27 that controls the selection input.

The pipeline arithmetic unit 3 includes arithmetic pipeline registers 31, 32, and 33 that sequentially send and store arithmetic data, a parity modification circuit 38 that inverts and modifies the parity to be stored in the parity section 39 of this register 33, and registers 31 to 33.
When the valid signal of the pipeline registers 3435 and 36 and the register 35 indicates valid (-1), The parity that is not inverted and modified by the modifier circuit 38 is selected and input to the register 33, and when the valid signal of the register 35 indicates invalidity (-〇), the modifier circuit 2
The control circuit 37 includes a control circuit 37 for controlling the register 23 to selectively input the parity inverted by 8 to the register 23. Incidentally, FIG. 3 shows a detailed example of the pipeline computing units 2 and 3.

Next, the operation of one embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, in one embodiment of the present invention, data from general-purpose register 1 is sequentially stored in registers 21 and 31 of pipeline arithmetic units 2 and 3 via data transfer path 6.

The pipeline arithmetic units 2 and 3 perform pipeline arithmetic processing on the data provided via the pipeline registers 21 to 23 and 31 to 33, and the arithmetic results are stored in the registers 23 and 33.

This calculation result is transferred to the selection circuit 7 via the bus 7,
The selection is made by the selection circuit 4 in response to a selection instruction signal applied from the control circuit 5 via the bus 8 . The operation results selected in this manner are stored in general-purpose register 1.

Valid signals are carried around in the pipeline registers 24-26 and 34-36 as described above. When the signal of the register 25.35 indicates valid (-1), the parity that is not inverted modified by the modifier circuit 28.38 or the parity part 29.39 of the final stage register 23.33.
is stored in

Also, when the signal of register 25.35 indicates invalid (-〇), the parity that has been inverted and modified by modifier circuit 28.38 is the parity section 29.39 of register 23.33 in the final stage.
is stored in

By applying such processing to the parity of the operation result, the parity section is processed only when the operation result in the final stage pipeline register 23, 33 is valid, that is, when the signal in the register 2636 indicates valid (-1). Parity that is not inverted modified is stored in 29.39.

For example, when the contents of the final stage register 23 that stores the calculation results of the pipeline calculation unit 2 are valid, the control circuit 5 transfers the calculation results of the calculation units 2 and 3 to the selection circuit 4.
Since no instructions have been issued to avoid collisions, the contents of the register 33 that stores the operation results of the pipeline arithmetic unit 3 are invalidated.

A technique for issuing commands in the selection circuit 4 so as to avoid conflicting operation results will be described below.

FIG. 2 is a circuit diagram showing a specific example of the control circuit 5.
Referring to the figures and FIG. 2, instructions provided on line 10 are decoded by decoder 50 within control circuit 5. Referring to FIG. Based on the result of this decoding, the contents of the selected circuit management registers 51 to 54 are checked, and if the instruction can be issued, the instruction is issued, and a value indicating the operation execution time is stored in the stack 55. While an operation is being executed in the pipeline arithmetic unit 2 or 3, the value indicating the operation execution time in the stack is clocked down every clock. When the value becomes “0”, selection circuit 4
is switched, and the operation result is taken into general-purpose register 1.

For example, when a pipeline arithmetic unit operates with three pipeline stages and takes 2" to execute an operation, when issuing an instruction,
If the selection circuit management register 51 is in a free state indicating "0", it can be issued.

Therefore, the instruction is issued, the selection circuit management register 51 becomes "1", and the operation execution value "2" is stored in the stack 55. Thereafter, the contents of the stack 55 are counted down every clock, and "1" in the selection circuit management register 51 is counted down.
° is rotated every clock with registers 53 and 54, and in the pipeline arithmetic unit 2, the pipeline register 21
．． Arithmetic processing is performed using 22 and 23.

After 2 clocks, the operation data is transferred to pipeline register 2.
3, and the value in the stack 55 is "O". The selection circuit 4 is controlled to take in the calculation result from the pipeline calculation unit 2 by a control signal applied via the selection circuit control line 8 at the next clock.

When the above control is performed, if the pipeline arithmetic unit 3 receives an instruction with an arithmetic execution time of "1" following an instruction with an arithmetic execution time of "2", the selection circuit management register 52 is busy. Commands cannot be issued.

Therefore, an instruction with an operation execution time of "1" remains in the instruction issue control decoder 50 for one clock, and the pipeline management register 52 becomes free at the next clock, allowing the instruction to be issued. At this time, whether register 52 is busy or register 5
1 or free, and an instruction with an operation execution time of "2" can be issued, the instruction issue control decoder 50 increases the operation execution time of the pipeline arithmetic unit 3 from "1" to "2". This synchronizes with the operation execution time in the stack that was changed when the instruction was issued.

The above control makes it possible to continuously issue instructions that could not be issued by conventional instruction issue control circuits.

That is, if the parity of the calculation result register 23 is normal, the <parity of the calculation result register 33 becomes an invalid value. As a result, the control circuit 5 or the selection circuit 4
If the contents of the calculation result register 33 of the calculation unit 3 are selected when the contents of the calculation result register 23 of the calculation unit 2 should be selected due to a failure, the parity of the contents of the calculation result register 33 is invalid. Then, a parity error occurs in the error detection circuit 14 and a malfunction is detected.

Effects of the Invention The present invention makes it possible for only the parity of the operation result of a valid operation unit to be a normal value among the operation results of a plurality of pipeline operation units, and the parity of the operation results of other invalid operation units to be invalid. is controlled. Therefore, if the control circuit of the selection circuit that selects calculation results from multiple calculation units malfunctions and selects the calculation result of an invalid calculation unit, a parity error will occur in the error detection circuit of the selection circuit. Malfunctions can be detected. As a result, there is an effect that malfunctions of the control circuit can be detected, which was previously impossible.

[Brief explanation of drawings]

1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a detailed configuration of the control circuit 5 in FIG. 1, and FIG. 3 is a diagram showing details of the pipeline arithmetic units 2 and 3 in FIG. 1. FIG. Explanation of symbols of main parts 1...General-purpose register 2.3...Pipeline arithmetic units 24-26 34-36...Arithmetic valid signal carrying register 2
9.39...Parity department

Claims (1)

[Claims] (1) Storage means for storing calculation data or calculation results to be subjected to pipeline calculation processing, signal transport means for transporting a valid signal indicating whether or not the contents of this storage means are valid, and this signal transport means. An arithmetic processing device characterized by comprising: modifying means for modifying the parity of an arithmetic result stored in the storage means when the valid signal carried by the means indicates that it is not valid.