JPH0458679B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory capable of detecting leakage current existing in a semiconductor element or the like and removing such a semiconductor memory.

(Prior Art) Conventionally, semiconductor memories have been subjected to rigorous electrical tests at low and high temperatures after the wafer stage or package assembly to eliminate defective products or those that do not meet electrical standards. However, in recent miniaturized ICs (semiconductor integrated circuits), although there are sometimes leakage current paths within the elements, they are shipped as non-defective products because they meet electrical standards, and after they are mounted on equipment, this leakage The current path increases, and there are more cases of IC failure. This means, for example, that the operating current of the circuit is
This is because even if a leakage current of 10 μA exists at 1 mA, it will only disturb the voltage level by about 1%, and it will have almost no effect on the characteristics and cannot be excluded in initial electrical tests. That is, conventional semiconductor memories have a drawback in that defective elements having minute leakage current paths cannot be completely removed by electrical testing on a wafer.

(Object of the Invention) An object of the present invention is to provide a highly reliable semiconductor memory capable of detecting even a small leakage current in an electrical test in a wafer state by eliminating the above-mentioned drawbacks.

(Structure of the Invention) A semiconductor memory of the present invention includes first and second cell transistors whose bases and collectors are cross-connected to each other and whose first emitters are commonly connected, and one end of which is connected to the first and second cell transistors. A plurality of memory cells formed in a flip-flop type and arranged in a matrix of rows and columns, each including first and second load elements correspondingly connected to the collectors of the plurality of memory cells; a first digit line connected to the second emitter of each of the first cell transistors of the corresponding column provided and a second digit line connected to the second emitter of each of the second cell transistors; A first load element provided for each row of memory cells and connected to the other ends of the first and second load elements of the corresponding row.
and a second word line connected to the first emitters of the first and second cell transistors, and currents in the corresponding first and second digit lines depending on the voltages supplied to the bases. a read current circuit including a plurality of first transistors each controlling the current of the second word line, and a plurality of second transistors each controlling the current of the corresponding second word line according to the voltage supplied to the base. a holding current circuit; and a plurality of third transistors that are provided corresponding to each of the first word lines and flow a collector current according to a voltage supplied to the base, and the first word line corresponds to the address signal. a word line driver circuit that sets the word line to a selection level; a reference voltage circuit that supplies a reference voltage to each of the first, second, and third transistors; and a highest potential terminal and each of the first and second digit lines. and a plurality of first diodes connected to the second word line so that a reverse voltage is applied between the bases and emitters of the first and second cell transistors, respectively, and When a voltage outside the level range is applied to the signal input terminal between the signal input terminal for inputting a signal in the level range and the bases of each of the first, second, and third transistors, When a voltage outside the level range is applied to the second diode connected to turn off the first, second, and third transistors and to be non-conductive within the level range, and the signal input terminal. a third fixing each first word line to a predetermined voltage;
diodes and a word line voltage fixing circuit.

Further, the second diode is connected between the signal input terminal and the bases of each of the first and second transistors.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of essential parts for explaining the operating principle of an embodiment of the present invention.

In this embodiment, cell transistors Q ₁ to _{Q 4} whose bases and collectors are cross-connected to each other constitute a flip-flop (Q ₁ and Q ₂ and Q ₃ and Q ₄ each form a two-emitter type NPN transistor). A memory cell 11 consisting of load resistances R ₁ and R ₂ is
One ends of the load resistors R ₁ and R ₂ are commonly connected to the high potential side (first) word line WT, and the cell transistor is connected to the high potential side (first) word line WT.
The emitters of Q ₂ and Q ₄ are commonly connected to the low potential side (second) word line WB, and the cell transistor Q ₁
The emitter of the cell transistor Q3 is connected to the first digit line D, and the emitter of the cell transistor _Q3 is connected to the second digit line to form a memory cell array. And the highest potential terminal
Connect a diode between the V _CCA terminal 12 and the digit line D, word line WB, and digit line, respectively.
D ₁ , D ₂ and D ₃ are connected with the anode side being the V _CCA terminal 12. Furthermore, the V _CCA terminal 12 is connected to the collector of an NPN type output transistor _Q5 whose emitter is connected to the output terminal O.

In a normal ECL type logic circuit, the highest potential terminal is
The power supply V _CC terminal to which the internal circuit is connected and the V _CCA terminal 12 to which the collector of the output transistor Q ₅ is connected
I have two. Here, V _CCA terminal 12 is
If no load resistor is connected to the emitter of output transistor _Q5 , only the collector of output transistor _Q5 is connected, so unless there is a leakage current path between the base and collector of output transistor _Q5 , a high It is in an impedance state. On the other hand, only the emitters of cell transistors Q ₁ to _{Q 4} and the collectors of constant current transistors for supplying constant current to these word lines and digit lines are connected to the word line WB and digit line D on the low potential side of the memory cell array. Therefore, if the word line WB or digit line D is forced to the high potential side, the word line WB or digit line D will increase the emitter-base breakdown voltage (BV) of the cell transistors _Q1 to _Q4 . It remains in a high impedance state until it exceeds _EB ) or emitter-collector breakdown voltage (BV _EC ). Therefore, as shown in FIG. 1, the diodes D ₁ , D ₂ ,
By connecting the V _CCA terminal 12 to the word line WB and digit line D through _D3 , the V _CCA terminal 12
BV _EB and BV _EC of the cell transistor can be observed.

In Figure 2, the voltage of the word line WT is 0V, and V _CCA
It shows the current characteristics when a voltage is applied to the terminal 12. Normally BV _EB or BV _EC has a value of about 3.5V, so if the forward voltage of diodes D ₁ , D ₂ , D ₃ is 0.8V and the voltage V _CCA is 4.2V or more, the cell transistor will break down. do
Diode D ₁ from V _CCA terminal 12 to word line WT,
Current can be passed through D ₂ and D ₃ . By the way, now cell transistors Q ₁ , Q ₂ , Q ₃ , Q ₄
If there is any leakage between EB (emitter-base) or EC (emitter-collector), the voltage will be lowered from V _CCA terminal 12 through this leakage current path before breakdown occurs between EB or EC. Since a current is passed through the word line WT, almost the diode characteristics of the diode D ₁ , D ₂ or D ₃ are observed as shown in FIG. 2B. Note that in FIG. 2, A indicates normal characteristics.

FIG. 3 shows a circuit diagram of an embodiment of the present invention constructed based on this operating principle.

In this embodiment, memory cells M ₁₁ ...M _on are connected to word lines WT ₁ ...WT _o , WB ₁ ...W _o and digit lines.
The memory cell array 21 is arranged between D ₁ , _{1 .} . . D _n , _n, respectively. The digit lines D ₁ , _{1 .} . . D _n , _n are each connected to the collector of the constant current (first) transistor of the read current circuit 22 _, and the word lines WB ₁ . Connected to the collector of the current (second) transistor, the word line WT ₁ ...
WT _o is connected to the emitter of the driver transistor of the word driver circuit 24, respectively. Furthermore, the word lines WT ₁ ...WT _o are each a diode.
D _WT1 ...Word line voltage fixing circuit 2 via D _WTo
The input transistor Q11 of the word line voltage fixing circuit 25 is connected to the collector of the output transistor Q11 of the word line voltage fixing circuit ₂₅ .
The base of is connected to the signal input terminal IN of the internal circuit 26 via the third diode _DC , and this signal input terminal IN is connected to the holding current I _WB1 ...I _WBo of the memory cell array 21 via the diode Dd. The reference voltage terminal 3 of the reference voltage circuit 27 serves as a control circuit that controls the read currents I _D1 , I _D1 ...I _Dn , I _Dn
0, and the reference voltage terminal 30 is further connected to the bases of constant current (first, second, and third) transistors of the read current circuit 22, the holding current circuit 23, and the word driver circuit 24. On the other hand, digit lines D ₁ , ₁ ...D _n , _n and word lines W _B1 ...
W _Bo are (first) diodes D _D1 and D _D respectively
₁ ......D _Dn , D _Dn and the diode D _WB1 ...D _WBo are connected to the cathode, and the diodes D _D1 , D _D1 ...
D _Dn , D _Dn and D _WB1 ...The anodes of D _WBo are commonly connected and connected to the collector of the output transistor 28 through a series connection circuit of diodes Da and Db.
Connected to V _CCA terminal 29.

That is, diodes Da and Db are connected to the V _CCA terminal 29 to which the collector of the output transistor 28 is connected.
Diodes D D1 , D D1 ... D Dn , D Dn are connected to each digit line D ₁ , ₁ ... D _n , _n through the digit lines D ₁ , ₁ ... D _n , _n , and a diode D _WB1 ... is connected to each word line WB ₁ ... WB _o .
D _WBo is connected.

For normal memory read/write operations,
Digit lines D ₁ , ₁ ... D _n , _n and word lines
WB ₁ ...WB _o potential does not fall below the voltage V _CC of the power supply V _CC to a potential less than three times the forward voltage (Vf) of the diode, so these diodes Da, Db,
D _D1 , D _D1 ... D _Dn , D _Dn , D _WB1 ... D _WBo has no influence.

In normal operation, the signal input terminal IN has -
A normal logic level of 0.9V/−1.7V is applied, but when observing the leakage current characteristics of the memory cell of this embodiment, the same level as the voltage V _EE of the power supply V _EE is applied. When the signal input terminal IN becomes the same level as V _EE , the output level of the reference voltage circuit 27 is first lowered through the diode Dd, and the constant current transistors of the holding current circuit 23, read current circuit 22, and word driver circuit 24 are all turned off. Turn off.

As a result, the holding current I _WB1 of the memory cell array 21
...I _WBo and the read currents I _D1 , I _D1 ...I _Dn , I _Dn are turned off, making it easy and accurate to observe the leakage current characteristics of the memory cell.

On the other hand, a diode connected to the signal input terminal IN
The word line voltage fixing circuit 25 is turned on by DC. That is, when a normal logic level is input to the signal input terminal IN, the input transistor _Q11 of the word line voltage fixing circuit 25 is on, and the output current _IW is zero, but the signal input terminal When IN becomes the same level as V _EE , transistor Q ₁₁ is turned off and an output current I _W is generated. As a result of all constant current transistors in the word driver circuit 24 being off, the output current _IW is
D _WT1 ... D _WTo is equally divided, and the word line WT ₁ ...
...Fix W _o to a potential that is lower than V _CC by the forward voltage Vf of the diode and approximately equal to the selection level.

In this state, a voltage higher than V _CC is applied to the V _CCA terminal 29.
When V _CCA is applied, there is no leakage current path in the cell transistor and BV _EB , BV _EC = 3.5V, the voltage increases.
V _CCA does not flow current until 3.5V + 2 x Vf = 3.5V + 0.8V x 2 = 5.1V because the cell transistor does not break down. However, if there is a leakage current path in any one of the cell transistors, current begins to flow at a voltage V _CCA of 2×Vf=1.6V or higher. In other words, V _CCA terminal 29
It is sufficient to apply a voltage of approximately 2V, which is greater than 1.6V, and detect the presence or absence of current flowing from the V _CCA terminal 29 at this time to determine whether the semiconductor memory is good or bad.

Further, in this embodiment, there is a method of applying a word address input signal without turning off the constant current transistor of the word driver circuit 24. In this way, according to this word address input signal, only one of the word lines WT ₁ ... WT _o will be selected and set to high level, and all the others will be set to low level, so
It is also possible to selectively check the leakage current characteristics of only memory cells on one word line.

(Effects of the Invention) As described in detail above, the semiconductor memory of the present invention has a decoupling diode connected between the highest potential terminal (V _CCA ) and the digit line and the word line on the low potential side. If a transistor constituting a memory cell has a leakage current path, a word line voltage fixing circuit connected to the word line on the potential side allows the voltage to be applied from the highest potential terminal through the diode and the memory cell with the leakage current path. Since a current path is formed between the current path and the lowest potential terminal (V _EE ), the presence or absence of a memory cell having a leakage current path can be easily tested. Furthermore, the semiconductor memory of the present invention has the effect that leakage current paths can be checked more accurately by turning off the constant current transistors of the holding current circuit and the read current circuit using an external control signal.

Therefore, according to the present invention, a highly reliable semiconductor memory that can detect even a slight leakage current in an electrical test in a wafer state can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the main part for explaining the operating principle of an embodiment of the present invention, FIG. 2 is a current-voltage characteristic diagram between the word line WT-V _CCA terminal in FIG. 1, and FIG. FIG. 1 is a circuit diagram of an embodiment of the present invention. 11...Memory cell, 12...V _CCA terminal, 2
DESCRIPTION OF SYMBOLS 1...Memory cell array, 22...Reading current circuit, 23...Holding current circuit, 24...Word driver circuit, 25...Word line voltage fixing circuit, 2
6... Internal circuit, 27... Reference voltage circuit, 28...
...Output transistor, 29...V _CCA terminal, 30
...Reference voltage terminal, D,, _D1 , ₁ , Dn, _{n ...}
...digit line, D ₁ to D ₃ , Dc, Dd, D _D1 , _D1 ,
D _Dn , _Dn , D _WB1 , D _WBo , D _WT1 , D _WTo ...Diode, I _D1 , _D1 , I _Dn , _Dn ...Reading current, I _WB1 ,
I _WBo ...Holding current, I _W ...Output current (word line voltage fixing circuit), IN...Signal input terminal, _M11 , _M1n ,
M _1o , M _on ... memory cell, O ... output terminal, Q ₁
~Q ₅ , Q ₁₁ ... NPN transistor, R ₁ , R ₂ ...
Load resistance, WB, WB ₁ , WB _o , WT, WT ₁ ,
WT _o ...word line.

Claims (1)

[Claims] 1. The base and the collector are cross-connected to each other and the first
A flip-flop type device comprising first and second cell transistors whose emitters are commonly connected, and first and second load elements whose one ends are connected to the collectors of the first and second cell transistors in correspondence with each other. A plurality of memory cells formed and arranged in a matrix of rows and columns, and a first emitter provided for each column of the plurality of memory cells and connected to the second emitter of each of the first cell transistors in the corresponding column. and a second digit line connected to the second emitter of each of the second cell transistors, and the first and second load elements provided for each row of the plurality of memory cells in the corresponding row. a first word line connected to the other end and a second word line connected to the first emitters of the first and second cell transistors; and a read current circuit comprising a plurality of first transistors each controlling the current of the second digit line, and a plurality of read current circuits each controlling the current of the corresponding second word line according to the voltage supplied to the base. a holding current circuit comprising a second transistor;
a plurality of third transistors, each of which is provided in correspondence with the first word line, and whose collector current flows in accordance with the voltage supplied to the base; the first word line corresponding to the address signal is set to a selection level A driver circuit, a reference voltage circuit that supplies a reference voltage to each of the first, second, and third transistors, and between the highest potential terminal and each of the first, second, and second digit lines and the second word line. a plurality of first diodes connected so that a reverse voltage is applied between the base and emitter of the first and second cell transistors, respectively; and a signal for inputting a signal in a predetermined level range to the internal circuit. When a voltage outside the level range is applied to the signal input terminal between the input terminal and the base of each of the first, second, and third transistors, each of the first, second, and third transistors a second diode connected to be non-conductive within the level range; and a second diode connected to be non-conductive within the level range; 1. A semiconductor memory comprising a third diode and a word line voltage fixing circuit for fixing the voltage to a voltage of . 2. The semiconductor memory according to claim 1, wherein the second diode is connected between the signal input terminal and the bases of each of the first and second transistors.