JPH045948B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic analyzer, and particularly to a logic analyzer that compares captured data with reference data and separates (identifies) error data in input data.

Recently, many electronic devices have built-in microprocessors, and it is difficult to repair such electronic devices using only one oscilloscope. Logic analyzers are effective in isolating defects in logic circuits in a very short time. As the number of information channels increases and the capacity of storage devices increases, there is a need for a method to limit the number of data during readout and display and concentrate on channels where defects actually exist and a small portion of the captured data within those channels. be.
New logic analyzers have emerged that allow the operator to increase the number of signal acquisition channels to, for example, 104 and the capacity of the signal acquisition storage to, for example, 512 words. When it comes to multi-channels like 104 channels, only 2 or 3 channels, i.e. only 2,
It becomes difficult to isolate the defect in the storage part 3.

Conventional logic analyzers have a trigger word function that captures input data before and after the trigger word. If the trigger word is a defective word, the defective word of the captured input data can be separated. However, this method cannot separate defective words when they are combined in a complex manner.

Other conventional logic analyzers
119070), any captured word can be stored for later comparison. To isolate erroneous words, the operator can use a logic table display to compare the acquired data to reference data stored in a reference store. Furthermore, this kind of logic analyzer
It has a brightness modulation function that distinguishes different data parts by increasing the display brightness of the captured data parts that are different from the reference data. However, since the display area is limited and it is not possible to display all the captured data at the same time, it is troublesome to check all the captured data.

Furthermore, other conventional logic analyzers (Japanese Patent Application Laid-open No.
-119070 publication) displays both captured data and reference data, and compares the captured data with the reference data, starting from the LSB (least significant bit).
The columns of the display table are erased up to the MSB (most significant bit) or from the MSB to the LSB. However, in such a method, since the acquired data is compared channel by channel and not word by word, it is troublesome to separate the erroneous words. Furthermore, all of the captured data cannot be displayed at the same time.

Furthermore, other conventional logic analyzers can acquire data by comparing the storage contents of the data acquisition storage device and the reference storage device, and repeating this comparison until the storage contents match. However, in this logic analyzer, the reference storage device has a large storage capacity, and the operator must store both important and unimportant words. Memory settings are troublesome.

In view of the above points, the present invention eliminates the drawbacks of the prior art described above, and provides a logic analyzer that can quickly compare captured data with reference data and can reliably obtain desired captured data. The purpose is to provide.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a logic analyzer using the present invention. Data import pods 10-16
is connected to the level adjustment circuit 18 through a data bus. Each probe pod 10-16 has eight probe chips (not shown) for detecting logic signals from the device under test. Level adjustment circuit 18 adjusts the level of the logic signals from probe pods 10-16 to a predetermined logic level (determined by the logic circuit used in the logic analyzer). The output of level adjustment circuit 18 is stored in acquisition storage circuit 28 in storage mode according to an address signal from storage address register 30. A storage section for each probe chip in the storage circuit 28 is determined in advance. The desired word from the level adjustment circuit 18 is detected by a word recognition circuit 32, and the detection output is provided to a main bus 34 consisting of data, address and control buses.

The data stored in the storage circuit 28 is supplied to the controller, interface and register circuit 36 during the read operation, and the output of the stored data is supplied to the main bus 34.
Additionally, control data from the main bus 34 is supplied to this circuit 36, which controls the storage and read modes of the storage circuit 28, the address and counting speed of the storage address register 30, and the word recognition circuit 32. desired word is controlled. The trigger and time base circuit 38 has a clock signal generator and is connected to the main bus 34 by which the trigger position (front, middle or rear trigger) is controlled and the clock signal generator from the main bus 34 is controlled. A clock signal is generated according to the control signal.

Microprocessor 40, keyboard 42, random access memory (RAM) 44, read only memory (ROM) 46 and display controller 48
is connected to the main bus 34. Microprocessor 40 is a central processing unit that processes data and receives instruction signals from keyboard 42 and
Control signals are generated according to the firmware stored in the ROM 46. RAM 44 temporarily operates as memory and assists the operation of microprocessor 40. A character generator 50 and a timing waveform generator 52 are controlled by a display controller 48, and a menu (logic analyzer operating mode list), state table (stored data is displayed in binary format) is displayed on a display means, that is, a monitor 54. , octal, or hexadecimal).
Alternatively, a timing diagram (accumulated data is displayed in logical waveforms) is displayed. The operator is
microprocessor 40, keyboard 42 and
The firmware stored in the ROM 46 can control the display mode, trigger word, clock frequency, memory address, trigger position, storage/readout mode, etc.

The configuration and operation described above are similar to those of a conventional logic analyzer. The present invention has unique features as described below. To operate the logic analyzer, the operator uses the keyboard 42 to set a number of logic analyzer conditions and select a storage mode. In this embodiment, 32 probe chips in the data acquisition probe pods 10 to 16 are configured according to the firmware in the ROM 46.
Divided into groups A, B and C. That is, probe pods 10 and 12 constitute group A;
Probe pods 14 and 16 constitute groups B and C, respectively. The trigger word is set to "000FFFE" by hexadecimal notation. The data detected by the probe pods 10-16 is stored in a predetermined portion of the storage circuit 28 via the level adjustment circuit 18. Trigger word is word recognition circuit 3
2, the data acquisition operation is stopped according to the trigger position. At that time, the desired data is stored in the storage circuit 28.

In order to use the stored data as reference data, the stored data is transferred from the storage circuit 28 to the controller, interface and register 36, and main bus 34 according to key operations on the keyboard 42.
The data is transferred to a predetermined part of the RAM 44 through. The memory circuit 28 and RAM 44 constitute a memory means. When the hexadecimal state table is selected by key operation, the microprocessor 40
The binary signal stored in the RAM 44 is converted into a hexadecimal signal and is supplied to the display controller 48 for display according to the firmware of the ROM 46. Display controller 48 controls character generator 50 to display the state table on monitor 54. In this case, the keyboard 42
The 14 words of the desired address selected by are displayed. However, if the display contains unimportant words, the display table becomes difficult to read. According to the invention, only important words are displayed. The operator determines the critical word or address and then enters the start and stop address of the critical word via the keyboard 42. This address information is stored in RAM 44 by microprocessor 40. When the microprocessor 40 receives a mask command from the keyboard 42, the unselected address words, ie, the rows of the state display, are masked by the microprocessor 40 according to the information in the RAM 44 and the firmware in the ROM 46. That is, the microprocessor 40 acts as a masking means, and the rows are masked as shown in FIG.

In the display shown in Figure 2, "TRIG=" means a trigger word, "A", "B" and "C"
means a probe group, "SEQ" means a sequence of words, i.e., a memory address, and "HEX" means a 16
It means the base of the decimal number. Words of SEQ 18-24 are displayed; other words are masked, ie, not read from RAM 44 by microprocessor 40. A string of start and stop addresses or words is displayed in the upper right corner of monitor 54. Additionally, the third number of group A (corresponding to the four probe tips on pot 12) and the first number of group B (corresponding to the four probe tips on pot 14)
The th digit, ie, LSB, is masked, ie, the desired column is masked according to the key operation. The masked number information is stored in RAM 44.
In other words, the present invention can mask both unimportant columns and rows.

To compare acquired data with reference data,
New data is captured by the logic analyzer and stored in storage circuit 28. Third
As shown, both the captured data in storage circuit 28 and the reference data in RAM 44 are displayed on monitor 54 by firmware stored in microprocessor 40 and ROM 46. "ACQ" and "REF" in the display in Figure 3
represent captured data and reference data, respectively. If desired, desired columns and rows of the captured data can be erased in the same manner as the reference data. In this way, defects in captured data can be easily separated (identified).

In order to facilitate the discovery of defective data, the present invention compares the captured data with the rest of the masked reference data by means of a microprocessor 40, which is a comparing means, and compares the captured data with the rest of the masked reference data.
The comparison process can be repeated until the stored contents of the RAM 44} match or do not match, and the data can be imported. This function is performed as follows. By the microprocessor 40,
The remainder of the masked data is selected from the lookup table stored in RAM 44 according to the mask information in RAM 44 and the firmware in ROM 46. Furthermore, the information in the masked columns of RAM 44 and
According to the firmware of the ROM 46, a necessary column, that is, a channel is selected from the captured data,
The captured data is compared to the unmasked data in the lookup table. It should be noted that such a feature not only speeds up the comparison process, but more importantly allows the elimination of unimportant columns and rows in the display table. Furthermore, since only the important data is compared with the acquired data by the microprocessor, the comparison process is faster and the data acquisition clock frequency can be increased. In addition, new imported data is repeatedly imported until a match or mismatch between the reference data part and the imported data part is detected, but since the comparison process can be performed quickly as described above, that is, in a short time, the desired imported data can be The possibility of losing data is reduced.

It will be obvious to those skilled in the art that the above description is only of one preferred embodiment of the invention, and that various modifications can be made without departing from the spirit of the invention. For example, the operating procedure of the present invention can be controlled by hardware rather than firmware.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a logic analyzer according to the present invention, and FIGS. 2 and 3 are diagrams showing displays of display means for explaining the operation of the present invention. 10-16 are data acquisition probe pods, 2
8 and 44 are storage means, 40 is a microprocessor, 42 is a keyboard, 46 is a ROM, and 54 is a display means.

Claims (1)

[Claims] 1. Recording reference data consisting of a plurality of words in a storage means, sequentially importing captured data and storing it in the storage means, and displaying the stored reference data and captured data as a table of a desired radix on a display means. In the logic analyzer, a masking means for masking both a desired row and column of the table of the reference data;
comparing means for comparing the portion of the unmasked reference data with a portion of the captured data stored in the storage means and corresponding to the portion of the unmasked reference data, the portion of the unmasked reference data and the captured data; A logic analyzer characterized in that the acquisition of the above-mentioned newly acquired data is repeated until a match or a mismatch is detected in the parts.