JPH045992B2 - - Google Patents

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Publication number
JPH045992B2
JPH045992B2 JP56070160A JP7016081A JPH045992B2 JP H045992 B2 JPH045992 B2 JP H045992B2 JP 56070160 A JP56070160 A JP 56070160A JP 7016081 A JP7016081 A JP 7016081A JP H045992 B2 JPH045992 B2 JP H045992B2
Authority
JP
Japan
Prior art keywords
ecd
circuit
voltage
switch
electrochromic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56070160A
Other languages
Japanese (ja)
Other versions
JPS57185485A (en
Inventor
Tatsuo Niwa
Tsuneo Sukegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nikon Corp
Original Assignee
Nippon Kogaku KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Kogaku KK filed Critical Nippon Kogaku KK
Priority to JP7016081A priority Critical patent/JPS57185485A/en
Publication of JPS57185485A publication Critical patent/JPS57185485A/en
Publication of JPH045992B2 publication Critical patent/JPH045992B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 本発明はエレクトロクロミツク素子の駆動装置
に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for driving an electrochromic device.

従来より、エレクトロクロミツク素子(ECD)
は電圧を印加すれば酸化還元反応により着色また
は消色することを利用したものである。その素子
構造は、ガラス等の基板上に透明電導膜が形成さ
れその上にエレクトロクロミツク物質と電解質か
らなるEC層がもう一つの基板上に形成された透
明電極でサンドイツチされている。両側の基板上
の透明電極に着色電圧を印加すればEC層が着色
し逆電圧を印加すれば透明になり消色する。
Traditionally, electrochromic devices (ECD)
This method utilizes the fact that when voltage is applied, the color changes or disappears due to an oxidation-reduction reaction. The device structure is such that a transparent conductive film is formed on a substrate such as glass, and an EC layer made of an electrochromic substance and an electrolyte is sandwiched between a transparent electrode formed on another substrate. When a coloring voltage is applied to the transparent electrodes on both substrates, the EC layer is colored, and when a reverse voltage is applied, it becomes transparent and disappears.

従来ECD駆動装置は駆動回路の電源が切られ
たときECDの両電極はオープンあるいは短絡さ
れたまゝである。しかしECDの駆動時に過電圧
等のため副反応が生じることがありECDに消色
電圧を印加したのち消色状態が実現してもECD
の両電極をオープンあるいは短絡したまゝに長時
間放置すれば着色状態に戻ることがある。
In conventional ECD drive devices, both electrodes of the ECD remain open or shorted when the drive circuit is powered off. However, when driving the ECD, side reactions may occur due to overvoltage, etc. Even if a decoloring state is achieved after applying a decoloring voltage to the ECD, the ECD
If both electrodes are left open or shorted for a long time, the colored state may return.

またEC層がそれぞれ還元によつて着色するEC
層A、固体電解層B、酸化によつて着色するEC
層Cの三層からなり、一つのEC層Aのみがパタ
ーニングされている全固体型ECDにおいては、
着色電圧を印加するとパターニングされている
EC層AとパターニングされていないEC層Cの
EC層Aに対向する部分とが着色し、その合成の
色が観察される。着色を長時間続けるとEC層C
のEC層Aに対向する部分に隣接する部分へ着色
関与するイオンが拡散し着色する。拡散による着
色は消色のレスポンスが遅いため一定時間の消色
電圧を印加しても消え残つたまゝになる。
Also, the EC layer is colored by reduction.
Layer A, solid electrolyte layer B, EC colored by oxidation
In an all-solid-state ECD that consists of three layers, layer C, and only one EC layer A is patterned,
It is patterned when a coloring voltage is applied.
EC layer A and unpatterned EC layer C
The portion facing the EC layer A is colored, and the combined color is observed. If coloring continues for a long time, EC layer C
The ions involved in coloring diffuse into the part adjacent to the part facing the EC layer A and are colored. Coloring caused by diffusion has a slow response to erasing, so it remains erased even if a color erasing voltage is applied for a certain period of time.

この様な着色の残りは表示素子の品位を下げる
ばかりでなく表示の誤認の原因にもなる。特に透
過型でECDを使用するときは消え残りは著しく
視界を妨げ使用不能となる。
Such residual coloring not only degrades the quality of the display element but also causes misperception of the display. Particularly when using a transparent type ECD, the remaining parts will significantly obstruct visibility and become unusable.

このためECDの非駆動時にも常時消色電圧を
印加しECDの消残りを防ぐことを行うように
ECD駆動回路を作動させることが考えられるが、
常時ECD駆動回路を作動させることは駆動回路
自体での電力消費が大きくなつてしまう。
For this reason, a decoloring voltage is always applied even when the ECD is not driven to prevent the ECD from remaining unerased.
It is possible to activate the ECD drive circuit, but
If the ECD drive circuit is constantly operated, the power consumption of the drive circuit itself becomes large.

本発明の目的は、ECDの非駆動時に常時消色
電圧を印加するが消費電力の極めて少ないECD
駆動装置を提供することにある。
The purpose of the present invention is to apply a decoloring voltage to the ECD at all times when the ECD is not driven, but to provide an ECD with extremely low power consumption.
The purpose of the present invention is to provide a driving device.

上記課題は、本発明に従い、ECD駆動回路と
は別にその作動中電力消費が極めて少ない消色電
圧回路を設けたECD駆動装置によつて解決され
た。本発明のECD駆動装置の構成は、エレクト
ロクロミツク素子を着・消色する駆動回路、駆動
回路を作動させる第1状態とこれを非作動とする
第2状態を有するスイツチ、およびスイツチが第
2状態のとき作動してエレクトロクロミツク素子
に電源端子間に形成される高インピーダンス回路
を介して消色電圧を印加する消色電圧回路とから
なる。
The above problem has been solved according to the present invention by an ECD drive device which is provided with an erasing voltage circuit which consumes very little power during operation, separately from the ECD drive circuit. The configuration of the ECD drive device of the present invention includes a drive circuit for coloring and decoloring an electrochromic element, a switch having a first state in which the drive circuit is activated and a second state in which it is inactive, and a switch in which the switch is in a second state. and a color erasing voltage circuit which operates when the electrochromic element is in the state and applies a color erasing voltage to the electrochromic element via a high impedance circuit formed between the power supply terminals.

以下図面を参照して本発明の実施例について説
明する。
Embodiments of the present invention will be described below with reference to the drawings.

第1図3は本発明の第1の実施例のブロツク図
を示す。ECD駆動回路2と消色電圧回路3が
別々に存在し、ECD駆動中はECD駆動回路2は
電源1とECD4が連動したスイツチSW1,SW2
で結ばれている。スイツチSW1,SW2を消色電圧
回路3側につなげばECD4と消色回路3が結ば
れ、駆動回路2はoffになりECD4には消色電圧
が印加される。第4図は第一実施例の回路図であ
りスイツチSW1,SW2,SW3(このSW2,SW3
は第1図のSWxを構成する。)が図の実線の状態
にあるときECD駆動信号回路2Aに電源1から
の電圧が加わり、そして駆動電圧発生回路2Bは
VRの電圧を発生する。ECD4はECD駆動信号回
路2Aの着色信号SCあるいは消色信号SBにより着
色消色する。信号SCがハイレベルになつたときト
ランジスタTγ1と、インバータI1を通してトラン
ジスタTγ4がオン状態になりECD4に着色電圧が
加わりECD4は着色する。信号SBがハイレベル
のときはトランシスタTγ3,Tγ2がオン状態にな
り着色電圧とは極性が逆である消色電圧が印加さ
れる。信号SC,SBが両方ともローレベルのときト
ランジスタTγ1〜Tγ4は全てオフ状態となりECD
4の両端子はオープン状態になりメモリー性とな
り現在の状態を維持し続ける。今スイツチSW1
を点線側に接続すればダイオードD1〜D4、抵
抗γ1からなる消色回路3に電圧が加わる。スイ
ツチSW2,SW3も連動し点線側に接続し、ECD
4に抵抗γ1の端子間電圧である所定の消色電圧
が加わる。ダイオードD1〜D4はECD4の消
色時の抵抗が変化してもECD4自体に加わる電
圧を一定するためと消色電圧の大きさを決めるた
めに用いられている。即ち、ダイオードD1,D
2,D3およびD4の各々の端子間電圧は順方向
電圧として一定であるので抵抗γ1の端子間の電
圧は一定に維持される。抵抗γ1は消色電圧回路
3の消費電流が電池の自然電流に比べてあまり大
きくならない様に選ばれている。ECD4は電荷
注入素子であるので着色濃度が大きく変化しない
とき、たとえば消色状態が維持されるときは大き
な抵抗値を持つ抵抗体とみなすことができるので
ECD4自体の消色電圧印加継続時の消費電力は
充分に小さい。
FIG. 13 shows a block diagram of a first embodiment of the invention. An ECD drive circuit 2 and a color erasing voltage circuit 3 exist separately, and during ECD drive, the ECD drive circuit 2 operates through switches SW 1 and SW 2 in which the power supply 1 and ECD 4 are linked.
are tied together. If the switches SW 1 and SW 2 are connected to the erasing voltage circuit 3 side, the ECD 4 and the erasing circuit 3 are connected, the drive circuit 2 is turned off, and the erasing voltage is applied to the ECD 4. Figure 4 is a circuit diagram of the first embodiment, in which switches SW1, SW2 , SW3 ( SW2 , SW3
constitutes SW x in Figure 1. ) is in the state shown by the solid line in the figure, the voltage from the power supply 1 is applied to the ECD drive signal circuit 2A, and the drive voltage generation circuit 2B is
Generates a voltage of V R. The ECD 4 is colored and decolored by the coloring signal S C or decoloring signal S B of the ECD drive signal circuit 2A. When the signal S C becomes high level, the transistor Tγ 4 is turned on through the transistor Tγ 1 and the inverter I 1 , and a coloring voltage is applied to the ECD 4 to color the ECD 4 . When the signal S B is at a high level, the transistors Tγ 3 and Tγ 2 are turned on, and a decoloring voltage whose polarity is opposite to that of the coloring voltage is applied. When both signals S C and S B are at low level, transistors Tγ 1 to Tγ 4 are all turned off and ECD
Both terminals of 4 are in an open state and have a memory property and continue to maintain the current state. Now switch SW1
When connected to the dotted line side, a voltage is applied to the decoloring circuit 3 consisting of diodes D1 to D4 and resistor γ1. Switches SW 2 and SW 3 are also linked and connected to the dotted line side, and the ECD
A predetermined decoloring voltage, which is the voltage between the terminals of the resistor γ1, is applied to the resistor γ1. The diodes D1 to D4 are used to keep the voltage applied to the ECD 4 itself constant even if the resistance of the ECD 4 changes during erasing, and to determine the magnitude of the erasing voltage. That is, diodes D1, D
Since the voltage between the terminals of each of resistors 2, D3, and D4 is constant as a forward voltage, the voltage between the terminals of resistor γ1 is maintained constant. The resistor γ1 is selected so that the current consumption of the decolorizing voltage circuit 3 is not too large compared to the natural current of the battery. Since the ECD4 is a charge injection device, it can be regarded as a resistor with a large resistance value when the color density does not change significantly, for example when the decolored state is maintained.
The power consumption of the ECD 4 itself when the decoloring voltage is continuously applied is sufficiently small.

以上の回路によりECDの非駆動時にECDに所
定の大きさの消色電圧を加えることによりECD
の着色を押さえることができ、且つその際の消費
電力はわずかである。又、駆動時は消色回路3は
切断されているためメモリー性を利用した駆動法
も可能である。
With the above circuit, by applying a decoloring voltage of a predetermined magnitude to the ECD when the ECD is not driven, the ECD
Coloring can be suppressed, and the power consumption at that time is small. Furthermore, since the erasing circuit 3 is disconnected during driving, a driving method that utilizes memory properties is also possible.

第2図は第2実施例のブロツク図である。 FIG. 2 is a block diagram of a second embodiment.

第1の実施例との異なるところは消色電圧回路
3がECD駆動回路2のオン・オフにかかわらず
作動していることである。
The difference from the first embodiment is that the erasing voltage circuit 3 operates regardless of whether the ECD drive circuit 2 is on or off.

第5図は第2の実施例の回路図でありスイツチ
SW1が閉じられると第1の実施例のごとくECD
は駆動される。抵抗γ1〜γ3からなる消色電圧
回路3はスイツチSW1の開閉にかゝわらず作動
状態である。ECD4に着色電圧が印加されると
き、消色電圧回路3が同時に作動しているが
ECD駆動回路2に比べて出力インピーダンスが
非常に大きくなるように抵抗γ1〜γ3の値を選
んであるのでECD駆動回路2が作動していると
きは消色電圧回路3は無視できる。たヾしメモリ
ー性を考慮した駆動はできない。スイツチSW1
が開かれるとECD駆動回路2はオフ状態となり
ECDに消色電圧が印加される。
FIG. 5 is a circuit diagram of the second embodiment, and the switch
When SW1 is closed, ECD is activated as in the first embodiment.
is driven. The decoloring voltage circuit 3 consisting of resistors γ1 to γ3 remains in operation regardless of whether the switch SW1 is opened or closed. When the coloring voltage is applied to the ECD 4, the decoloring voltage circuit 3 is activated at the same time.
Since the values of the resistors γ1 to γ3 are selected so that the output impedance is much larger than that of the ECD drive circuit 2, the erasing voltage circuit 3 can be ignored when the ECD drive circuit 2 is operating. However, it is not possible to drive with memory performance in mind. switch SW1
When is opened, ECD drive circuit 2 is turned off.
A decoloring voltage is applied to the ECD.

第2の実施例は第1の実施例に比べスイツチの
数が少なくてよく、またECDに大きなリークが
生じたときも消色電圧回路3の消色電流はある値
(抵抗γ1とγ3で決まり、これらの抵抗が大き
ければ大きいほど、消色電流の流れが小さくな
り、抵抗が無限大ならば、電流はゼロになる)以
上にはならず電池の浪費を防止する。
The second embodiment requires fewer switches than the first embodiment, and even when a large leak occurs in the ECD, the erasing current of the erasing voltage circuit 3 is set to a certain value (determined by resistors γ1 and γ3). , the larger these resistances are, the smaller the flow of the bleaching current will be (if the resistance were infinite, the current would be zero), preventing battery waste.

第3図は第3の実施例のブロツク図である。
ECD4の駆動回路2の一部が消色電圧印加回路
を兼ねており駆動回路の電源1が切られたとき消
色回路が働くようになつており、第6図はその回
路例である。
FIG. 3 is a block diagram of a third embodiment.
A part of the drive circuit 2 of the ECD 4 also serves as a color erasing voltage application circuit, and the color erasing circuit is activated when the power source 1 of the drive circuit is turned off. FIG. 6 shows an example of the circuit.

スイツチSW1が閉じられるとECD駆動信号回
路2Aが作動し信号ScがハイレベルそしてSBがハ
イレベルのときトランジスタTγ4をオン状態に
しECD4に着色電圧が印加される。そののち信
号SCがローレベルそして信号SBがハイレベルのと
きECD4の端子はオープン状態になりメモリー
性により着色状態が維持される。SBがローレベル
のときトランジスタTγ5がオン状態になりECD
4に消色電圧が印加される。抵抗R3は抵抗R2
に較べて十分大きくしてあるのでスイツチSW1
が閉じているときは抵抗R3は無視される。
When the switch SW1 is closed, the ECD drive signal circuit 2A is activated, and when the signal S c is at a high level and the signal S B is at a high level, the transistor Tγ4 is turned on and a coloring voltage is applied to the ECD4. Thereafter, when the signal S C is at a low level and the signal S B is at a high level, the terminal of the ECD 4 is in an open state and the colored state is maintained due to the memory property. When S B is low level, transistor Tγ5 turns on and ECD
A decoloring voltage is applied to 4. Resistor R3 is resistance R2
Since it is sufficiently large compared to the switch SW1
When R3 is closed, resistor R3 is ignored.

スイツチSW1が開かれると抵抗R2,R3を
通してベース電流が流れトランジスタTγ5を能
動状態にする。そのためECDには消色電圧が印
加される。抵抗R3は第7図のように駆動信号回
路2Aに内含させることもできる。この場合はほ
とんど新しい回路を用いずに消色電圧を印加する
ことが可能となる。
When the switch SW1 is opened, a base current flows through the resistors R2 and R3 and activates the transistor Tγ5. Therefore, a decoloring voltage is applied to the ECD. The resistor R3 can also be included in the drive signal circuit 2A as shown in FIG. In this case, it becomes possible to apply a decoloring voltage without using almost any new circuit.

以上のごとく本発明は、ECD駆動回路と別に
設けられた低電力消費消色電圧回路によつて
ECD駆動装置の非駆動時に消色電圧をたえず印
加しつヾけることによりECDの着色の戻りを防
ぐこと、あるいはECDの消え残りを消色するこ
とが出きECDの着色による品位の低下、情報の
誤認を防ぐ効果を非駆動時の電力消費を大きくす
ることなく達成している。
As described above, the present invention utilizes a low power consumption decoloring voltage circuit provided separately from the ECD drive circuit.
By constantly applying a color erasing voltage when the ECD drive device is not driven, it is possible to prevent the ECD from returning to color, or to erase the remaining color of the ECD. This is achieved without increasing power consumption when not in use.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例のECD駆動装
置のブロツク図、第2図は本発明の第2の実施例
のECD駆動装置のブロツク図、第3図は本発明
の第3の実施例のECD駆動装置のブロツク図、
第4図は第1図の第1の実施例のブロツク図のよ
り具体的回路図、第5図は第2図の第2の実施例
のブロツク図のより具体的回路図、第6図は第3
図の第3の実施例のブロツク図のより具体的回路
図、および第7図は第6図の回路例の変形を示す
回路図である。 〔主要部分の符号の説明〕、エレクトロクロミ
ツク素子駆動回路……2、スイツチ……SW1
SW2、消色電圧回路……3。
FIG. 1 is a block diagram of an ECD drive device according to a first embodiment of the present invention, FIG. 2 is a block diagram of an ECD drive device according to a second embodiment of the present invention, and FIG. 3 is a block diagram of an ECD drive device according to a second embodiment of the present invention. Block diagram of the ECD drive device of the embodiment,
4 is a more specific circuit diagram of the block diagram of the first embodiment shown in FIG. 1, FIG. 5 is a more specific circuit diagram of the block diagram of the second embodiment shown in FIG. Third
A more specific circuit diagram of the block diagram of the third embodiment shown in the figure, and FIG. 7 is a circuit diagram showing a modification of the circuit example of FIG. 6. [Explanation of symbols of main parts], Electrochromic element drive circuit...2, Switch...SW 1 ,
SW 2 , color erasing voltage circuit...3.

Claims (1)

【特許請求の範囲】 1 エレクトロクロミツク素子を着・消色する駆
動回路、該駆動回路を作動させる第1状態とこれ
を非作動とする第2状態を有するスイツチ、およ
び該スイツチが第2状態のときに作動して該エレ
クトロクロミツク素子に電源端子間に形成される
高インピーダンス回路を介して消色電圧を印加す
る前記駆動回路より電力消費の少ない消色電圧回
路とからなるエレクトロクロミツク素子駆動装
置。 2 特許請求の範囲第1項に記載のエレクトロク
ロミツク素子駆動装置において、 前記消色電圧回路は電源端子間に接続された高
インピーダンス素子からなり、前記消色電圧は該
高インピーダンス素子によつて前記電源電圧を分
圧したものによつて得られていることを特徴とす
る装置。 3 特許請求の範囲第1項に記載のエレクトロク
ロミツク素子駆動装置において、 前記消色電圧回路は消色用電源端子間に前記エ
レクトロクロミツク素子と直列接続されたトラン
ジスタを含み、該トランジスタのベースは低イン
ピーダンス素子を介して前記駆動回路へ接続され
且つ高インピーダンス素子を介して該トランジス
タのコレクタに接続されており、該トランジスタ
は前記スイツチの第1状態において前記駆動回路
が作動中は該低インピーダンス素子を介してオフ
されそして前記スイツチの第2状態において前記
駆動回路が非作動中は該高インピーダンス素子を
介してオンされて前記エレクトロクロミツク素子
に消色電圧を印加していることを特徴とする装
置。
[Scope of Claims] 1. A drive circuit for coloring and decoloring an electrochromic element, a switch having a first state in which the drive circuit is activated and a second state in which it is inactive, and a switch in which the switch is in the second state. an electrochromic device comprising a color erasing voltage circuit which operates when the electrochromic device is in operation and applies a color erasing voltage to the electrochromic element via a high impedance circuit formed between power supply terminals, the power consumption of which is lower than that of the driving circuit; Drive device. 2. In the electrochromic device driving device according to claim 1, the color erasing voltage circuit includes a high impedance element connected between power supply terminals, and the color erasing voltage is generated by the high impedance element. A device characterized in that the device is obtained by dividing the power supply voltage. 3. In the electrochromic element driving device according to claim 1, the erasing voltage circuit includes a transistor connected in series with the electrochromic element between erasing power supply terminals, and the base of the transistor is connected to the drive circuit through a low impedance element and to the collector of the transistor through a high impedance element, the transistor being connected to the low impedance when the drive circuit is in operation in the first state of the switch. and is turned off via the high impedance element, and when the drive circuit is inactive in the second state of the switch, is turned on via the high impedance element to apply a color erasing voltage to the electrochromic element. device to do.
JP7016081A 1981-05-12 1981-05-12 Electrochromic element driver Granted JPS57185485A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7016081A JPS57185485A (en) 1981-05-12 1981-05-12 Electrochromic element driver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7016081A JPS57185485A (en) 1981-05-12 1981-05-12 Electrochromic element driver

Publications (2)

Publication Number Publication Date
JPS57185485A JPS57185485A (en) 1982-11-15
JPH045992B2 true JPH045992B2 (en) 1992-02-04

Family

ID=13423528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7016081A Granted JPS57185485A (en) 1981-05-12 1981-05-12 Electrochromic element driver

Country Status (1)

Country Link
JP (1) JPS57185485A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5256897A (en) * 1975-11-05 1977-05-10 Citizen Watch Co Ltd Drive circuit of electrochromic display device

Also Published As

Publication number Publication date
JPS57185485A (en) 1982-11-15

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