JPH0461529B2 - - Google Patents
Info
- Publication number
- JPH0461529B2 JPH0461529B2 JP57007184A JP718482A JPH0461529B2 JP H0461529 B2 JPH0461529 B2 JP H0461529B2 JP 57007184 A JP57007184 A JP 57007184A JP 718482 A JP718482 A JP 718482A JP H0461529 B2 JPH0461529 B2 JP H0461529B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- switching element
- terminal
- pulse
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
- H03K5/023—Shaping pulses by amplifying using field effect transistors
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明はパルス増幅回路、特にガス放電パネル
や電場発光素子（以下ELと略称する）などの表
示装置すなわち容量性負荷を駆動するために用い
られる高電圧パルス増幅回路に関する。[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a pulse amplification circuit, particularly a pulse amplifier circuit used for driving a display device such as a gas discharge panel or an electroluminescent device (hereinafter abbreviated as EL), that is, a capacitive load. The present invention relates to a high voltage pulse amplification circuit.
(b) 技術の背景
従来、上記のような表示装置を駆動するために
用いられていたパルス増幅回路は例えば第１図ａ
に示すようなものであつた。すなわちこれは第１
のスイツチング素子Qu（以下アツプスイツチング
素子と呼ぶ）と第２のスイツチング素子Qd（以下
ダウンスイツチング素子と呼ぶ）を主とし、上記
アツプスイツチング素子Quおよびリンギング防
止用の第１のダイオードD1とで１種のカソード
フオロワを形成してなる部分の出力端子２と、抵
抗RGおよびダウンスイツチング素子Qdからなり、
１種のインバータを形成してなる部分の点Ｐとの
間に導通路を与える第２のダイオードD2を接続
してなる回路を構成し、該回路の入力端子１には
例えば波高値が5V程度の入力パルス電圧Viを加
え、出力端子２から例えば波高値が100V程度の
出力パルス電圧Vpを取り出すものである。(b) Background of the technology The pulse amplification circuit conventionally used to drive the above-mentioned display device is shown in Fig. 1a, for example.
It was something like the one shown here. In other words, this is the first
The main components are a switching element Qu (hereinafter referred to as an up-switching element) and a second switching element Qd (hereinafter referred to as a down-switching element), the above-mentioned up-switching element Qu and a first diode D1 for ringing prevention. It consists of an output terminal 2 which forms a kind of cathode follower, a resistor R G and a down-switching element Qd,
A circuit is constructed by connecting a second diode D2 that provides a conductive path between the part forming a type of inverter and the point P, and the input terminal 1 of the circuit has a peak value of, for example, 5V. An input pulse voltage V i of about 100 V is applied to the output terminal 2, and an output pulse voltage V p having a peak value of about 100 V, for example, is taken out from the output terminal 2.
(c) 従来技術と問題点
ところで上記スイツチング素子Qu及びQdとし
ては、一般にバイポーラトランジスタや第１図ｂ
に示すような絶縁ゲート形電界効果トランジスタ
（以下MOSTと略称する）を用いた回路方式が考
えられている。ただしこの第１図ｂおよび前記第
１図ａの回路において、３は100V程度の電流供
給用電圧Vsを、また４は5V程度のゲートバイア
ス電圧VGを、それぞれ供給する端子であり、Cp
として示したものは前記表示素子の等価容量であ
る。(c) Prior art and problems By the way, the above-mentioned switching elements Qu and Qd are generally bipolar transistors or
A circuit system using an insulated gate field effect transistor (hereinafter abbreviated as MOST) as shown in the figure is being considered. However, in the circuits shown in FIG. 1b and FIG. 1a, 3 is a terminal that supplies a current supply voltage Vs of about 100V, and 4 is a terminal that supplies a gate bias voltage VG of about 5V, respectively. p
What is shown as is the equivalent capacitance of the display element.
ところで、特にマトリツクス型ガス放電パネル
においては、プラズマ放電の開始電圧が複数から
なる表示用電極ごとに少しずつ相違するものであ
るが、このわずかずつの相違を適切に補正するた
めには、上記各表示電極に接続される個々のパル
ス増幅回路の出力パルス電圧Vpを適宜調整する
ことが必要となる。 By the way, especially in matrix type gas discharge panels, the starting voltage of plasma discharge differs slightly for each display electrode made up of a plurality of display electrodes, and in order to appropriately correct for these slight differences, it is necessary to It is necessary to appropriately adjust the output pulse voltage V p of each pulse amplification circuit connected to the display electrode.
しかし、こうしたきめの細かい電圧調整は例え
ば第１図ｂに示したような単純な回路を用いるこ
とによつては不可能であつた。 However, such fine-grained voltage regulation has not been possible using a simple circuit such as that shown in FIG. 1b.
(d) 発明の目的
本発明は上記従来の欠点に鑑みてなされたもの
で、ガス放電パネルの各表示電極に供給される
個々の出力パルス電圧Vpを精密に調整しうるパ
ルス増幅器を提供することを目的とする。(d) Object of the Invention The present invention has been made in view of the above-mentioned conventional drawbacks, and provides a pulse amplifier capable of precisely adjusting the individual output pulse voltages V p supplied to each display electrode of a gas discharge panel. The purpose is to
(e) 発明の構成
この目的は、電流供給用電源と出力端子との間
につながれたアツプスイツチング素子と該アツプ
スイツチング素子の出力端子と接地間につながれ
たダイオードおよび上記出力端子とアツプスイツ
チング素子の入力端子との間に導通路を与えるダ
イオードを有し、かつ前記アツプスイツチング素
子の入力端子と接地間につながれたダウンスイツ
チング素子を有してなる増幅回路において、前記
アツプスイツチング素子の入力端子を上記電流供
給用電源の電圧よりも低い電圧を有する別の電源
に接続し、該アツプスイツチング素子のオン動作
時にその出力端子から前記別の電源の電圧とほぼ
同レベルの電圧を出力させるように構成してなる
ことを特徴とするパルス増幅回路を提供すること
によつて達成される。(e) Structure of the Invention The object of the present invention is to connect an up-switching element connected between a current supply power source and an output terminal, a diode connected between the output terminal of the up-switching element and ground, and a switch between the output terminal and the up-switching element. In the amplifier circuit, the amplifier circuit has a diode providing a conductive path between the input terminal of the up-switching element and a down-switching element connected between the input terminal of the up-switching element and ground. The input terminal of the element is connected to another power supply having a voltage lower than the voltage of the current supply power supply, and when the up-switching element is turned on, a voltage of approximately the same level as the voltage of the other power supply is applied from the output terminal. This is achieved by providing a pulse amplification circuit characterized in that it is configured to output.
(f) 発明の実施例 以下本発明の実施例を図面によつて詳述する。(f) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.
第２図ａは本発明に係るパルス増幅回路の一実
施例を示す図であるが、第１図ｂと同等部位には
同一符号を付す。 FIG. 2a is a diagram showing an embodiment of the pulse amplification circuit according to the present invention, and the same parts as in FIG. 1b are given the same reference numerals.
この第２図ａが先の第１図ｂと異なる所は、ア
ツプスイツチング素子QuとしてのアツプMOSト
ランジスタのゲートバイアスは所定の回路素子と
しての抵抗RGを介して端子３につながれておら
ず別に設けられた端子７に接続されている点で、
しかも上記端子７に印加される電圧VGは端子３
で印加され電圧Vsのように例えば100V一定では
なく、当該電圧Vsよりも低い値に設定されてお
り、しかもその電圧VGは用いられるパルス増幅
器ごとに例えば92V，97V，95V……のように上
記電圧Vsより低く、かつ変化させるように設定
されていることである。そしてこの変化させて印
加される電圧VGは、前記したようにいくらかず
つ異なるプラズマ放電開始電圧Vpに対応する値
となつている。 The difference between FIG. 2 a and the previous FIG. 1 b is that the gate bias of the up MOS transistor as the up switching element Qu is not connected to the terminal 3 via the resistor R G as a predetermined circuit element. In that it is connected to a separately provided terminal 7,
Moreover, the voltage V G applied to the terminal 7 is
The applied voltage V s is not constant, for example, 100 V, but is set to a lower value than the voltage V s , and the voltage V G varies, for example, 92 V, 97 V, 95 V, etc., depending on the pulse amplifier used. The voltage V s is set to be lower than the voltage V s and to be changed as shown in FIG. The voltage V G that is applied while changing has a value that corresponds to the plasma discharge starting voltage V p that differs somewhat as described above.
このように電圧VGのレベルを電圧Vsよりも低
く設定しておけば第２図ｂに示したような入力パ
ルス電圧Viが端子１に加わつた場合出力パルス電
圧Vpの波高値は第２図ｂに示したように電圧VG
よりも高くなることはない。 If the level of voltage V G is set lower than voltage V s in this way, when input pulse voltage V i is applied to terminal 1 as shown in Figure 2b, the peak value of output pulse voltage V p will be As shown in Figure 2b, the voltage V G
It cannot be higher than.
この理由は出力パルス電圧Vpのレベルが仮に
電圧VGのレベルよりも高くなろうとするとアツ
プスイツチングMOSトランジスタのゲート端子
すなわち点Ｐの電圧がVGにクランプされている
ために該MOSトランジスタがオフ状態となり、
さらにダイオードD2によつて出力パルス電圧の
レベルは電圧VGにクランプされてしまうためで
ある。 The reason for this is that if the level of the output pulse voltage Vp were to become higher than the level of the voltage VG , the voltage at the gate terminal of the up-switching MOS transistor, that is, the voltage at point P, would be clamped to VG . It is in the off state,
Furthermore, the level of the output pulse voltage is clamped to the voltage VG by the diode D2 .
すなわちこのようにしておくことによつて、ガ
ス放電パネルの各表示電極に供給される個々の出
力パルス電圧Vpは、当該パネルの放電開始電圧
の少しずつの相違によく対応できるようになり、
その結果、上記パネルにおける各部分の輝度は精
密に揃えられて均一なものとなる。 In other words, by doing this, the individual output pulse voltages V p supplied to each display electrode of the gas discharge panel can better respond to slight differences in the discharge starting voltage of the panel.
As a result, the brightness of each part of the panel becomes precisely aligned and uniform.
また第３図に示したものは本発明の変形実施例
であつて、アツプスイツチング素子Quたるアツ
プMOSトランジスタのゲートバイアス電圧は先
の第１図ｂと同じく抵抗RG1を介して端子３から
供給されている。しかしここで第３図中のＰ点は
可変抵抗RG2を介して接地されている所が異なつ
ている。このためにアツプMOSTのゲートバイ
アス電圧は端子３に印加される100V程度の電圧
Vsを抵抗RG1，RG2で分割したものとなり、当然
電圧Vsよりも低いものとなるし、抵抗RG2を半固
定式にしておけば、ガス放電パネルの各表示電極
ごとにつながるこの第３図に示したようなパルス
増幅器の出力パルス電圧Vpは、たとえ電圧Vsが
100Vなる一定値を持つものであつても種々の値
に変化させうるので、結局、この第３図の変形実
施例は第２図ａに示したものと同一の効果を発揮
することになる。 The one shown in FIG. 3 is a modified embodiment of the present invention, in which the gate bias voltage of the up MOS transistor serving as the up switching element Q is applied from the terminal 3 via the resistor R G1 as in FIG. 1 b. Supplied. However, the difference here is that point P in FIG. 3 is grounded via a variable resistor R G2 . For this reason, the gate bias voltage of UP MOST is approximately 100V applied to terminal 3.
V s is divided by the resistors R G1 and R G2 , which is naturally lower than the voltage V s . If the resistor R G2 is semi-fixed, this voltage will be connected to each display electrode of the gas discharge panel. The output pulse voltage V p of a pulse amplifier as shown in Fig. 3 is
Even though it has a constant value of 100V, it can be changed to various values, so that the modified embodiment shown in FIG. 3 has the same effect as that shown in FIG. 2a.
(g) 発明の結果
以上、詳細に説明したように、本発明に係るパ
ルス増幅回路は該回路の出力パルス電圧を回路ご
とに微細に調整することができ、そのためにガス
放電パネルの表示電極ごとに生じている放電開始
電圧の相違（バラツキ）を完全に補正することが
できるようになり、したがつて上記パネルにおけ
る各部分の輝度は精密に揃えられて均一なものに
できる。(g) Results of the Invention As explained above in detail, the pulse amplification circuit according to the present invention can finely adjust the output pulse voltage of the circuit for each circuit, and therefore It becomes possible to completely correct the differences (dispersions) in the discharge starting voltage that occur in the panel, and therefore the brightness of each part of the panel can be precisely aligned and made uniform.
第１図ａ，ｂは従来のパルス増幅回路を示す
図、第２図ａ，ｂは本発明に係るパルス増幅回路
と該回路中の電圧パルス波形を示す図、第３図は
本発明の変形実施例を示す図である。
１，２，３，４，７……は端子、Qd……ダウ
ンスイツチング素子、Qu……アツプスイツチン
グ素子、D1，D2……ダイオード。
FIGS. 1a and 1b are diagrams showing a conventional pulse amplification circuit, FIGS. 2a and 2b are diagrams showing a pulse amplification circuit according to the present invention and voltage pulse waveforms in the circuit, and FIG. 3 is a modification of the present invention. It is a figure showing an example. 1, 2, 3, 4, 7... are terminals, Qd...down switching element, Qu...up switching element, D1 , D2 ...diode.
Claims (1)
たアツプスイツチング素子と該アツプスイツチン
グ素子の出力端子と接地間につながれたダイオー
ドおよび上記出力端子とアツプスイツチング素子
の入力端子との間に導通路を与えるダイオードを
有し、かつ前記アツプスイツチング素子の入力端
子と接地間につながれたダウンスイツチング素子
を有してなる増幅回路構成において、 前記アツプスイツチング素子の入力端子を上記
電流供給用電源の電圧よりも低い電圧を有する別
の電源に接続し、該アツプスイツチング素子のオ
ン動作時にその出力端子から前記別の電源の電圧
とほぼ同レベルの電圧を出力させるように構成し
てなる ことを特徴とするパルス増幅回路。[Scope of Claims] 1. An up-switching element connected between a current supply power source and an output terminal, a diode connected between the output terminal of the up-switching element and ground, and an up-switching element connected between the output terminal and the up-switching element. In an amplifier circuit configuration comprising a diode providing a conductive path between the up-switching element and the input terminal, and a down-switching element connected between the input terminal of the up-switching element and ground, The input terminal is connected to another power supply having a voltage lower than the voltage of the current supply power supply, and when the up-switching element is turned on, a voltage approximately at the same level as the voltage of the other power supply is output from the output terminal. A pulse amplification circuit characterized in that it is configured to cause
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP718482A JPS58124324A (en) | 1982-01-19 | 1982-01-19 | Pulse amplifying circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP718482A JPS58124324A (en) | 1982-01-19 | 1982-01-19 | Pulse amplifying circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58124324A JPS58124324A (en) | 1983-07-23 |
| JPH0461529B2 true JPH0461529B2 (en) | 1992-10-01 |
Family
ID=11658968
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP718482A Granted JPS58124324A (en) | 1982-01-19 | 1982-01-19 | Pulse amplifying circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58124324A (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5547494A (en) * | 1978-09-30 | 1980-04-03 | Tokyo Shibaura Electric Co | Control rod drive mechanism |
| JPS601779B2 (en) * | 1979-11-20 | 1985-01-17 | 富士通株式会社 | pulse circuit |
-
1982
- 1982-01-19 JP JP718482A patent/JPS58124324A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58124324A (en) | 1983-07-23 |
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