JPH0462181B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a semiconductor photodetection device using an SIT (static induction type transistor), and in particular, the gate is a first gate for signal readout and a second gate for providing a potential reference. It is divided into two gates.
Concerning improvements to semiconductor photodetection devices using SIT.

BACKGROUND ART Regarding a semiconductor photodetection device using SIT, such as a solid-state imaging device, the most basic device is disclosed as a starting technology in Patent Application Publication No. 15229 of 1980, and a further improved version of this device is disclosed. Various proposals have been made, including Patent Application No. 204656 of 1982.

By the way, solid-state imaging devices that use a gate-split type SIT have the excellent ability to change the output characteristics during signal readout by controlling the voltage applied to the shielding gate (or floating gate). It has its features. In order to fully utilize this feature, it is preferable that the potential of the shielding gate does not change even when light enters each cell.

In FIG. 1A, a source region 1 made of an n ⁺ layer is formed in a channel region 2 made of an n ⁻ layer, and a shielding gate region 3A made of a p ⁺ layer and a control The main part of the solid-state imaging device in which the gate region 3B is formed is shown in fragments as a concept necessary for understanding the band structure. The structure of the valence band in such a configuration is shown in Figure 1B,
The area near the source region has the lowest potential and is called a true gate. When light enters a solid-state imaging device with such a band structure from the outside, electron-hole pairs are generated and the holes are accumulated in the control gate region 3B, as shown in FIG. 1C. As shown, the potential of the control gate region 3B is lowered, and a difference of ΔE ₁ occurs with respect to the potential of the shielding gate region 3A. Conversely, when holes are accumulated in the shielding gate region 3A, the potential of the shielding gate region 3A decreases, as shown in _FIG. It makes a difference. If the potential of the shielding gate region 3A is taken as a reference, the potential of the control gate region 3B will be relatively increased by ΔE ₂ .

On the other hand, the signal readout current corresponds to the band change due to the accumulation of holes as shown in FIG. 1C or D. Therefore, in the case shown in FIG. 1D, even if no holes due to incident light are accumulated in the control gate region 3B, a signal may be output as if light had been incident. There is sex. FIG. 1E shows a band structure including control gate regions 3C of adjacent cells. In this figure, the holes generated when light enters the cell on the left are:
Most of the holes are accumulated in the control gate region 3C, but some of the holes are also accumulated in the shielding gate region 3A. Therefore, the potential of the control gate region 3C decreases as indicated by the arrow F1, and the potential of the shielding gate region 3A also decreases by ΔE as indicated by the arrow F2.

As described above, when the potential of the shielding gate region 3A changes, the output characteristics during signal readout change as described above.
As a result, a problem arises in that control of the output characteristics by applying a predetermined voltage to the shielding groove region 3A is disturbed. Also, in reality,
Signals are also read out from cells with no incident light, resulting in a smearing phenomenon on the reproduced image.

Furthermore, if carriers (holes in the above example) generated by the incident light are accumulated in the shielding gate region, the output signal for weak incident light becomes smaller, resulting in a decrease in sensitivity. .

Purpose The present invention improves the drawbacks of the prior art, reduces the accumulation of carriers in the shielding gate region, and improves the photodetection sensitivity by increasing the efficiency of carrier accumulation in the control gate region. The object of the present invention is to provide a semiconductor photodetection device that can improve the output characteristics of the shielding gate region by suppressing fluctuations in the potential of the shielding gate region caused by incident light and controlling the output characteristics well. .

DISCLOSURE OF THE INVENTION According to the present invention, a steep potential barrier is formed at the boundary between the shielding gate region and the channel region by providing a material such as an insulating layer with a larger forbidden band width than the channel. This suppresses the accumulation of carriers at the shielding gate.

According to another embodiment of the invention, the suppressing means is achieved by applying a voltage to the shielding gate region through a steep (discontinuous) potential barrier formed by an insulating layer or the like. In addition to the potential barrier formed by one of the source and drain regions located adjacent to the shielding gate region.

According to yet another embodiment of the present invention, the suppressing means includes a shielding gate region of the same conductivity type as the channel region in a steep (discontinuous) potential barrier formed by an insulating layer or the like. A potential barrier formed by applying a pulsed voltage to the voltage is added.

According to a further embodiment of the invention, the suppression means comprises, in addition to the above-described potential barrier, an optical layer which prevents light from entering the shielding gate region.

DESCRIPTION OF EMBODIMENTS Next, embodiments of a semiconductor photodetection device according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows an embodiment of an imaging device, which is a semiconductor photodetection device using SIT according to the present invention. In this figure, A is a partially cutaway plan view, and B is an end view of A as viewed from the direction of the arrow in the plan view. In this figure B, components that connect each cell are omitted to avoid complicating the diagram. Further, the end face of a cell corresponding to one pixel, which corresponds to FIG. 2B, is shown enlarged in FIG.

In these figures 2A, B and 3, impurity density using materials such as silicon (Si) is high.
A channel region 12 made of an n ^- layer with low impurity density is formed on the n ⁺ layer substrate 10 .

A control gate region 14 made of a p ⁺ layer with high impurity density is provided on the upper surface of the n ⁻ layer where the channel region 12 is formed. A source region 16 made of an n ⁺ layer with high impurity density is provided around the control gate region 14 . These control gate areas 1
As shown in FIG. 2A, the control gate regions 14 and source regions 16 are arranged in a regular two-dimensional matrix at appropriate intervals. A cell corresponding to one pixel is formed.

Between adjacent source regions 16 is a shielding gate region 1 made of a p ⁺ layer with high impurity density.
8 is formed. An insulating layer 18I is formed at the boundary between the seeding gate region 18 and the channel region 12. Further, a shielding gate electrode 18E is connected to the shielding gate region 18 so that an appropriate voltage can be applied from the outside.

Next, a channel region 12 is formed.
On the top surface of the n ^- layer, a control gate region 14,
Silicon oxide (SiO ₂ ) throughout except for some exposed parts of the source region and shielding gate region
A film (hereinafter simply referred to as "oxide film") 20 is formed for surface protection. A source electrode 22 is formed in an exposed portion of the source region 16 to connect adjacent cells. The direction of this connection is
As shown in FIG. 2A, this is a direction that intersects the connection direction of control gate electrodes, which will be described later.

Next, a transparent control gate electrode 24 is formed on the exposed portion of the control gate region 14 with an insulating layer 26 interposed therebetween. Insulating layer 26
is made of, for example, an oxide film, and the source electrode 22
It is extended upwards. A control gate electrode 24 is formed along this insulating layer 26. That is, the control gate region 14 and the control gate electrode 2 are separated by the insulating layer 26.
A capacitor is formed between the source electrode 22 and the shielding gate electrode 18E.
The control gate electrodes 24 are insulated from each other. This control gate electrode 2
The connection direction of cell 4 and the connection direction of source electrode 22 intersect, thereby making it possible to read out information stored in any of the cells. That is, by selecting any one of the plurality of source electrodes 22 and selecting any one of the plurality of control gate electrodes 24, a cell at a position where both electrodes intersect is selected. A drain electrode 28 is formed on the side of the substrate 10 opposite to the n ^- layer where the channel region 12 is formed.

The shielding gate electrode 18E is connected at a portion not shown, so that a predetermined voltage can be applied to the entire shielding gate region 18.

Next, the electrical equivalent circuit of the imaging device having the above-described structure, the connection between each electrode, and the connection with the driving means will be explained.

FIG. 4A shows the electrical circuit and connections to external devices. A portion of this connection is also shown in FIG.

First, symbols representing cells shown in FIG. 4A will be explained with reference to FIG. 4B.
In this figure, SA represents a channel, to which a source electrode 22 and a drain electrode 28 are connected. SB represents the control gate region 14, and SC1 represents a capacitor formed by the insulating layer 26, to which the control electrode 24 is connected. Furthermore, SD represents a shielding gate region 18, to which a shielding gate electrode 18E is connected. SC2 is
It represents a capacitor formed by an insulating layer 18I.

Next, in FIG. 4A or FIG. 3, a plurality of cells PC corresponding to pixel units are arranged in a two-dimensional matrix as shown in FIG. 2A. The plurality of control gate electrodes 24 include
The read address circuits 30 are connected to each other,
A reading pulse voltage is applied sequentially to each horizontal row. On the other hand, a plurality of source electrodes 2
2 is a transistor 40 that performs a switching operation.
, and their sources are each connected to an output terminal 38. The gates of the transistors 40 are each connected to the video line selection circuit 32. The video line selection circuit 32 sequentially outputs selection pulse voltages to the transistors 40, thereby sequentially driving the transistors 40.

For example, the transistor 40 is normally “OFF”
The read address circuit 30 and the video line selection circuit 3 are configured by the SIT in the state of
2 is constituted by, for example, a shift register.

Further, an output resistor 34 and a power source 36 are connected between the output terminal 38 and the ground, that is, the drain electrode 28 . The shielding gate electrode 18E of each cell PC is connected to another variable power source of 36V.
is connected. This variable power supply 36V includes, for example, a variable resistor VR, a voltage variable power supply VE, and a variable capacitance capacitor VC.

Next, regarding the overall operation of the above-mentioned embodiment,
The explanation will be made with reference to FIGS. 5 and 6 in addition to FIGS. 2 to 4. Note that the substrate 10 is shown in FIG.
The outline of the band structure from the n ⁺ layer to the control gate region 14 is shown in FIG.
A band structure from the control gate region 14 to the shielding gate region 18 is schematically shown.

First, when light enters each cell PC, electron-hole pairs are generated in the potential gradient portion formed from the channel region 12 to the control gate region 14, as shown in FIG. Ru. Specifically, the incident light hν mainly passes through the control gate region 14 and reaches the channel region 12, and electrons E are excited to the conduction band CB.
Holes H are generated in the valence band VB. Electronic E
moves in the direction of the drain electrode 28, and the hole H
moves toward the control gate region 14 and is accumulated.

On the other hand, since the band structure extending from the channel region 12 to the shielding gate region 18 is approximately the same as that shown in FIG.
It will also move in the direction of 8.

On the other hand, considering the band structure centered on the source region 16, as shown in FIG. 6, the potential is low in the source region 16 and the control gate region 14 and shielding gate region
8, the potential increases as the shielding gate region 18 increases.
An insulating layer 18 is provided at the boundary between the channel region 12 and the channel region 12.
A steep potential barrier is formed by I. A positive voltage is applied to the shielding gate region 18 by a variable power supply of 36V (see FIG. 4A). Therefore, the shielding gate region 18 and the band in its vicinity are indicated by the arrow F in FIG.
Go down in the direction of 3.

Therefore, the holes H moving in the direction of the shielding gate region 18 move in the direction of the control gate region 14 along the valence band VB and are accumulated, but are not accumulated in the shielding gate region 18. .

Furthermore, even when the voltage from the variable power supply 36V is not applied, the shielding gate region 1 is
The accumulation of holes H in 8 will be greatly reduced.

Due to the above action, the accumulation of holes H in the shielding gate region 18 is suppressed, that is, there is almost no change in the potential of the shielding gate region 18, and a carrier is provided to each control gate region 14. Holes H are accumulated and image information is accumulated for each cell PC.
Next, the transistor 4 connected to the plurality of source electrodes 22 by the video line selection circuit 32
Selective pulse voltages are sequentially applied with respect to 0. This drives the corresponding transistor 40,
The source electrodes 22 and drain electrodes 28 of a plurality of cells PC arranged in the corresponding column direction among the cells PC shown in FIG. 4A are connected to a power source 36 via a resistor 34. This completes the preparation for the flow of source-drain current. In this state, for example, the voltage of the power supply 36 is adjusted so that each cell PC maintains a non-conductive state.

Through the above operations, a video line from which image information is to be read is selected. Next, the read address circuit 30 selects a plurality of gate electrodes 2.
4, a pulse voltage is applied in sequence. The cell located on the video line selected by this
The PCs are driven one after another, and a source-drain current corresponding to the amount of holes H accumulated in the control gate region 14, that is, the amount of incident light, flows through the resistor 34, and is further converted into a voltage and output to the output terminal 38. That will happen.

The above operations are performed for each video line, and image information corresponding to the incident light is output to the output terminal 38.
This results in a good output as a voltage change.
Furthermore, the potential of the shielding gate region 18 is
Since there is little change, its output characteristics are maintained at well-set characteristics.

As described above, according to this embodiment, each cell PC
The separation between the channels is extremely good, the carriers generated by the incident light are accumulated effectively, and the space where the channels are formed is effectively used. These effects can be further improved. In order to achieve this, it is preferable to take the following consideration into the formation of the insulating layer 18I.

First, the material used for the insulating layer 18I is, for example, silicon oxide (SiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), or silicon nitride (SiN,
Si ₃ N ₄ ) is used. The thickness of this insulating layer 18I is
If it is too thin, it loses its meaning as an insulating layer due to the tunnel effect, and if it is too thick, the influence of the voltage applied to the shielding gate electrode 18E on the channel region 12 becomes too weak, which is not preferable.
The thickness of the insulating layer 18I is set in consideration of these points, and when silicon oxide is used, it is set to, for example, 300 Å to 1000 Å. Since silicon nitride has a higher dielectric constant than silicon oxide, the dielectric constant is, for example, 40 Å to several 100 Å.

Next, it is preferable that the distance between the insulating layer 18I and the source region 16 takes into account the Debye length. In other words, by setting the distance within the Debye length determined by the impurity density of the channel region 12, changes in the potential of the shielding gate region 18 can be favorably influenced by the potential of the channel region 12, thereby improving the output characteristics. can be easily controlled.

Next, a modification of the above-described embodiment will be described with reference to FIGS. 7 and 8. In the above embodiment, the accumulation of holes H in the control gate region 14 is extremely effective, and the sensitivity to weak incident light is greatly improved.
It is relatively weak against so-called blooming, which is caused by the generation of a large amount of carriers due to strong incident light. The following modification example takes such blooming into consideration.

FIG. 7 shows a portion of a semiconductor layer of a modified example, and FIG. 8 shows a cross section taken along the - line in this figure. Note that the same reference numerals will be used for the same components as in the above-described embodiment, and the explanation thereof will be omitted.

In this modification, a buried layer consisting of a mesh-like p ⁺ layer is formed below the shielding gate region 18 and at the boundary between the n ⁺ layer of the substrate 10 and the n ^- layer where the channel region 12 is formed. 18A is provided.

FIG. 9 shows the shielding gate region 18 in this configuration from the p ⁺ layer to the substrate 10.
An overview of the band structure up to the n ⁺ layer is shown. When a positive voltage is applied to the shielding gate region 18 by the variable power source 36V (see FIG. 4A), the band near the shielding gate region 18 moves in the direction of arrow F4 in FIG. 9 as shown in FIG. It will go down as explained. As is clear from this band structure, the potential of the buried layer 18A is partially high, so that the holes H are absorbed. Basically, the holes H generated by the incident light are in the control gate region 1.
However, when it reaches a saturated state, the holes H are absorbed into the buried layer 18A. Therefore,
The occurrence of blooming is well suppressed. Since the buried layer 18A is formed in a mesh shape, the area of the potential slope portion formed at the boundary with the channel region 12 is enlarged, and holes H are well absorbed.

Note that if the buried layer 18A is provided over a too wide area, it will absorb more holes H than necessary, which will cause a decrease in sensitivity. Therefore, when forming the buried layer 18A, it is preferable to give sufficient consideration to such points, especially the degree of expansion of the depletion layer formed in the channel region 12 by the buried layer 18A.

FIG. 10 shows an embodiment in which the present invention is applied to a line sensor. Note that the same reference numerals are used for the same components as in the above-described embodiment, and the explanation thereof will be omitted.

In this embodiment, the source region 16L is formed continuously and commonly for each cell, and the same is true for the source electrode 22L. The shielding gate region 18L is the control gate region 14
A part of the surrounding area has been removed.

In the line sensor, unlike the imaging device, selection of video lines is not required, so the above-mentioned simple configuration can be achieved. Therefore, the video line selection circuit 32L and the transistor 40L
Although not necessarily required, it is illustrated for comparison with the embodiment described above.

Next, another embodiment will be described in which prevention of carrier accumulation in the shielding gate region is further improved. This embodiment is shown in FIGS. 11A and 11B, in which FIG. 11A is a plan view corresponding to FIG. 2A, and FIG. 11B is an end view corresponding to FIG. 2B. FIG. 11 is a view seen from the arrow in FIG. 11A. In this embodiment, the same reference numerals are used for the same components as in the above-described embodiment, and the explanation thereof will be omitted.

In the embodiment shown in FIGS. 11A and 11B, source region 46 is provided in close proximity to shielding gate region 18. In the embodiment shown in FIGS. That is, if the distance between the source region 46 and the shielding gate region 18 is WA, and the distance between the source region 46 and the control gate region 14 is WB, then WA<
It becomes a WB relationship. In this way, in the band structure shown in FIG.
The position with the lowest potential, that is, the true gate position at 6 moves to the left in the figure, and the holes H become more effectively stored in the control gate region 14.

Furthermore, in this embodiment, an insulating film 42 is formed on the source region 46 and the shielding gate region 18.
An aluminum film 44 is formed through the aluminum film. Therefore, the shielding gate area 18
No light enters the channel region 12 from the portion , and carriers (holes H in this embodiment) are not accumulated in the shielding gate region 18 . Note that in this embodiment, the shimmering film 4
4 is connected to the shielding gate region 18 through the through hole portion 20H of the oxide film 20, and also serves as a shielding gate electrode.
This shimmering film 44 covers the control gate electrode 2.
It is not necessary to provide it on the lower side of 4, but it may be provided on the upper side.

As described above, according to this embodiment, the isolation between the cells PC is further improved.
This can also be achieved by deeply forming
It can also be achieved by making the impurity density of the shielding gate region higher than that of the control gate region 14.

By using any one of the above configurations or a combination of multiple configurations, it is possible to improve the separation between cell PCs, and the cell PCs arranged per unit area can be improved.
The degree of integration can be significantly improved.

Still another embodiment of the invention is shown in FIGS. 12 and 13. In this embodiment, shielding gate region 18B has a high impurity density.
It is formed of an n ⁺ layer and is not directly connected to the shielding gate electrode 18E.

A negative pulse voltage is applied to the shielding gate electrode by a power source 36W. As a result, electrons existing in the shielding gate region 18B are discharged, and the electrons existing in the shielding gate region 18B are discharged.
As a result, it becomes positively charged and its potential changes as shown by arrow F3 in FIG. Therefore, like the embodiments described above, the accumulation of carriers in the shielding gate region 18B is reduced.

The thickness of the insulating layer 18BI in this shielding gate region 18B is not fundamentally different from that of the insulating layer 18I in the embodiment described above. That is, as shown in FIG.
Both the thicknesses Δt ₁ and Δt ₂ are, for example, 300 Å to 1000
It is set to about Å.

In all of the above embodiments, the channel is formed by the n ^-layer , but it is
A channel may be formed by the p ^- layer, and the conductivity types of other constituent parts may be changed accordingly. The source and drain may be made to correspond inversely to those in the above embodiment, and the same effect will be achieved.

Further, the driving transistor 40 may be a normal transistor, and this transistor 4
It is also optional to integrate the 0, read address circuit 30, and video line selection circuit 32 with the imaging device to form an integrated circuit.

Although the above-mentioned embodiments relate to an area sensor using a two-dimensional matrix or a line sensor using a one-dimensional array, it goes without saying that it can also be operated as a photodetector using only a single cell, that is, a phototransistor.

Silicon was mainly used as the material, but
Other materials such as germanium, - group compound semiconductors, etc. can also be used.

In addition, the characteristics of the SIT include a normally OFF type in which the channel is non-conducting in a thermal equilibrium state with no external voltage applied, and a normally ON type in which the channel is conductive in a thermal equilibrium state. Good too.

Furthermore, the shape of each part in the above embodiments may be arbitrary within the range of having similar functions.
In the embodiment shown in , the control electrode 24 may cover the insulating layer 26 . In this way, the controllability of the voltage applied to the control gate electrode 24 is improved, and the margin for mask alignment in the manufacturing process is improved.

In addition, in order to obtain color image information, a matrix of cells is configured to correspond to, for example, red (R), green (G), and blue (B), and the incident light is filtered through color filters. The B light may be separated and made to enter each corresponding cell.

Effects As described above, according to the present invention, since a means for suppressing the accumulation of carriers generated by incident light is formed in the shielding gate region, potential fluctuations in the shielding gate region are suppressed. is effectively suppressed, and the controllability of the output characteristics is improved. In addition, the separation between each cell is improved, and as a result, the photodetection sensitivity can be improved, which is an excellent effect.

[Brief explanation of the drawing]

1A to 1E are explanatory diagrams showing changes in the potential of the shielding gate region due to incident light; FIG. 2A is a partially cutaway plan view showing an embodiment of the imaging device according to the present invention; FIG. B is same figure A
3 is an enlarged sectional view of one unit of cells in FIG. 2B, and FIG. 4A is a circuit diagram showing an electrical equivalent circuit as a two-dimensional imaging device. , FIG. 4B is an explanatory diagram for explaining the symbol of one imaging cell, FIG. 5 is an explanatory diagram showing the band structure from the n ⁺ layer of the substrate to the p ⁺ layer of the control gate region, and FIG. 6 is an explanatory diagram for explaining the symbol of one imaging cell. From the p ⁺ layer in the control gate region to the p ⁺ layer in the shielding gate region
FIG. 7 is a partially cutaway perspective view showing a modification of the present invention; FIG. 8 is a perspective view showing a cross section taken along line - in FIG. 7;
9 is an explanatory diagram showing the band structure in the example of FIG. 8, FIG. 10 is a partially cutaway plan view showing an embodiment of the line sensor according to the present invention, and FIG. 11A is an explanatory diagram showing the band structure in the example of FIG. 11B is a plan view showing the embodiment, FIG. 11B is an end view taken from arrow XI in FIG. 11A, FIG. 12 is a sectional view showing still another embodiment of the present invention, and FIG. FIG. 3 is an explanatory diagram showing an enlarged view of a ding gate portion. Explanation of symbols of main parts, 12... Channel area, 14... Control gate area, 16, 1
6L... Source area, 18, 18B, 18L...
Shielding gate region, 18A...buried layer,
18I, 18BI...Insulating layer, 44...Shining film,
H...hole, hν...incident light, PC...cell.

Claims (1)

[Scope of Claims] 1. A source region and a drain region consisting of a semiconductor region of one conductivity type with high impurity density, a channel region consisting of a semiconductor region of one conductivity type with low impurity density between the source region and the drain region, The transistor is composed of a static induction type transistor having first and second gate regions formed of semiconductor regions of opposite conductivity type provided adjacent to a channel region, and the second gate region is used for signal readout. A gate electrode made of a transparent electrode is provided on at least a part of the first gate region with an insulating layer interposed therebetween, and the electron-hole pairs generated by the incident light are A semiconductor photodetector device in which carriers of one of the carriers are accumulated in the first gate region, thereby controlling a current flowing between the source region and the drain region, the boundary between the second gate region and the channel region A steep potential barrier is set up in
A semiconductor photodetection device characterized in that the potential barrier suppresses accumulation of the carrier in the second gate region. 2. In the device according to claim 1,
The steep potential barrier is formed by an energy discontinuity in a band structure formed at the boundary between the second gate region and the channel region and formed by a material having a larger forbidden band width than the channel region. A semiconductor photodetection device characterized by: 3. In the device according to claim 2,
A semiconductor photodetecting device, wherein the material having a forbidden band width larger than that of the channel region is an insulator. 4. In the device according to claim 3,
A semiconductor photodetector characterized in that the potential barrier includes a potential barrier formed by one of the source and drain regions disposed adjacent to the second gate region. Device. 5. In the device according to claim 3,
A semiconductor photodetection device characterized in that a potential of a second gate region formed by applying a voltage is added to the potential barrier. 6. In the device according to claim 5,
A semiconductor photodetection device characterized in that the voltage is pulsed and the second gate region has the same conductivity type as the channel region. 7. In the device according to any one of claims 3 to 5, the second gate region is coated with a shielding layer that blocks incident light. Features of semiconductor photodetection device. 8. A semiconductor photodetection device according to any one of claims 1 to 7, characterized in that a plurality of the electrostatic induction transistors are arranged one-dimensionally. 9. A semiconductor photodetection device according to any one of claims 1 to 7, characterized in that a plurality of the static induction transistors are two-dimensionally arranged. 10. The semiconductor photodetecting device according to claim 8 or 9, wherein the second gate region is provided in common to adjacent static induction transistors. . 11. The device according to any one of claims 8 to 10, characterized in that excess carrier absorption means is added in the channel region opposite to the second gate region. Semiconductor photodetector. 12. The semiconductor photodetector according to claim 11, wherein the absorption means is of the same conductivity type as the first gate region. 13. A semiconductor photodetection device according to claim 12, wherein the absorption means is formed in a mesh shape. 14. A semiconductor photodetector according to claim 1, wherein the electrostatic induction transistor is provided as a single cell.