JPH0462222B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a phase signal detection method.

Generally, in order to obtain phase synchronization in an independently synchronized facsimile machine that complies with CCITT's G2 standard, as shown in Figure 1A, the demodulated phase signal must have one period corresponding to the transmission time of one line. 6Hz with one rising and changing point per cycle
Since this is a periodic signal, and its rising and changing points are used as phase reference points, conventional phase synchronizers have a configuration as shown in FIG. That is, in the conventional device shown in the figure,
The demodulated output signal of the demodulator 22 which has led the facsimile image signal received through the telephone line via the line interface circuit 21 is supplied to and set by the flip-flop 23 for resetting by the arithmetic processing unit (CPU) 25. The timer 24 is reset and free-run by the output signal of , an interrupt signal consisting of a 6 Hz periodic signal is generated, and the interrupt signal is supplied to the arithmetic processing unit 24 to obtain the required phase synchronization.

However, if the condition of the telephone line used to transmit the facsimile image is poor and noise is mixed into the facsimile image signal, the demodulated output signal will have a waveform as shown in Figure 1B, with multiple rising and changing points. Because these occur consecutively, the second
In the conventional phase synchronization device having the configuration shown in the figure, the reference point for phase synchronization is not determined, which often causes a shift in phase synchronization, and therefore a shift occurs in the facsimile image, resulting in jitter-like disturbances. It had the disadvantage of appearing. In addition, in order to eliminate such drawbacks, attempts have been made to filter out the noise components included in the demodulated output phase signal using a bandpass filter that passes only the carrier component of the phase signal. Since it is necessary to add additional elements, the phase synchronization device has a disadvantage that the structure is complicated and expensive.

An object of the present invention is to eliminate the above-mentioned conventional drawbacks and to detect a phase signal having a predetermined pulse width that is repeated at a constant period without error.

The present invention will be described in detail below with reference to the drawings.

First, an example of the configuration of a phase synchronization device according to the present invention is shown in FIG. In the illustrated configuration example, a received facsimile image signal from a telephone line is guided to a demodulator 32 via a line interface circuit 31, and the demodulated output signal is sent to a processing unit (CPU).
37 and its arithmetic processing unit 37
The output signal of the flip-flop 33 is applied to reset the flip-flop 33, and the output signal of the flip-flop 33 directly resets the first timer 34 and also resets the second timer 36 via the OR gate 35. And the free running of the second timers 34 and 36 is started simultaneously. The second timer 34 is G2
According to the standard, a first interrupt signal is generated periodically at 6 Hz, and the arithmetic processing unit 37 determines a reference point for phase synchronization based on the first interrupt signal. Further, since the second timer 36 is also reset by the first interrupt signal applied from the first timer 34 via the OR gate 35, the first and second timers 34 and 36
will always free run in sync.
Further, the second timer 36 is a programmable timer, and by sequentially setting the timer values N ₁ and N ₂ by the arithmetic processing unit 37, the period of one cycle of 6 Hz according to the G2 standard of the first timer 34 is set. A plurality of second interrupt signals can be generated and supplied to the arithmetic processing unit 37.

The timing chart in FIG. 2 shows an example of the time relationship between the above-mentioned signals. That is, in the illustrated timing chart, the first and second timers 34 and 36 are started at the rising edge of the output signal waveform shown in waveform B of the flip-flop 33, which is set at the reference point of the demodulated signal shown in waveform A. , at the next reference point in the demodulated signal,
Although one first interrupt signal shown in waveform C is generated, the second interrupt signal shown in waveform D is generated by the timer value N ₂ from the arithmetic processing unit 37,
In the arithmetic processing unit ₃₇ , a final second interrupt signal from the second timer 36, for example, a second interrupt signal according to the timer value _N2 is generated.
In response to the interrupt signal, a flag signal is set as shown in waveform E, and the second interrupt signal that is the earliest counting from the first interrupt signal from the first timer 34 that is generated subsequently is set.
For example, the flag signal is reset by the second interrupt signal based on the timer value _N1 , and is used as a timing signal for synchronization determination to determine the phase relationship between the demodulated phase signal and the first interrupt signal from the first timer 34. The flag signal is used.

A flowchart of interrupt processing in the arithmetic processing unit 37 described above is shown in FIG. In the illustrated flowchart, as a series of interrupt processing steps from interrupt to return, it is determined in step S1 whether or not the incoming interrupt signal is the first interrupt signal from the first timer 34. , if no, step
In step S2, it is determined whether or not this is the first second interrupt signal from the second timer 36, and if not, it is determined in step S3 whether or not it is the second second interrupt signal. , if the incoming signal is not any interrupt signal, it is determined that there is an error. When it is determined in step S1 that it is the first interrupt signal, a timer value N1 is set in the second timer 36 in step S4, and in step S2, it is determined that it is the first second interrupt signal. When it is determined that this is the second interrupt signal, a timer value _N2 is set in the second timer 36 in step S5, a flag signal is set in S6, and it is determined that it is the second second interrupt signal in step S3. When it is determined, step
The flag signal is reset at S7.

The timing relationship of the synchronization determination by the above-described interrupt processing in the arithmetic processing unit 37 is shown in FIGS. 6A and 6B, and the flowchart of the synchronization determination is shown in FIG. That is, as shown in FIG. 6A, the arithmetic processing unit 37 determines that normal phase synchronization is possible if the black signal portion of the demodulated phase signal is included in the period when the flag signal level is at the high logic level "high". It is determined that the result is obtained. Here, the illustrated period T/2 represents the time length of 1/2 of the period T of the black signal portion, and there is a margin of T/2 before and after the flag signal level "high" period. If the black signal portion is included, it is determined that the phase synchronization is normal. Note that symbols ~ in the figure indicate corresponding processes in the flowchart described later.

On the other hand, the condition of the telephone line used to transmit the facsimile image was poor, and as shown in Figure 6B, the edges of the demodulated phase signal became unclear due to mixed noise, and the difference between the first interrupt signal and the phase signal Even if the phase relationship with the reference point deviates by more than a predetermined value, the reference point of the phase signal can be adjusted by generating a signal to reset the flip-flop 33 from the arithmetic processing unit 37 at the falling point of the flag signal. The first timer 34 can be started at , and the synchronization determination operation described above can be performed to obtain a normal phase synchronization state.

Next, in the flowchart shown in FIG. 7, the steps corresponding to the check shown in FIG.
The flag signal level is determined in S11, and when the flag signal level is high, the step S12 corresponding to the check is performed.
~ In S14, it is determined whether the flag signal is at a high level and reaches the black signal portion during the period T/2, and if the flag signal reaches the black signal portion after the period T/2, a check is performed. In steps S5 and S16, it is determined whether the flag signal is at a high level and has changed to a white signal, and if it has changed to a white signal,
At steps S17 and S18 corresponding to the check,
It is determined whether the flag signal is at a low level and the white signal continues.

Note that when it is determined in step S19 that the synchronization determination operation has been repeated a predetermined number of times, the phase synchronization operation is ended, and in step S20,
When the white signal continues, it is determined whether or not a phase signal due to normal facsimile communication is being received, and when it is determined that the reception state is not normal, the process moves to error processing.

As described above, according to the present invention, the period of the received signal pulse is constant, and the leading edge (for example, the falling edge and the pulse continuing for a certain period of time) and the trailing edge (for example, the rising edge) of the received signal pulse are constant. ) is within the second period, the received signal is detected as a phase signal, so the phase signal can be detected reliably.

[Brief explanation of the drawing]

Figures 1A and B are waveform diagrams showing examples of facsimile phase signal waveforms during normal reception and abnormal reception, respectively; Figure 2 is a block diagram showing the configuration of a conventional phase synchronization device; and Figure 3 is a diagram of the present invention. FIG. 4 is a block diagram showing a configuration example of the phase synchronization device according to the invention; FIG. 4 is a timing chart showing the operation waveforms of each part; FIG. 5 is a flow chart showing an example of the interrupt processing process; FIG.
Figures A and B are waveform diagrams showing examples of the synchronization determination process during normal reception and abnormal reception, respectively, and FIG. 7 is a flowchart showing an example of the synchronization determination process. 21, 31...Line interface circuit, 2
2, 32... Demodulator, 23, 33... Flip-flop, 24, 34, 36... Timer, 25, 3
7... Arithmetic processing unit (CPU), 35... OR gate.

Claims (1)

[Claims] 1. A method for detecting a phase signal consisting of a pulse signal in which predetermined on-periods and off-periods are repeated, including: a first period shorter than the off-period with reference to the rear end of the received signal pulse; and a second period that is longer than the on-period following the first period, and detecting a leading edge and a trailing edge of the received signal pulse within the second period based on the measurement results, A phase signal detection method characterized by determining a received signal pulse as a phase signal.