JPH0462494B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] The comparator circuit of the present invention includes a differential amplifier having a differential stage and an output stage, and when the output level of the output stage reaches a predetermined value. Sometimes, a constant current source is connected to the output side of the differential stage to form a bypass circuit, thereby limiting the output operating range of the differential stage even if there is a difference between the two input signal levels. This enables high-speed operation in response to changes in the input signal level.

[Industrial application field]

The present invention relates to a comparator circuit, and particularly to a comparator circuit using a differential amplifier.
Usually composed of semiconductor integrated circuits.

[Conventional technology]

Figure 4 shows one of the so-called differential type comparator circuits.
By way of example, the comparator comprises a differential stage 1 and an output stage 2. The differential stage 1 includes P channel transistors T ₁₁ and T ₁₂ and an N channel transistor whose sources are commonly connected.
T ₁₃ and T ₁₄ , the N-channel transistor
A constant current source 1 is connected between the source side of T ₁₃ and T ₁₄ and the ground.
5 is connected. Then, for example, an input signal (IN+) at a reference level is input to the gate of one N-channel transistor _T14 , and an input signal to be compared with the input signal at the reference level is input to the gate of the other N-channel transistor _T13. (IN−) is input.

The voltage level V ₁ on the drain side of the N-channel transistor T ₁₄ is input to the gate of the P-channel transistor T ₂₁ constituting the output stage 2.
A constant current source 22 is connected between the drain side of the P-channel transistor _T21 and the ground, and an output voltage _V2 is taken out from the drain side (output terminal OUT) of the transistor _T21 .

In such a differential comparator circuit,
Even if there is a slight level difference between the two input signals (IN-) and (IN+) input to the pair of N-channel transistors T ₁₃ and T ₁₄ configuring the differential stage 1, the level According to the difference, the ratio of currents flowing through the pair of N-channel transistors T ₁₃ and T ₁₄ changes, and accordingly, from the output side of the differential stage 1, that is, from the drain side of the N-channel transistor T ₁₄ , Voltage V ₁ with large fluctuations (that is, the input signal level difference is amplified)
is taken out.

Now let us assume that the reference input signal level (IN+)
compared to the input signal level (IN−)
becomes high, the corresponding input signal level (IN−)
The source potential of the N-channel transistor _T13 to which is input increases with the input. Then, the source potential of _T14 rises as well, and the current increases to _T13 .
It will start to flow more. As a result, the gate potential of the P channel transistors T ₁₁ and T ₁₂ is lowered.
As a result, the P-channel transistor _T12 also tries to cause current to flow, but the N-channel transistor _T14 , to which the reference input signal level (IN+) is input, tries to prevent current from flowing. The potential V ₁ on the drain side of the N-channel transistor T ₁₄ increases in accordance with the level difference between the two input signal levels.

On the other hand, when the input signal level (IN-) input to the transistor _T13 is lower than the reference input signal level (IN+) input to the transistor _T14 , the input signal level (IN-) is lower than the reference input signal level (IN+) input to the transistor T14. The source potential of the N-channel transistor _T13 to which the signal is input decreases with the input. Then, the source potential of _T14 also decreases, and more current flows through _T14 . As a result, the gate potentials of the P channel transistors T ₁₁ and T ₁₂ are increased. As a result, the P-channel transistor _T12 tries to block the current, while the N-channel transistor _T14 , to which the reference input signal level (IN+) is input, tries to conduct the current. 2
The drain side potential V ₁ of T ₁₄ decreases in accordance with the level difference between the two input signal levels.

Note that the output potential of the differential stage 1 varies as described above depending on the level difference between the two input signal levels.
V ₁ in turn constitutes the output stage 2 transistor T ₂₁
is supplied to the gate of the output stage 2, and the potential is
V ₁ is inverted and amplified and taken out from the output terminal OUT as an output voltage V ₂ .

[Problem that the invention seeks to solve]

In such a conventional circuit, when the input signal level (IN-) gradually increases and the level difference between it and the reference input signal level (IN+) increases, the source potential of the N-channel transistor _{T13 increases} . rises. Then, the source potential of _T14 similarly rises, and finally the N-channel transistor _T14 or the P-channel transistor _T21 enters the cut-off state.

In this state, the input signal level (IN-) then becomes the reference input signal level (IN+).
The problem is that when the current is applied to the transistors T ₂₁ and T ₁₄ when the current becomes lower, it takes time for the stray capacitance existing there to be charged, resulting in a large delay in the next operation. produce a point.

The present invention has been made in order to solve this problem, and detects the cut-off situation by a fixed level of the output stage connected to the output side of the differential stage, and detects the cut-off state or a state close to it. Based on the idea of forming a bypass circuit including a constant current source on the output side of the differential stage when the differential stage is detected, the operating speed of the comparator circuit can be reduced by limiting the output range of the differential stage. This was done to eliminate delays.

[Means for solving problems]

In order to solve the above problems, according to the present invention, a differential stage 1 receiving an input signal, an output stage 2 including an output transistor controlled by an output signal of the differential stage 1, and a a detection circuit 3 connected to the output terminal and generating a detection output when the voltage at the output terminal drops below a predetermined detection level; A comparator comprising a switching circuit 4 for forming a bypass circuit having a current source 5, and when the switching circuit 4 is conductive, a constant current is caused to flow from the output terminal of the differential stage 1 to the bypass circuit. A circuit is provided.

[Operation] According to the above configuration, when the potential on the output side of the differential stage (indicated by V _A in FIG. 1) rises and the transistor of the differential stage becomes cut-off or close to cut-off, detects this by a change in the output level of the output stage (indicated by V _B in Figure 1) obtained by inverting and amplifying the potential V _A , and thereby forms the bypass circuit. This makes it possible to force a predetermined current to flow through the transistors of the differential stage, prevent the potential V _A from rising, and limit the output operating range of the differential stage, thereby preventing the output stage transistors from being cut off. prevent.

〔Example〕

FIG. 1 shows the basic configuration of a comparator circuit as an embodiment of the present invention, and parts common to the conventional example shown in FIG. 4 are given the same reference numerals.

As shown in FIG. 1, in the present invention, the output level V _B of the output stage 2 (obtained by inverting and amplifying the output level V _A of the differential stage 1) is detected by the level detection circuit 3. When the output level V _B detected by the detection circuit 3 falls below a predetermined level due to the increase in the output level V _A , the switching circuit 4 operates and the output side of the differential stage 1 ( connection point between the drain of P-channel transistor _T12 and the drain of N-channel transistor _T14 )
A bypass circuit P (bypass circuit for the N-channel transistor _T14 ) is formed from the constant current source 5 to ground.

FIG. 2 shows the conventional circuit shown in FIG.
FIG. 2a is a timing diagram showing a comparison of the operation with the circuit of the present invention shown in FIG. 1, and FIG. ) shows a situation in which the value of

In such a case, in the conventional example shown in FIG. 4, first the input signal level (IN-) is
becomes higher than the reference input signal level (IN+),
As mentioned above, the output level V ₁ of the differential stage 1 rises, and depending on the level difference, the P channel transistor T ₂₁ or the N channel transistor T ₁₄
is in the cut-off state. Therefore, after that, the second
The input signal level (IN-) as shown in Figure a
It takes time to make the cut-off transistor conductive again when the input signal level (IN+) becomes lower than the reference input signal level (IN+).
-), there will be a delay in inverting (lowering) the output level _V1 (see the dotted line in FIG. 2B). Therefore, the level
A similar delay occurs in the output level _V2 of the output stage ₂ obtained by inverting and amplifying V1 (see the dotted line in FIG. 2C).

On the other hand, in the circuit according to the present invention shown in FIG. 1, the input signal level (IN-) is
is higher than the reference input signal level (IN+), the output level V _A of differential stage 1 increases, and the output level V _B of output stage 2 decreases accordingly; When the output level V _B decreases below the predetermined detection level L due to the signal level difference, the level detection circuit 3 detects the level decrease and operates the switching circuit 4 to turn off the bypass circuit P. A predetermined constant current is forced to flow through the P channel transistor _T12 through the bypass circuit P.

Therefore, the output level V _B does not fall below the detection level L, in other words, the differential stage 1
When the output level V _A of the P-channel transistor no longer rises above a predetermined detection level,
T ₂₁ is prevented from being cut off.
In other words, in the circuit shown in Figure 1, the comparator can always be used actively, and when the input signal level (IN-) is inverted (lowered) with respect to the reference input signal level (IN+), the output level is immediately changed. V _A and even the output level V _B can be inverted. In this way, the transition to the next operation becomes easy and high-speed operation becomes possible.

FIG. 3 shows a specific example of the level detection circuit 3 and the switching circuit 4 in the circuit shown in FIG.
A first stage inverter consisting of T ₃₁ and T ₃₂ ,
It is constituted by a second stage inverter consisting of transistors _T33 and _T34 , while switching circuit 4 is constituted by one P channel transistor _T41 .

The output level _VB of the output stage 2 is input to the gates of the transistors _T31 and _T32 constituting the first stage inverter in the level detection circuit 3.
When the output level V _B drops to a predetermined detection level L (for example, when the power supply voltage is Vcc and the detection level L is 1/5Vcc), the transistor _T31 and
The first stage inverter consisting of transistors _T32 is inverted (its output is set to high level), and then the output is re-inverted by the second stage inverter consisting of transistors _T33 and _T34 to make it low. level, and supplies the low level output to the gate of the P channel transistor _T41 of the switching circuit 4, making the transistor _T41 conductive and forming a bypass circuit P.

In the circuit shown in FIG. 3, each of the constant current sources 15, 22, and 5 shown in _FIG . It is constituted by the supplied transistors T ₁₅ , T ₂₂ and T ₅ .

In the circuits shown in FIGS. 1 and 3, a bypass circuit P is formed on the output side of the differential stage 1 upon detecting that the output level V _B has decreased to a predetermined value, thereby reducing the output level. This prevents the cut-off of the P-channel transistor _T21 constituting stage 2, but the same idea can be applied when the output level _VB rises to a predetermined value, and the P-channel transistor T21 constituting the differential stage A bypass circuit including a constant current source can also be formed at the connection point between T ₁₁ and N-channel transistor T ₁₃ .

However, in this case, the output stage P channel transistor T ₂₁ is not cut off, and therefore the necessity of forming the above-mentioned bypass circuit on the transistors T ₁₁ and T ₁₃ side is reduced.
The amount is relatively small compared to the T ₁₂ and T ₁₄ sides.

〔Effect of the invention〕

According to the present invention, by limiting the output operating range of the differential stage, it is possible to prevent the transistors forming the output stage from entering the cut-off state,
Therefore, the comparator circuit can operate at high speed in response to changes in the input signal level.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the basic configuration of a comparator circuit as an embodiment of the present invention, and FIG.
3 is a timing diagram illustrating the operation of the circuit shown in the figure in comparison with a conventional circuit. FIG. 3 is a circuit diagram showing in detail one specific example of the circuit of FIG. 1, especially the level detection circuit and the switching circuit. , FIG. 4 is a circuit diagram showing a conventional example of this type of differential type comparator. (Explanation of symbols), 1...Differential stage of differential amplifier, 2
...Output stage of differential amplifier, 3...Level detection circuit, 4
...switching circuit, 5... constant current source provided in bypass circuit P.

Claims (1)

[Claims] 1 A differential stage 1 that receives an input signal, an output stage 2 that includes an output transistor that is controlled by the output signal of the differential stage 1, and is connected to the output terminal of the output stage 2 so that the voltage at the output terminal is a predetermined voltage. A switching circuit for forming a bypass circuit having a detection circuit 3 that generates a detection output when the voltage drops below the detection level, and a constant current source 5 that conducts in response to the detection output and has a constant current source 5 at the output end of the differential stage 1. 1. A comparator circuit comprising a circuit 4, wherein when the switching circuit 4 is conductive, a constant current is caused to flow from the output terminal of the differential stage 1 to the bypass circuit.