JPH0462555B2 - - Google Patents

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention involves passing a recording current through a recording electrode through an ink ribbon consisting of a resistive layer and an ink layer such as heat-melting ink or sublimation ink. The present invention relates to a drive circuit for an electrical transfer recording device that transfers and records ink onto a desired paper or the like using generated Joule heat.

[Prior Art] FIG. 8 is a block diagram of a conventional electrical transfer recording apparatus. In FIG. 8, a plurality of recording electrodes 31
is selectively driven by the recording electrode drive circuit 32, a recording current is passed from the recording electrode 31 in the thickness direction of the resistive layer 33, the resistive layer 33 near the recording electrode 31 is heated, and the ink in the ink layer 35 is heated. The image is transferred and recorded onto a predetermined paper (not shown) provided in contact with 35.

The recording current flows to the return electrode 37 via the conductive layer 34 and the resistance layer 33 near the return electrode 37.

FIG. 9 is an equivalent circuit of the ink ribbon 36 of FIG. 8 and a block diagram of the recording electrode drive circuit 32 proposed in US Pat. No. 4,350,449. In the equivalent circuit of the ink ribbon 36, the resistance layer 33 that generates Joule heat during recording includes a plurality of recording electrodes 31.
It consists of a plurality of resistors R _L connected in series to a to 31n, the other ends of each of the resistors R _L are connected together, and the connection point is the conductive layer 34 and the resistive layer 33 that serve as the return path for the recording current. is connected in series to the combined resistance R of . The other end of the combined resistance R is the return electrode 3.
Connected to 7.

Here, when the plurality of recording electrodes 31a to 31n are simultaneously driven with the same drive printing voltage, the current that acts on printing, that is, flows through the resistance R _L of the resistance layer 33 that is in contact with and connected to the recording electrode 31, is This varies depending on the number of recording electrodes 31 that are simultaneously driven, and therefore the amount of Joule heat energy consumed by the resistance R _L of the resistance layer 33 varies, making it impossible to obtain stable print recording.

In order to solve this problem, US Patent No.
No. 4,350,449 proposes a recording electrode drive circuit which drives each of the recording electrodes 31a to 31n with constant current sources 38a to 38n, respectively, to prevent fluctuations in the recording current, as shown in FIG.

[Problems to be Solved by the Invention] However, in the conventional drive circuit shown in FIG. 9, the same number of constant current sources as recording electrodes are required, which complicates the circuit configuration and makes it difficult to miniaturize and reduce the cost of the circuit. It was difficult to reduce the cost.

[Object of the Invention] An object of the present invention is to solve the above-mentioned problems and to provide a drive circuit for an electrical transfer recording device that has a simple configuration and is capable of stable print recording.

[Structure of the Invention] The present invention provides a drive circuit for an electrical transfer recording device that performs recording by selectively passing a recording current through a plurality of recording electrodes to an ink ribbon having a resistive layer and an ink layer. The present invention is characterized by comprising voltage generating means for generating a voltage proportional to the number of recording electrodes and applying it to the recording electrodes.

[Embodiment] FIG. 1 is a block diagram of a drive circuit of a current transfer recording apparatus showing an embodiment of the present invention. In FIG. 1, 1 is a CPU that outputs printing pattern information DATA to a digital-to-analog converter (hereinafter referred to as a D/A converter) 2 and a recording electrode drive circuit 3.
The D/A converter 2 converts the input pattern information DATA into a print voltage control circuit 4 by converting the input pattern information DATA into an analog voltage V _D proportional to the number of high-level signals of the pattern information DATA.
Output to. The print voltage control circuit 4 amplifies the input analog voltage V _D and applies a print voltage V _P proportional to the analog voltage to the return electrode 5 .

On the other hand, the recording electrode drive circuit 3 grounds the recording electrodes 6 that contribute to printing based on the pattern information input from the control circuit 1 in order to drive them, and also connects the recording electrodes 6 that do not contribute to printing to an open circuit. , performs on/off control of each printing electrode of the recording electrode 6.

With the above configuration, the D/A converter 2 receives pattern information DATA from the control circuit 1, and prints the number of pattern information DATA that is a high signal, that is, the number of dots recorded simultaneously. An analog voltage V _D proportional to the number of electrodes is output to the printing electrode control circuit 4, and the printing voltage control circuit 4
controls the print voltage V _P applied to the return electrode 5 so that it is proportional to the analog voltage V _D .

On the other hand, since the recording electrode drive circuit 3 drives only the recording electrodes 6 that contribute to printing based on the pattern information input from the control circuit 1, it is grounded to earth, so the recording electrodes 6 and the return electrodes 5 that contribute to printing are grounded.
In between, a printing voltage V _P proportional to the number of dots recorded simultaneously is applied. As a result, a constant current flows through the resistor R _L of the resistive layer 33 in FIG. 8 that contributes to printing, and a constant Joule heat is generated in the resistor R _L.
The ink in the ink layer 35 facing the ink layer 35 is transferred to a predetermined paper provided in close contact with the ink layer 35, and stable printing can be performed.

FIG. 2 is a circuit diagram of the D/A converter 2 and printing voltage control circuit 4 shown in FIG.

In FIG. 2, n binary parallel data signals DATA ₁ to DATAn are input from a control circuit 1 to a D/A converter as pattern information. The binary signals DATA ₁ to DATNn have a voltage +Vcc [V], which is a signal "1", when printing is performed, and a voltage 0 [V], which is a signal "0", when not printing. Binary data signal DATA ₁
to DATAn are respectively connected together via a resistor R _D and further connected to a non-inverting input terminal of an operational amplifier OP ₁ of the print voltage control circuit 4 . As described above, the binary signal DATA ₁ to DATAn is connected to the resistor R _D
By connecting wired or through
It constitutes a D/A converter.

Furthermore, the operational amplifier OP ₁ of the printing voltage control circuit 4
The inverting input terminal of is connected to its output, and the output is connected to the anode of the Zener diode Dz. Here, the operational amplifier _OP1 constitutes a voltage floor circuit for buffering.

The cathode of the Zener diode Dz is connected to the non-inverting input terminal of the operational amplifier OP ₂ and to the DC voltage source +Vs via a resistor Rz. In addition, the inverting input terminal of the operational amplifier OP ₂ is connected to the ground via a temperature characteristic compensation resistor Rs, and is also connected to one end of a parallel circuit of a thermistor R _T and a temperature characteristic compensation resistor Rp. The other end is connected to the emitter and return electrode 5 of the transistor Qp. The output of the operational amplifier _OP2 is connected to the base of the transistor Qp, and the collector of the transistor Qp is connected to the DC voltage +Vs.

The operational amplifier OP ₂ and the transistor Qp constitute a constant voltage circuit, and the output of the constant voltage circuit, which is the emitter of the transistor Qp, is connected to the thermistor R _T and the temperature characteristic compensation resistor Rp.
and temperature compensated by Rs. Here, the resistance values of the thermistor _RT and resistors Rp and Rs are set as shown in the following formula.

1/K=Rs/RpR _T +Rs (1) Here, K is a constant, and RpR _T is the resistance value of the parallel circuit of thermistor R _T and resistor R.

By configuring as shown in FIG. 2, a binary signal which is pattern information output from the control circuit 1
DATA ₁ to DATAn are respectively applied to the resistor R _D of the D/A converter 2, and the number of dots printed simultaneously, that is, the binary signal DATA ₁ is applied to the resistor R D of the D/A converter 2.
If the number of ON signals among DATAn is m, then the analog voltage that is the output voltage of the D/A converter 2 input to the non-inverting input terminal of the operational amplifier OP ₁
V _D is expressed by the following formula.

V _D =m/nVcc... (2) This analog voltage V _D is applied to the anode of the Zener diode Dz of the Zener voltage Vz via the operational amplifier _OP1 for the buffer, and
The reference voltage Vr at the cathode of the diode Dz is expressed by the following equation.

Vr=Vz+V _D =Vz+m/nVcc...(3) This reference voltage Vr is input to the non-inverting input terminal of the operational amplifier _OP2 , and is the output of the constant voltage circuit constituted by the operational amplifier _OP2 and the transistor Qp. The output of the emitter of the transistor Qp, that is, the print voltage Vp, is divided by the parallel circuit and the resistor Rs at a voltage division ratio of 1/K in the above equation (1), and the parallel circuit is the divided detection voltage Vp'. The voltage at the connection point with the resistor Rs is input to the inverting input terminal of the operational amplifier _OP2 . This detection voltage Vp' is expressed by the following equation.

Vp'=1/KVp...(4) The above-mentioned constant voltage circuit is designed so that the two voltages input to the inverting input terminal and the non-inverting input terminal of the operational amplifier _OP2 are equal, that is, Vp'=Vr ...(5) It operates as follows. Therefore, equations (3), (4) and
The following equation is obtained from equation (5).

Vp=K・Vr=K(Vz+m/nVcc)...(6) From equation (6), it is clear that the printing voltage Vp is proportional to the number of printed dots m, and the printing voltage
Vp is applied to the return electrode 5. Note that since the thermistor R _T is used in the printing voltage detection stage as described above, the printing voltage Vp is changed according to the ambient temperature, thereby preventing fluctuations in recording density due to changes in the ambient temperature.

FIG. 3 is a circuit diagram of the recording electrode drive circuit 3 of FIG. 1. In FIG. 3, the pattern information n
The binary signals DATA ₁ to DATAn are input to the bases of transistors Q ₁ to Qn via resistors Ri, respectively, and the collectors of transistors Q ₁ to Qn are input to the bases of transistors Q 1 to Qn via resistors Ro for stabilizing the recording operation. The signals are outputted to each print electrode of the recording electrode 6 as print signal outputs _OUT1 to OUTn.

With the above configuration, the binary signal DATA ₁ to
The positive voltage of +Vcc [V], which is the ON signal of DATAn, is applied to the transistors _Q1 to Qn through the input resistor Ri.
When a voltage is applied to the base of the transistor Q1 to Qn, the transistor _Q1 to Qn to which the voltage is applied is turned on, and the collector of the transistor _Q1 to Qn is grounded. This allows the binary signal DATA ₁ to
Print signal output corresponding to DATAn on signal
The print electrodes of the recording electrodes 6 connected to OUT ₁ to OUTn are grounded to earth via the output resistor Ro. On the other hand, when a voltage of 0 [V], which is the off signal of the binary signals DATA ₁ to DATAn, is applied to the bases of the transistors Q ₁ to Qn via the input resistor Ri, the applied transistors Q ₁ to Qn are turned off. state, and its transistor Q ₁ to Qn
collector, i.e. the corresponding recording electrode 6
The printing electrode becomes an open circuit state.

Therefore, depending on the ON signal or OFF signal of the binary signals DATA ₁ to DATAn, the printing electrodes of the corresponding recording electrodes 6 are grounded or placed in an open circuit state, and the printing electrodes of the recording electrodes 6 are turned on or off. can be controlled.

The circuits shown in FIGS. 2 and 3 are used to configure the driving circuit of the current transfer recording apparatus shown in _FIG . Recording electrode drive circuit 3
As a result, a temperature-compensated printing voltage Vp proportional to the number m of printing dots of pattern information is applied to the return electrode 5, while the printing electrode of the recording electrode 6 corresponding to the pattern information is grounded. Therefore, the current flowing through the resistor R _L of the resistive layer 33 that contributes to printing becomes constant, and desired printing corresponding to the pattern information can be stably performed.

Next, a method for correcting adjacent dots in printing in the embodiment shown in FIG. 1 will be described. Adjacent dot correction involves controlling the recording energy depending on whether or not adjacent dots are recorded, in order to prevent the recorded dot density from fluctuating due to the diffusion of heat from adjacent dots that are recorded at the same time. This is a correction to stabilize the FIG. 4 is a time chart of the binary signal DATA of pattern information for explaining this adjacent dot correction. To perform adjacent dot correction, one printing operation is time-divided into three patterns: adjacent lower channel correction pattern LDATA, basic pattern DATA, and adjacent upper channel correction pattern RDATA, as shown in the explanatory diagram of FIG. , the energizing times of each of the above patterns are Tc, T _B and Tc, respectively.

When the printing of dots on both sides is off, the pattern information is a binary signal for the entire period of one printing operation.
DATA is turned on, and therefore, the energization time Tφ at this time is Tφ=T _B +2·Tc (7).

Further, when the printing of one adjacent dot is off and the printing of the other adjacent dot is on, two patterns exist as shown in FIG.

That is, the adjacent lower channel correction pattern
There are two patterns: a () pattern that turns on LDATA and basic pattern DATA, and a () pattern that turns on basic pattern DATA and adjacent upper channel correction pattern RDATA, and the energization time T ₁ for these two patterns is , T ₁ =T _B +Tc...(8).

Furthermore, when the printing of both adjacent dots is turned on, only the basic pattern DATA is turned on,
The energization time T ₂ at this time is T ₂ =T _B (9). Therefore, from equations (7), (8), and (9), the above-mentioned adjacent dot correction is performed with the relationship Tφ>T ₁ >T ₂ (10).

As a method for obtaining the above-mentioned correction patterns LDATA and RDATA, there is a method in which the CPU of the control circuit 1 performs calculations according to the following equations.

LDATA = (DATA) * (data shifted upwards by 1 bit) (11) RDATA = (DATA) * (data shifted upwards by 1 bit) (12) Calculation of equations (11) and (12) above By performing this, correction patterns LDATA and RDATA can be obtained. In equations (11) and (12), “data obtained by shifting DATA upward by 1 bit” and “data obtained by shifting DATA downward by 1 bit” are the mnemonics of the Z-80CPU, respectively.
It can be obtained using the "SLA" and "SRL" commands in the code.

Therefore, the drive circuit of the current transfer recording device is configured using the circuits shown in FIGS. 1 and 2, and the pattern information is divided into time-divided correction patterns LDATA and DATA together with the basic pattern DATA as shown in FIG. Adjacent dot correction can be performed by applying the following dots.

Figures 5 and 6 show the above pattern information.
3 is a circuit diagram of the D/A converter 2, print voltage control circuit 4, and recording electrode drive circuit 3 when DATA is serial data. FIG. In FIGS. 5 and 6, the same parts as in FIGS. 2 and 3 are designated by the same reference numerals.

In FIG. 5, a binary serial data signal SDATA, which is pattern information output from the control circuit 1 in FIG. 1, and a clock signal, which is its synchronization signal, are shown.
CLOCK is input to AND gate 51, and
A counter reset signal CLR for counting the number of recording dots output from the control circuit 1 is input to the CL terminal of the counter 52. AND gate 51
The output terminal of the counter 52 is connected to the CP terminal of the counter 52, and the parallel output terminal of the counter 52 is connected to the input of the D/A converter 53, and the output of the D/A converter 53 is connected to the anode of the Zener diode Dz. connected to.

The counter 52 counts the number of pulses input to the CP input terminal of the counter 52, and outputs the counted value to the D/A converter 53 via the parallel bus in real time.

Note that when a pulse of the reset signal is input to the CL terminal of the counter 52, the count value of the counter 52 is reset to "0". Further, the D/A converter 53 outputs an analog voltage V _D proportional to the input count value to the anode of the Zener diode Dz. The printing voltage control circuit 4 in FIG. 5 is the same circuit as that in FIG. 2.

In FIG. 6, a binary serial data signal which is pattern information output from the control circuit 1
SDATA and clock CLOCK are input to the IN terminal and CP terminal of the shift register 54, respectively, and a print command signal which is the energization timing signal to the recording electrode 6 output from the control circuit 1
PRINT is the enable terminal of shift register 54
Entered into OE. The output terminals P ₁ to Pn of the shift register 54 are connected to the bases of the transistors Q ₁ to Qn through resistors Ri, respectively, the emitters of the transistors Q ₁ to Qn are all connected to ground, and the collectors thereof are connected to the ground. Each is connected to a corresponding electrode of the recording electrode 6 via an output resistor Ro.

Note that, after the shift register 54 captures the binary serial data signal SDATA in synchronization with the clock CLOCK input to its CP input terminal, when the print command signal PRINT is input to its enable terminal OE, the shift register 54 outputs the binary serial data signal SDATA. Data signal SDATA
Output the serial-parallel converted pattern data of
Output to P ₁ to Pn.

Figure 7 shows the first circuit using the circuits of Figures 5 and 6.
3 is a time chart showing the operation when the drive circuit of the energized transfer recording device shown in the figure is configured.

In Fig. 7, first the reset signal is
CLR is input to the counter 52, and the reset signal is
After the counter 52 is reset by the CLR,
The n serial data signals SDATA and the clock signal which is its synchronization signal are sent to the D/A converter 2.
The signal is input to the counter 52 via the AND gate, and is also input to the shift register 54 of the recording electrode drive circuit 3. As a result, the counter 52
outputs the pattern count value of the input serial data signal SDATA to the D/A converter 53, and in response, the D/A converter 53 outputs an analog voltage V _D proportional to the pulse count value to the print voltage control circuit. 4
output to the anode of the Zener diode Dz. As a result, the print voltage control circuit 4 applies a print voltage Vp proportional to the analog voltage V _D to the return electrode 5, similar to the operation shown in FIG.

On the other hand, the serial data signal SDATA and the clock signal are transferred to the shift register 5 of the recording electrode drive circuit 3.
When the print command signal PRINT is input to the shift register 54, the pattern data obtained by converting the binary serial data signal SDATA into serial and parallel signals is output to its outputs _P1 to Pn, and the pattern data is turned on. Each printing electrode of a certain recording electrode 6 is grounded to earth.

Therefore, a temperature-compensated printing voltage Vp proportional to the number m of pattern information printing dots is applied to the return electrode 5, and on the other hand, the printing electrode of the recording electrode 6 corresponding to the pattern information is grounded, so that printing Each current flowing through the resistor R _L of the resistive layer 33 that contributes to the pattern information becomes constant, and desired printing corresponding to the pattern information can be stably performed.

As shown in Figure 7, the above-mentioned reset signal CLR
The period from 1 to the print command signal PRINT constitutes one print cycle, and as is well known, this cycle is repeated to perform predetermined recording.

[Effects of the Invention] As described in detail above, according to the present invention, by providing a voltage generating means that generates a voltage proportional to the number of recording electrodes and applies it to the recording electrodes, it is possible to achieve a simple and stable structure. This method has the advantage of making it possible to print and record images in a timely manner, thereby reducing costs.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a drive circuit of a current transfer recording apparatus showing an embodiment of the present invention, FIG. 2 is a circuit diagram of the D/A converter and printing voltage control circuit of FIG. 1, and FIG. Circuit diagram of the recording electrode drive circuit in Figure 1, No. 4
The figure is a time chart of a binary signal of pattern information to explain adjacent dot correction, and Figure 5 is the D/A of Figure 1 when the pattern information is serial data.
A circuit diagram of a converter and a printing voltage control circuit, FIG. 6 is a circuit diagram of the recording electrode drive circuit of FIG. 1 when the pattern information is serial data, and FIG. 7 is a circuit diagram of the recording electrode drive circuit of FIG. 1 when the pattern information is serial data. A time chart showing the operation when the drive circuit of the current transfer recording device shown in FIG. and a block diagram of a conventional recording electrode drive circuit. DESCRIPTION OF SYMBOLS 1... Control circuit, 2... Digital-to-analog converter (D/A converter), 3... Recording electrode drive circuit, 4... Print voltage control circuit, 5... Return electrode,
6...Recording electrode.

Claims (1)

[Scope of Claims] 1. In a drive circuit for an electrical transfer recording device that performs recording by selectively passing a recording current through a plurality of recording electrodes to an ink ribbon having a resistive layer and an ink layer, 1. A drive circuit for an electrical transfer recording apparatus, comprising voltage generating means for generating a voltage proportional to the number of electrodes and applying it to the recording electrodes. 2. The present invention further comprises a detection means for detecting ambient temperature, and a first control means for controlling the output of the voltage generation means so as to prevent fluctuations in recording density due to changes in ambient temperature using the output of the detection means. A drive circuit for an electrical transfer recording apparatus according to claim 1. 3. Claim 1 further comprising a second control means for controlling the output time of the voltage generating means so as to prevent fluctuations in recording density due to the presence or absence of recording on adjacent recording electrodes. A drive circuit for the electrical transfer recording device described above.