JPH0462676B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a kanji processing device equipped with an address conversion table.

<Conventional technology> Conventionally, 8-bit CPUs used in kanji processing devices
(Central processing unit), the usable memory capacity is normally 64KB, and for items such as kanji patterns that require more than 64KB, the kanji pattern storage area is configured in a bank configuration as shown in Figure 7. By switching banks, the storage address of the desired kanji pattern can be obtained. In FIG. 7, the memory capacity for kanji patterns is 12 KB, and this is arranged in banks of 16 KB each. A and a' in FIG. 7 are areas in which system programs for processing kanji characters, programs for accessing kanji patterns, processing data, etc. are stored. Areas b ₀ to _{b 7} are areas where kanji patterns are stored, and each
A 16KB area is allocated, and the configuration is such that a total of 8 areas can be accessed by switching banks. When the kanji patterns assigned to b ₀ to _{b 7} are stored in a variable-length compressed format, an address conversion table is required to find the first address where each kanji pattern is stored. The configuration is such that the conversion table is stored in the b ₀ area in FIG.

FIG. 8 shows the configuration when this conversion table is added. a and a' are the same as in FIG. b ₀
~ _b7 stores variable-length compressed Kanji patterns. c is an address translation table. FIG. 9 shows the structure of a conventional address translation table. In FIG. 9, gm (l≦m≦n) is an area storing the storage address of the m-th kanji pattern, each of which requires 3 bytes. dm, em,
fm (1≦m≦n) is an element that constitutes gm,
dm stores the bank number in 1 byte. em
stores the upper byte of the address, and fm stores the lower byte of the address.

In the configuration shown in FIG. 9, 3 bytes x n are required as this address conversion table, for example
Non-kanji defined in JISC6226 (1 point for 1 to 8 wards)
94 points) and 1st level kanji (16th ward 1 point - 47th ward 94 points)
For a total of 3760 characters (points), 11280 bytes are required.
In other words, the space required for the address translation table increases. A kanji processing device using this address conversion table has a configuration as shown in FIG. In FIG. 10, reference numeral 1 denotes a kanji code buffer for storing kanji codes to be displayed, and the stored kanji codes are structured so that the higher order indicates a block and the lower order indicates the order within the block. 2 is a search control circuit which selects table data having the same kanji code from the address conversion table 3 and outputs it. The address conversion table 3 has address information and bank information for each code. 4
1 is an access control section which accesses the pattern memory 5 based on the given bank information and address information and selects desired Kanji pattern data.
6 is a pattern data processing section which converts pattern data into display data and outputs it. 7 is a display memory.

Then, the search control section 2 searches the address conversion table 3 based on the Kanji code, and sends bank information and address information to the access control section 4. The access control unit 4 switches banks according to the given information and sends desired kanji pattern data from the pattern memory 2. The sent kanji pattern data is sent to the pattern data processing section 6.
The data is expanded and sent to the display memory 7, where it is displayed.

In this configuration, as described above, since the address conversion table 3 includes address information and bank information for each Kanji code, there is a problem that the area of the conversion table becomes large.

<Object of the Invention> Therefore, an object of the present invention is to compress the memory capacity of an address conversion table in a kanji processing device.

<Structure of the Invention> In order to achieve the above object, the kanji processing device of the present invention has a large block made up of a collection of small blocks, and at the beginning of the small block, the address of the kanji character placed at the beginning of the group of kanji characters is written. an address conversion table configured to store the difference between the address of each remaining kanji and the address of the previous kanji;
The present invention is characterized in that it includes an address calculation section that calculates a storage address for the Kanji pattern data based on the information from the address conversion table and the storage location of the information.

<Examples> The present invention will be described in detail below with reference to illustrated examples.

FIG. 1 is a conceptual diagram showing the structure of an address translation table according to the present invention. hm (1≦m≦n) is a kanji
This area stores the storage address information of the kanji group included in the m-th block when 16 characters are considered a small block, and each block consists of 19 bytes. im, jm, km, lm ₁ to lm ₁₆ (1≦m≦n)
The elements that make up hm, im, jm, km are the bank numbers of the kanji placed at the beginning in the small block,
High byte of address. Store the lower byte,
Each consists of 1 byte. lm ₁ to lm ₁₆ are compressed information (described later) for each of the 16 kanji in the small block.
(see figure) is stored in a total of 16 bytes, each of which is 1 byte. According to this method, the 1st to 8th wards of JISC6226,
If each ward is divided into 6 small blocks for a total of 40 divisions from wards 16 to 47, the total number of small blocks will be 6.
With 40 small blocks, it becomes 240 small blocks,
Each small block requires 19 bytes, so 19 bytes x 240 = 4560 bytes, which is about 40% compressed compared to the configuration shown in Figure 9.

Figures 2a, b, and c show the structures of large blocks, small blocks, and small blocks in the address translation table. Figure 2a is a large block,
Non-kanji defined in JISC6226 (1 point for 1 to 8 wards)
94 points) and 1st level kanji (16th ward 1 point - 47th ward 94 points)
(points) are divided into large blocks for each district.

Figure 2b shows a state in which each section (each large block) is divided into six small blocks, and when dividing points 1 to 94 in each section into six small blocks, virtually zero points and 95 points, with 0 to 15 points as the first small block, 16 to 31 points, 32 to 47 points, and 48 points.
The points 63 to 63, points 64 to 79, and points 80 to 95 are the second, third, fourth, fifth, and sixth small blocks, respectively.

FIG. 2c shows the structure of each small block, and is a detailed description of the hm section of FIG. 1.
r, s, and t are the bank number of the address where the first kanji pattern is stored among the 16 kanji characters in the small block, and the upper byte and lower byte of the address are each indicated by 1 byte. It is. In this system, 16KB per bank
Therefore, the kanji pattern memory capacity is
When using 128KB, 8 banks are required, so r
A value from 0 to 7 is stored in . 16KB for s and t
The address space contains values from 0000H to 3FFFH.

In addition, to prevent a small block from being stored across the next small block between banks,
Each bank has a sector boundary configuration.

Compressed Kanji information for 16 characters (see Figure 3) constituting a small block is stored in u ₁ to u ₁₆ in a total of 16 bytes, each 1 byte. The kanji pattern placed first among the 16 characters is stored at addresses s and t. The address of the second kanji pattern is the address of s and t plus the compressed data length in the compressed information of the first kanji. Below, the nth kanji (2≦n≦16) is 1
By adding s and t to the sum of compressed data lengths up to (n-1)th, the address of the stored Kanji pattern can be found.

FIG. 3 is a diagram showing the structure of compressed information for each kanji. V is a half-width flag, and in a kanji pattern consisting of 16 x 16 dots, the dot elements that actually make up the pattern are concentrated only in the left half of the pattern, that is, a pattern consisting of 16 x 8 dots. This is a flag indicating that the pattern is a half-width pattern (see FIG. 4), and is assigned 1 in the case of a half-width pattern and 0 in the case of a full-width pattern of 16×16 dots, and consists of 1 bit. Note that in this example, the half-width pattern is not compressed;
The original pattern is stored as is.

W is a compression flag, which is assigned 1 when the pattern is compressed and stored, and 0 when it is stored as an original pattern without being compressed, and consists of 1 bit. In this embodiment, the following character types are stored in their original form without being compressed. First, characters that are frequently used, such as alphanumeric characters, hiragana, and katakana, are used in order to minimize the time it takes to restore them. Next, if some characters are compressed using a certain method, the memory capacity after compression may exceed the memory capacity when stored in their original form, so such characters may be stored in their original form. has been done.

X is a glyph flag and consists of 1 bit.

In a full-width pattern of 16 x 16 dots, 16 x 16
For patterns using dot areas, see 1.
0 is assigned to a pattern using a 16×15 dot area (see FIG. 5).

Y is the compressed data length, consisting of bits,
Values from 0 to 31 are stored. When Y is 0, there is no character shape assigned to the corresponding code, that is, the Kanji pattern is undefined in JISC6226. A value of 1 to 31 indicates that the memory capacity of the pattern is 2 to 32 bytes.

Figure 6 is a block diagram of the kanji processing device.
is a kanji code buffer that stores the kanji code of the kanji to be displayed, 8 is a search control circuit, and 9 is an address conversion table that stores memory address information of the pattern memory that stores kanji pattern data in correspondence with the kanji code. be. The address conversion table 9 shown in FIG. 1, FIG. 2a,
It has the structure shown in b and c, and consists of a large block which is a collection of small blocks, and the bank number and address of the kanji placed at the beginning of the kanji group are stored at the beginning of the small block. After that, the compressed data length of the first kanji, the compressed data length of the second kanji, and the compressed data length of the 15th kanji are stored. The address calculation unit 10 calculates the address of the kanji pattern data stored in the n-th small block by adding the 1st to (n-1)th compressed data lengths to the top address of the small block. Then, the access control unit 4 has a larger address than the above address and the address conversion table 9,
In response to a signal specifying a small block, the pattern memory 5 is accessed and the pattern data of kanji characters is sent to the pattern data processing section 6. Then, the pattern data processing unit 6 develops the pattern data into a display pattern, sends it to the display memory 7, and displays the kanji on a display device (not shown).

In this way, this address translation table 9
Since bank information and access information are not provided for each kanji code, the memory area can be greatly saved. Furthermore, since the kanji pattern data length can be assigned to each kanji pattern data, variable length kanji pattern data can be stored in the pattern memory without waste.

<Effects of the Invention> As is clear from the above, this kanji processing device stores the address of the kanji placed at the beginning of a kanji group at the beginning of a small block, and stores the address of each kanji in the address conversion table. Since the structure stores the difference between the address of the previous kanji and the address of the previous kanji, the memory area can be greatly saved.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the concept of the address conversion table of the present invention. FIGS. 2 a, b, and c are explanatory diagrams showing the structures of large blocks, small blocks, and small blocks, respectively. FIG. 4 is an explanatory diagram of a half-width pattern, FIG. 5 is a diagram showing a pattern using a 16×15 dot area, FIG. 6 is a block diagram of an embodiment of the present invention, and FIGS. Figure 8 is an explanatory diagram of the kanji pattern storage area, and Figure 9 is an explanatory diagram showing the concept of a conventional address conversion table.
FIG. 10 is a block diagram of a conventional kanji processing device. 1... Kanji code buffer, 4... Access control section, 5... Pattern memory, 7... Display memory, 8... Search control section, 9... Address conversion table, 10... Address calculation section.

Claims (1)

[Scope of Claims] 1. The address of the pattern memory in which the data of the kanji pattern compressed to a variable length is stored is determined based on the kanji code using an address conversion table, the data of the kanji pattern is read from the pattern memory, and the data of the kanji pattern is read out from the pattern memory. In a kanji processing device that displays kanji by converting it into display data in a data processing unit, the address conversion table has a large block consisting of a collection of small blocks, and a kanji character is placed at the beginning of a group of kanji at the beginning of the small block. The address of the kanji is stored, and the difference between that address of each remaining kanji and the address of the previous kanji is stored. Based on the information from the address conversion table and the storage location of that information, A kanji processing device comprising: an address calculation unit that calculates a storage address of kanji pattern data.