JPH0462841A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To insulate a plate electrode from a data-line electrode securely in a capacitor by a method wherein a first insulating film is formed on the plate electrode, and an oxide film, a second insulating film, is formed by a thermal oxidation method on the side wall of the plate electrode and on an impurity region to which the data line electrode is connected, and the oxide film is removed by etching. CONSTITUTION:First, a field oxide film 2, a gate oxide film 3, a gate electrode 4, a layer-to-layer insulating film 6, impurity diffusion layers 5, a capacitor lower electrode 7 and a capacitor insulating film 8 are formed in sequence on a silicon substrate 1. Then, a plate electrode 9 and an insulating film 10 are formed in order. After that, the side face of the plate electrode 9 and insulating film 10 is settled into the same shape. Next, an insulating film 11 is formed on the side wall of the plate electrode 9 and on a contact section 50 by a thermal oxidation method. Then, the insulating film 11 is etched anisotropically. As a result, the insulating film 11 formed on the contact section 50 is removed with the one formed on the side wall of the plate electrode 9 remained. Then, a data-line electrode 12 is formed from the contact section 50 up to the upper surface of the plate electrode 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device, and in particular to a data line connected to a plate electrode constituting a charge storage capacitor formed on a semiconductor substrate and a data line. The present invention relates to a method of manufacturing a semiconductor device in which a line electrode is electrically insulated from a line electrode by a first insulating film formed on a plate electrode and a second insulating film formed on a side wall of the plate electrode.

[Background Art] Demand for semiconductor memory devices has been rapidly expanding due to the remarkable spread of information devices such as computers. Furthermore, in terms of functionality, it is required to have a large storage capacity and be capable of high-speed operation. Along with this, technological development regarding higher integration, high-speed response, and high reliability of semiconductor memory devices is progressing.

Among semiconductor memory devices, DRAM is known as one that allows random input/output of stored information. Generally DR
An AM is a device that consists of a memory cell array section, which is a storage area that stores a large amount of memory information, and a peripheral circuit section that is necessary for input/output with the outside.For example, regarding the manufacturing method of the memory cell array section, Japanese Unexamined Patent Publication No. 63-19355
It is disclosed in Publication No. 5. FIGS. 2A and 2B are cross-sectional structural diagrams for explaining the manufacturing process of a memory cell array section of a conventional DRAM disclosed in Japanese Patent Laid-Open No. 193555/1983. First, the configuration of a memory cell array section of a conventional DRAM will be described with reference to FIG. 2B. The memory cell array section includes a silicon substrate 1,
An element isolation oxide film 2 for element isolation formed on a silicon substrate 1, an impurity diffusion layer 5 formed at a predetermined interval in a region surrounded by the element isolation oxide film 2, and an adjacent impurity diffusion layer 5. A gate electrode 4 formed between layers 5 via a gate oxide film 3, an interlayer insulating film 6 for insulation formed to cover the gate electrode 4, and an impurity diffusion layer adjacent to the element isolation oxide film 2. The capacitor lower electrode 7 formed on the layer 5, the capacitor insulating film 8 formed on the capacitor lower electrode 7, the plate electrode 9 formed on the capacitor insulating film 8, and only the upper surface portion of the plate electrode 9. The formed insulating film 10, the insulating film 21 formed on the side wall portions of the plate electrode 9 and the insulating film 10, and the side wall portion of the gate electrode 4 on the impurity diffusion layer 5 where the capacitor lower electrode 7 is not formed, and the gate electrode 4. The data line electrode 12 is connected to a contact portion 50 formed by an insulating film 21 formed on the side wall portion of the insulating film 21 and is formed to extend on the insulating film 21 and the insulating film 10 . Capacitor lower electrode 7, capacitor insulating film 8, and plate electrode 9 constitute a capacitor for storing charges corresponding to data.

Next, the manufacturing process will be described with reference to FIGS. 2A and 2B. First, as shown in FIG. 2A, an element isolation oxide film 2 is formed on a silicon substrate 1. Gate oxide film 3, gate electrode 4, and interlayer insulating film 6 are formed, and in parallel therewith, impurity diffusion layer 5 is formed. A capacitor lower electrode 7 is formed in a predetermined shape on the element isolation oxide film 2 and the interlayer insulation film 6 so as to be connected to the impurity diffusion layer 5 surrounded by the element isolation oxide film 2 and the interlayer insulation film 6. After forming a capacitor insulating film 8 on the capacitor lower electrode 7, a plate electrode 9 is formed.

An insulating film 10 is deposited on plate electrode 9 using the CVD method. By patterning the plate electrode 9 and the insulating film 10 at the same time, the plate electrode 9 and the insulating film 1
Make the side parts of 0 the same shape. Then, an insulating film 21 is deposited using the CVD method. By performing anisotropic etching, the insulating film 21 is etched until the silicon substrate 1 of the contact portion 50 is exposed. By this etching, an insulating film 21 is formed on the side wall portions of the plate electrode 9 and the insulating film 10 and on the side wall portion of the gate electrode 4 on the contact portion 50 side. Impurity diffusion layer 5 of contact portion 50
A data line electrode 12 is formed on the insulating film 21 and the insulating film 10. Here, the plate electrode 9 constituting the capacitor is electrically insulated from the data line electrode 12 by an insulating film 10 and an insulating film 21 formed on the side wall portions of the plate electrode 9 and the insulating film 10. .

[Problems to be Solved by the Invention] As described above, in the conventional method for manufacturing the memory cell array portion of a DRAM, the insulating film 21 for insulating the plate electrode 9 and the data line electrode 12 is deposited by the CVD method. It was formed by subsequent anisotropic etching.

However, in this method of depositing the insulating film over the entire surface and then performing anisotropic etching, the insulating film 21 will remain on the side wall portions of the contact portions 50 as well. As a result, the diameter of the contact hole becomes smaller, resulting in problems such as increased electrical resistance and poor conduction.

In other words, in the conventional method for manufacturing the memory cell array section of a DRAM, when forming the insulating film 21 for insulating the plate electrode 9 and the data line electrode 12 constituting the capacitor, the insulating film is also formed on the side wall portion of the contact section 50. 21 remains, the diameter of the contact hole becomes small, making it impossible to secure a sufficient contact area, resulting in problems such as increased electrical resistance and poor conduction.

The present invention was made to solve the above problems, and provides a semiconductor device that can reliably insulate a capacitor plate electrode and a data line electrode without reducing the contact area of the data line electrode. The purpose is to provide a manufacturing method for.

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes a method for manufacturing a semiconductor device in which a plate electrode forming a charge storage capacitor formed on a semiconductor substrate and a data line electrode connected to a data line are placed on the plate electrode. A method for manufacturing a semiconductor device that is electrically insulated by a first insulating film formed and a second insulating film formed on a side wall of a plate electrode, the first insulating film being formed on the plate electrode. a step of forming an oxide film to become a second insulating film by thermal oxidation on the impurity region to which the side wall of the plate electrode and the data line electrode are connected; and removing the membrane.

[Function] In the method for manufacturing a semiconductor device according to the present invention, a first insulating film is formed on the plate electrode, and a second insulating film is formed by thermal oxidation on the side wall of the plate electrode and the impurity region to which the data line electrode is connected. An oxide film that becomes an insulating film is formed, and by etching the oxide film, the oxide film formed on the impurity region is removed. No insulating film remains.

[Embodiments of the invention] Embodiments of the present invention will be described below based on the drawings.

FIGS. 1A to 1C show a DR according to an embodiment of the present invention.
FIG. 3 is a cross-sectional structural diagram for explaining a manufacturing process of an AM memory cell array section. First, the configuration of the memory cell array section of the DRAM of this embodiment will be described with reference to FIG. 1C. The memory cell array section includes a silicon substrate 1, an element isolation oxide film 2 for element isolation formed on the silicon substrate 1, and a region surrounded by the element isolation oxide film 2 on the silicon substrate 1 at a predetermined interval. an impurity diffusion layer 5 formed in the above manner, a gate electrode 4 formed between the adjacent impurity diffusion layers 5 with a gate oxide film 3 interposed therebetween, and an interlayer insulating film for insulation formed to cover the gate electrode 4. 6, a capacitor lower electrode 7 formed on the impurity diffusion layer 5 located between the element isolation oxide film 2 and the gate electrode 4 so as to extend over the element isolation oxide film 2 and the interlayer insulating film 6, and a capacitor lower electrode 7. capacitor insulating film 8 formed on the upper surface portion and side wall portion of plate electrode 7; plate electrode 9 formed on capacitor insulating film 8; insulating film 10 formed on the upper surface portion of plate electrode 9; An insulating film 1 is formed on the insulating film 11 formed on the side wall portion and on the contact portion 50 on the impurity diffusion layer 5 where the capacitor lower electrode 7 is not formed.
1 and 10, and a data line electrode 12 formed to extend onto the plate electrode 9 through the electrodes 1 and 10. In this way, in this embodiment, the plate electrode 9 constituting the capacitor
are electrically insulated from data line electrode 12 by insulating films 10 and 11.

Next, the manufacturing process of this embodiment will be explained with reference to FIGS. 1A to 1C. First, as shown in FIG. 1A, an element isolation oxide film 2 for element isolation is formed on a silicon substrate 1. Next, gate oxide film 3 is placed in a predetermined position.
Then, a gate electrode 4 and an interlayer insulating film 6 are formed, and in parallel thereto, an impurity diffusion layer 5 is formed. Capacitor lower electrode 7 is formed on impurity diffusion layer 5 located between element isolation oxide film 2 and gate electrode 4 so as to extend over element isolation oxide film 2 and gate electrode 4 . A capacitor insulating film 8 is formed on the capacitor lower electrode 7. After depositing the plate electrode 9 and depositing the insulating film 10 using the CVD method, the plate electrode 9 and the insulating film 10 are simultaneously patterned to make the side portions of the plate electrode 9 and the insulating film 10 have the same shape. . Next, as shown in FIG. 1B, an insulating film 11 is formed on the side wall portion of the plate electrode 9 and the contact portion 50 by a thermal oxidation method.

By anisotropically etching the insulating film 11, the insulating film 11 formed on the contact portion 50 is removed while leaving the insulating film 11 formed on the side wall portion of the plate electrode 9.

Next, as shown in FIG. 1C, a data line electrode 12 having a shape extending to the upper surface of the plate electrode 9 is formed in the contact portion 50.

As described above, in the manufacturing method of this embodiment, the insulating film 11 for insulating the plate electrode 9 and the data line electrode 12 is formed using the thermal oxidation method, and the insulating film 11 is formed using the conventional CVD method. The inconvenience that the insulating film remains on the side wall portion of the contact portion 50, which has been a problem with the forming method, does not occur. Therefore, it is possible to solve the conventional problem that by forming an insulating film to insulate the plate electrode of the capacitor and the data line electrode, the diameter of the contact hole becomes small and a sufficient contact area cannot be secured. , the plate electrode and the data line electrode can be reliably insulated without reducing the contact area of the data line electrode. Although this embodiment shows an example in which the insulating film 10 formed on the upper surface portion of the plate electrode 9 is formed by the CVD method, the present invention is not limited to this, and may be formed using a thermal oxidation method. good.

[Effects of the Invention] As described above, according to the present invention, the first insulating film is formed on the plate electrode constituting the capacitor, and the first insulating film is formed on the side wall of the plate electrode and the impurity region to which the data line electrode is connected. Forming an oxide film that will become a second insulating film by thermal oxidation,
By removing the oxide film formed on the impurity region by etching, the second insulating film does not remain on the side wall of the contact portion of the data line electrode as in the conventional case, so the contact area of the data line electrode can be reduced. It has now become possible to provide a method of manufacturing a semiconductor device that can reliably insulate the plate electrode of a capacitor and the data line electrode without reducing the voltage.

[Brief explanation of drawings]

FIGS. 1A to 1C show a DR according to an embodiment of the present invention.
Figures 2A and 2B are cross-sectional structural diagrams for explaining the manufacturing process of the AM memory cell array section.
FIG. 3 is a cross-sectional structural diagram for explaining a manufacturing process of an AM memory cell array section. In the figure, 1 is a silicon substrate, 2 is an element isolation oxide film,
3 is a gate oxide film, 4 is a gate electrode, 5 is an impurity diffusion layer, 6 is an interlayer insulating film, 7 is a capacitor lower electrode, 8 is a capacitor insulating film, 9 is a plate electrode, 10 is an insulating film, 11
1 is an insulating film, and 12 is a data line electrode. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A plate electrode forming a charge storage capacitor formed on a semiconductor substrate and a data line electrode connected to a data line are connected to a first insulating film formed on the plate electrode and the plate electrode. A method for manufacturing a semiconductor device electrically insulating by a second insulating film formed on a side wall of the plate electrode, comprising: forming a first insulating film on the plate electrode; forming an oxide film to serve as a second insulating film by thermal oxidation on the impurity region to which the data line electrode is connected; and removing the oxide film formed on the impurity region by etching. A method for manufacturing a semiconductor device.