JPH0463378B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an AC-driven liquid crystal display device using a transistor matrix array.

[Technical background of the invention and its problems]

In recent years, liquid crystal display devices in which switching transistors are arranged in a matrix array and used as a driving circuit have been attracting attention. In this method, image information is accumulated in each dot of a switching transistor matrix provided on a substrate, and this image information is displayed at a position corresponding to each dot of a liquid crystal layer provided on a matrix array. This method aims to obtain a desired image by using a CRT, and in principle, it is possible to realize a display device that is much thinner than the method using a CRT, which has been the mainstream of conventional display devices. In addition, the display principle of CRT is that a high-energy electron beam collides with a fluorescent material to emit light, so not only is the entire screen displayed at all times, but it also takes advantage of the afterimage phenomenon of the human eye. There was a problem with visibility due to Fritzker noise. On the other hand, a liquid crystal display device using a transistor matrix displays images almost all the time, and can provide a more natural screen than a CRT. Furthermore, it has features such as a flat screen compared to CRT, no need for a high-voltage power supply, no need for a vacuum area, and because it is an all-solid-state device, it is small and lightweight and has sufficient strength. .

FIG. 1 is a schematic diagram showing the basic configuration of a transparent transistor matrix array. Display screen is vertical m
The book is divided into a matrix of n horizontal lines, with a total of m.
It is divided into n unit pixels. At the intersections C ₁₁ , C ₁₂ ...C _ij ...C _no of each matrix, a pixel circuit with a memory function is constructed using switching transistors, and the image information of each pixel is stored here.
According to this information, display is realized in an area corresponding to each pixel of the liquid crystal provided on the matrix array.

A specific pixel circuit having a simple configuration as shown in FIG. 2 is used. This is because, in order to obtain a high-definition display screen, the size of the matrix m·n is very large, so a simpler circuit is desired in order to create a matrix array with a high yield. In FIG. 2, 21 is a switching transistor, 22 is a liquid crystal layer, and 23 is a switching transistor.
is a capacitor that stores image signals. Also, 2
4 is a capacitor for cutting a DC component used when driving the liquid crystal with AC, and is set to be sufficiently large compared to the capacitance of the liquid crystal layer. The gate of the transistor 21 is connected to the i-th address line X _i , and the source electrode is connected to the j-th data line Y _j . Address line X _i and data line
Y _j is connected to the power supplies of V (X _i ) and V (Y _j ), respectively. Transistor 21 is connected to address line X _i
When the ON state signal is input, the channel of the transistor 21 becomes conductive, and at this time, the image signal prepared on the data line Y _j is transferred to the capacitor 23.
The signal is stored in the capacitor 23 while the gate voltage V(X _i ) is zero. The liquid crystal 22 is driven in accordance with this accumulated image signal. Note that all the other transistors on the address line X _i are also turned on at the same time, and the image signals V (Y _i ), prepared on each data line Y _j at that time, respectively.
V( _Y2 )...V( _Yo ) are accumulated in each image circuit C _i1 , C _i2 ... _Cio . Similarly, the image signals on each address line are accumulated one after another in the manner of X _i+1 , X _i+2 , . . . , and the signals for the entire screen are written.

Figure 3 shows _image signals _{V di ,}
This diagram schematically shows how V _di+1 is written. In the image signals φ _i,j and φ _i+1,j in FIG.
The solid line shows the voltage waveform during ideal operation. That is, writing of the image signal of pixel C _i,j starts from time t _i1 , ends at t _i1 +ΔT, and at the same time the gate voltage V (X _i ) becomes zero, and then after one field period T _f again at time t _i2
As long as the image signal is written to C _ij ,
φ _i,j will be held in the image signal V _di .

However, in reality, as shown in FIG. 2, there is a parasitic capacitance 25 between the gate and drain of the switching transistor 21, so that at the moment the gate pulse becomes zero, the effect of this parasitic capacitance 25 causes an accumulation in the capacitor 23. The voltage φ _i,j has a third
A voltage drop ΔV as shown by the broken line in the figure occurs.

By the way, materials for switching transistors include crystalline, polycrystalline, amorphous Si,
CdSe, Te, CdS, etc. are used. Particularly in recent years, the area of transistor matrix arrays has become larger,
Thin film transistors (TFTs) using polycrystalline semiconductors or amorphous semiconductors, which can be manufactured using low-temperature processes, are attracting attention in order to reduce costs. In these TFTs, the field effect mobility is higher than that using crystalline Si.
Since it is considerably lower than that of MOS transistors,
In order to sufficiently write the image signal into the capacitor within the time ΔT shown in FIG. 3, it is necessary to increase the channel width of the TFT and to make the on-resistance of the channel sufficiently low. When such a large TFT is used, the parasitic capacitance 25 becomes so large that it cannot be ignored, and the voltage drop ΔV mentioned above also becomes very large.

On the other hand, in order to extend the lifespan of liquid crystal materials, the liquid crystal layer is driven by alternating current. FIG. 4 schematically shows the principle of operation by this AC drive. Now, let's focus on the ijth pixel circuit. Address line X _i turns on the transistor of that line at every time interval T _f and stores the image signal of data line Y _j in capacitor 23 .
In order to AC drive the liquid crystal, the image signal voltage V (Y _j ) of the data line Y _j is applied as shown in FIG. That is, in the display state (ON state), signals such as V _D [volts], 0 and V _D [volts], 0 are sent at intervals of T _f and in synchronization with the gate pulse V (X _i ). In the opposite state (OFF state), V _D /2 is sent in the same way, and in the ideal state where there is no voltage drop, the potential of the capacitor 23 changes as shown in [φ _i,j ] in FIG.
For example, by setting the counter electrode potential V _C of the liquid crystal layer to V _D /2, the desired display can be achieved.
However, the V _D /2 value needs to be larger than the threshold voltage of the liquid crystal layer. However, the actual potential φ _i,j of the capacitor 23 is the voltage drop ΔV mentioned above.
Due to the effect of , the leakage current of the switching transistor 21 or the leakage current of the liquid crystal layer, it changes as shown in φ _i,j shown in FIG. In the case of the example in Figure 4,
It is clear that the desired operation cannot be achieved if the potential V _C of the counter electrode of the liquid crystal layer is set to V _D /2.

Although the case where the image signal is 0, V _D /2, V _D has been described above, the same problem will occur even if the signal voltage is -V _D /2, 0, V _D /2, for example.

[Purpose of the invention]

In view of the above points, the present invention eliminates the effects of voltage drop and leakage current that occur immediately after the image signal voltage is written to the capacitor that accumulates the image signal, thereby providing a nearly complete solution that is necessary for extending the life of the liquid crystal layer. An object of the present invention is to provide a liquid crystal display device that realizes AC driving and enables highly reliable display without deterioration of contrast.

[Summary of the invention]

The present invention is based on a configuration in which the AC voltage applied to the liquid crystal varies symmetrically in positive and negative directions in the display state when performing the above-mentioned AC drive using a transistor matrix array.

To this end, the present invention is characterized in that, first, a constant DC potential difference is provided between the center potential of the AC signal voltage applied to the data line and the potential applied to the transparent electrode facing the display electrode. shall be.
Specifically, using the example shown in Figure 4, the potential V _C of the transparent electrode facing the display electrode is set to a DC potential that is a certain value lower than the value V _D /2 in an ideal state with no leakage. This setting prevents direct current voltage from being applied to the liquid crystal layer.

By the way, as explained in Fig. 4, considering the drop ΔV of the capacitor potential φij, the potential of the transparent electrode is
If V _C is the ideal value V _D /2, then V _C = V _D /2−
In some cases, it may not be possible to completely eliminate the DC voltage applied to the liquid crystal layer simply by setting ΔV. For such a case, in the present invention, secondly, the gate-drain capacitance and capacitor capacitance of the switching transistor are optimally set to increase the transparent electrode potential.
V _C =0 and no DC voltage is applied to the liquid crystal layer. The specific conditions are as follows. In the pixel circuit shown in Figure 2, the address line X _i now has a size as shown in Figure 5, V _G +V _G0 (V _G0
is a DC bias) gate pulse V (X _i ) is applied, and in synchronization with this, the peak value V _D is applied to the data line Y _j.
image signal V(Y _j ) is added. As a result, this image signal is accumulated in the capacitor 23, and its terminal voltage becomes V _D just before the gate pulse reaches V _G0 .
At this time, the charge Q stored in the total load capacitance including the capacitor 23 and the parasitic capacitance 25 is
− becomes Q−=C _S V _D + C _P (V _D −V _G −V _G0 )……(1). C _S and C _P are the capacitance values of the capacitor 23 and the parasitic capacitance 25, respectively. Here, V _G0 is smaller than the threshold voltage V _S that turns on the transistor, and V _G + V _G0 is set to a value greater than or equal to V _S. Although the effect of the DC cut capacitor 24 in FIG. 2 is not shown in equation (1), the capacitance of this capacitor 24 and the liquid crystal 22 itself are added in parallel to the capacitor 23, and C _S in equation (1) There is no problem if you think about it. Next, the total charge Q+ immediately after the gate pulse V (X _i ) becomes V _G0 and the transistor 21 is turned off is: Q+ = C _S (V _D - ΔV) + C _P (V _D - ΔV - V _G0 )
...(2) becomes. Here, ΔV is the amount of voltage drop due to the parasitic capacitance 25 described above. Since Q-=Q+
From equations (1) and (2), the voltage drop ΔV is ΔV=C _P /C _S +C _P V _G (3).

In the present invention, the image signal voltage V (Y _j ) of the data line Y _j is a voltage that repeats 0 and V _D in the display state, as shown in FIG. 5, and a voltage of V _D /2 in the non-display state. give. And at this time,
Assuming that the voltage applied to the counter electrode of the liquid crystal is V _C =0, (3)
The capacitance value of the gate-drain parasitic capacitance 25 is adjusted so that the voltage drop ΔV value in the formula becomes ΔVV _D /2.
Set C _P. This condition can be found from equation (3) as follows.

C _P = V _D /2V _G −V _D C _S ...(4) Here, the V _D and V _G values are uniquely determined from the transistor characteristics and liquid crystal characteristics, and C _S also has sufficient retention characteristics. , the C _P value is determined uniquely because it is taken as large as the area allows. If these conditions are set, as shown in Figure 5,
The alternating current driving voltage φ _i,j of the liquid crystal in the ON state is completely symmetrical in positive and negative directions.

Furthermore, as can be seen from Figure 6, which will be described later, the liquid crystal layer exhibits the most ideal state when the voltage drop ΔV is V _D /2, but even if ΔV deviates somewhat from V _D /2, Its effects are fully recognized. According to the inventors' intensive research and experiments, the ΔV value V _D /2
It has been found that it is desirable that the deviation from the threshold value Vth of the liquid crystal layer be within about ±Vth/2. That is, the desirable range of ΔV is ΔV=V _D /2±Vth/2 = Cp·Vg/(Cp+Cs)±Vth/2. However, Cs indicates the capacitance value of the image signal storage capacitor formed in parallel with the liquid crystal layer.

〔Effect of the invention〕

FIG. 6 is a diagram for explaining the effects of the present invention using the transmittance-voltage characteristics of the liquid crystal layer. Vth in the diagram
is the threshold voltage at which the liquid crystal layer starts transmitting. State A shows the most ideal operation when the voltage drop is V _D /2. In the figure, 〇 is OFF state, ×
is in the ON state, and ○ in both the positive and negative voltage regions indicates AC drive. Further, arrows in the figure indicate the effect of reducing accumulated charge due to leakage current or the like. In the present invention, as shown in state B, the voltage drop ΔV
Even if V D deviates somewhat from V _D /2, the effect is sufficiently recognized. That is, ON and OFF at B
There is no malfunction in displaying the status, and a display with a high contrast ratio can be obtained. However, if the deviation is large, there is a risk of shortening the life of the liquid crystal layer, so the deviation of the ΔV value from the V _D /2 value should be kept within approximately ±Vth/2 with respect to the threshold value Vth of the liquid crystal layer. It is desirable to do so. If the deviation is to this extent, it is possible to suppress the decrease in the life of the liquid crystal layer to some extent.

As described above, in the present invention, even if there is some leakage current in the transistors of the pixel circuit and the liquid crystal layer, it is possible to obtain ideal liquid crystal AC drive and high contrast display without display errors. Furthermore, since the opposing potential of the liquid crystal layer can also be fixed at zero, there is an advantage that no special power supply circuit is required.

Furthermore, since one end of the capacitor 23 is set to the ground potential, address lines other than the address line of the pixel to which the capacitor is connected can be used as a ground line, thereby increasing the degree of integration.

[Embodiments of the invention]

FIG. 7 is a sectional view of the main part structure of an embodiment according to the present invention. Matrix array has 220 address lines
There are 240 main and data lines, with an address line spacing of 200 μm and a data line spacing of 250 μm. The transistor matrix array is formed on a glass substrate 71 using normal thin film integrated circuit technology.
That is, address lines 72 (72 ₁ , 72 ₂ . . . ) which also serve as gate electrodes and ground lines are formed on the substrate 71 , and after depositing a SiO ₂ film 73 thereon, an amorphous Si film 74 ( 74 ₁ , 74 _{2 .} . . ) is formed. ) Data line 75 which is deposited and patterned and also serves as a source electrode.
(75 ₁ , 75 _{2 . .} . ) and display electrodes 76 ( 76 ₁ , 76 _{2 .} . . ) which also serve as drain electrodes are formed, and then covered again with a SiO ₂ film 77 to form a window on the display electrodes 76 . The display electrode 76 has a size of about 150×170 μm, and a liquid crystal layer 80 is provided on top of the display electrode 76, which is sealed with a glass substrate 78 provided with a transparent electrode 79. This transparent electrode 79 is biased to zero potential.

FIG. 8 shows the i-th and j-th pixel circuits, and 81 is a TFT made of an amorphous Si film 74. The capacitor 82 has the display electrode 76 as one terminal electrode, and the address line 72 adjacent to this pixel as the other terminal electrode. Capacitor 8
The capacitance value _C8 of 2 is approximately 3.0pF, and the capacitance value of the liquid crystal layer is approximately
It is 0.1pF. Here, in this transistor matrix, as shown in FIG. 9, the address line is normally set to zero, and V _G =20V is applied only during switching. The threshold voltage V _S of the transistor is approximately 3 (V).
On the other hand, the data signal on the data line Y _j is in the ON state and repeats 0 and V _D =10V, and in the OFF state it is repeating 5V. The capacitance value C _P of the gate-drain parasitic capacitance 83 is calculated according to equation (4), including the channel capacitance when the transistor 81 is in the ON state.
It was set to approximately 1.0 pF. As a result, the voltage applied to the liquid crystal layer 80 became as shown by φ _i,j in FIG. 9, and almost ideal AC driving was realized.

Note that when 20V is applied to the address line X _i , the adjacent address line X _i-1 has zero potential, so it functions as a ground line for the capacitor 82 . or,
When 20(V) is applied to address line X _i-1 , φ _i,j
The voltage becomes quite high, but this is instantaneous and poses no problem in operation.

Note that the present invention is not limited to the above embodiments. For example, the semiconductor material of the transistor is not limited to amorphous Si, but may be polycrystalline silicon, or may be a semiconductor material such as CdSe or CdS. However, in order to fully exhibit the effects of the present invention, the switching transistor must be a junction type (p-n
separation) is undesirable. Also, when driving with AC,
Depending on the potential of the capacitor, the transistor
Since it is turned on when it should be turned off, it is desirable to appropriately adjust the bias potential V _G0 of the address line when the channel is turned off to a value other than zero.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram of a transistor matrix array, FIG. 2 is a diagram showing a pixel circuit of a liquid crystal display device using this matrix array, and FIG. 3 is a diagram showing operating waveforms of the liquid crystal display device driven by direct current. 4 is a diagram showing operating waveforms caused by AC driving, FIG. 5 is a diagram showing operating waveforms caused by AC driving of the liquid crystal display device according to the present invention, and FIG. 6 is a diagram illustrating the effect thereof. FIG. 7 is a diagram showing the main structure of a liquid crystal display device according to an embodiment of the present invention.
The figure shows the pixel circuit, and FIG. 9 is a diagram showing the operating waveforms. 71...Glass substrate, 72 (72 ₁ , 72 ₂ ...)
...Address line (also gate electrode), 73...
SiO ₂ film, 74 (74 ₁ , 74 ₂ , ...) ... Amorphous Si film, 75 (75 ₁ , 75 ₂ ...) ... Data line (also source electrode), 76 (76 ₁ , 76 ₂ ...)
...Display electrode (also drain electrode), 77...SiO ₂
Film, 78...Glass substrate, 79...Transparent electrode, 8
0...Liquid crystal layer, 81...Thin film transistor, 82
... Capacitor, 83 ... Parasitic capacitance between gate and drain.

Claims (1)

[Scope of Claims] 1. A plurality of address lines and data lines that are orthogonal to each other, and switching transistors that are arranged at the intersections of these address lines and data lines, and whose sources and gates are connected to the data lines and the address lines, respectively. , and a transistor array having a display electrode connected to the drain of each transistor, and a transparent substrate having a transparent electrode facing the transistor array, and a liquid crystal sealed therebetween, and a gate pulse applied to the address line. In a liquid crystal display device in which an alternating current display signal voltage is supplied to the data line so that signal voltages of alternate polarity are synchronously applied to the liquid crystal, Cp is the parasitic capacitance between the gate and drain, and Vg is the gate voltage. , where Cs is the capacitance value of an image signal storage capacitor formed in parallel with the liquid crystal layer, and Vth is the threshold value of the liquid crystal layer, the central potential of the AC display signal voltage supplied to the data line and the transparent between the potential of the electrode and the center potential of the AC display signal voltage, and Cp・Vg/(Cp+Cs)±Vth/
A liquid crystal display device characterized by having a DC potential difference within 2. 2. The liquid crystal display device according to claim 1, wherein the switching transistor is a thin film transistor.