JPH0464838U - - Google Patents
Info
- Publication number
- JPH0464838U JPH0464838U JP10697490U JP10697490U JPH0464838U JP H0464838 U JPH0464838 U JP H0464838U JP 10697490 U JP10697490 U JP 10697490U JP 10697490 U JP10697490 U JP 10697490U JP H0464838 U JPH0464838 U JP H0464838U
- Authority
- JP
- Japan
- Prior art keywords
- frame synchronization
- synchronization pattern
- bits
- packet
- detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図は本発明の実施例を示すフレーム同期パ
ターン検出回路のブロツク図、第２図はその回路
の各部の出力信号の波形を示したタイミングチヤ
ート、第３図は従来のフレーム同期パターン検出
回路のブロツク図である。
１……シフトレジスタ、２……クロツク入力端
子、３……シリアル入力端子、４……パラレル出
力端子、５……メモリ、８……ラツチ回路。
Fig. 1 is a block diagram of a frame synchronization pattern detection circuit showing an embodiment of the present invention, Fig. 2 is a timing chart showing the waveforms of output signals of each part of the circuit, and Fig. 3 is a conventional frame synchronization pattern detection circuit. FIG. 1...Shift register, 2...Clock input terminal, 3...Serial input terminal, 4...Parallel output terminal, 5...Memory, 8...Latch circuit.
Claims (1)
するフレーム同期パターンを検出する回路におい
て、 前記パケツトをシリアル入力し、パケツトの一
部を構成するフレーム同期パターンのビツト数以
上のビツト数のパラレル出力を有するシフトレジ
スタと、 前記シフトレジスタの前記フレーム同期パター
ンのビツト数に等しいパラレル出力をアドレス入
力とし、前記フレーム同期パターンの検出として
認め得るビツトパターンによつて示されるアドレ
スの所定ビツトにはフレーム同期パターンの検出
を示す所定の２値データが記憶され、他のアドレ
スの前記所定ビツトには反対の２値データが記憶
された読出可能なメモリと を備え、 前記メモリ回路の出力を前記フレーム同期パタ
ーンの検出信号とすることを特徴とするフレーム
同期検出回路。[Claims for Utility Model Registration] In a circuit for detecting a frame synchronization pattern existing in a packet in a packet radio transmission system, the packet is serially inputted and the number of bits is greater than the number of bits of the frame synchronization pattern forming a part of the packet. a shift register having a parallel output of , and a parallel output of the shift register equal to the number of bits of the frame synchronization pattern as an address input, and a predetermined bit of an address indicated by a bit pattern that can be recognized as detection of the frame synchronization pattern. comprises a readable memory in which predetermined binary data indicating detection of a frame synchronization pattern is stored, and opposite binary data is stored in the predetermined bits of other addresses, and the output of the memory circuit is A frame synchronization detection circuit characterized in that the detection signal is a frame synchronization pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10697490U JPH0464838U (en) | 1990-10-12 | 1990-10-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10697490U JPH0464838U (en) | 1990-10-12 | 1990-10-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0464838U true JPH0464838U (en) | 1992-06-04 |
Family
ID=31853283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10697490U Pending JPH0464838U (en) | 1990-10-12 | 1990-10-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0464838U (en) |
-
1990
- 1990-10-12 JP JP10697490U patent/JPH0464838U/ja active Pending
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