JPH0466625U - - Google Patents

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Publication number
JPH0466625U
JPH0466625U JP10520090U JP10520090U JPH0466625U JP H0466625 U JPH0466625 U JP H0466625U JP 10520090 U JP10520090 U JP 10520090U JP 10520090 U JP10520090 U JP 10520090U JP H0466625 U JPH0466625 U JP H0466625U
Authority
JP
Japan
Prior art keywords
bus interface
output
section
data input
connector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10520090U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10520090U priority Critical patent/JPH0466625U/ja
Publication of JPH0466625U publication Critical patent/JPH0466625U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例に係るバスインタフ
エース回路のブロツク図、第2図はバスインタフ
エース回路を利用したデータ入出力の構成図、第
3図は従来のデータ入出力を示すブロツク図であ
る。 1,2,8……コネクタ、3……バスインタフ
エース部、4……デユアルポートメモリ、5……
スリーステートバツフア、6,12……バスイン
タフエース専用基板、7……入出力用基板、11
……入出力部、13……データ入出力基板。
Fig. 1 is a block diagram of a bus interface circuit according to an embodiment of the present invention, Fig. 2 is a block diagram of data input/output using the bus interface circuit, and Fig. 3 is a block diagram showing conventional data input/output. It is a diagram. 1, 2, 8... Connector, 3... Bus interface unit, 4... Dual port memory, 5...
Three-state buffer, 6, 12... Bus interface dedicated board, 7... Input/output board, 11
...Input/output section, 13...Data input/output board.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] システムバスにコネクタを介して接続されるバ
スインタフエース部と、データ入出力部に入出力
用コネクタを介して接続され、上記バスインタフ
エース部とデータ入出力部との間の送受信データ
を一時記憶するデユアルポートメモリとを具備し
たことを特徴とするバスインタフエース回路。
The bus interface section is connected to the system bus via a connector, and the data input/output section is connected via the input/output connector, and temporarily stores data sent and received between the bus interface section and the data input/output section. A bus interface circuit characterized in that it is equipped with a dual port memory.
JP10520090U 1990-10-08 1990-10-08 Pending JPH0466625U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10520090U JPH0466625U (en) 1990-10-08 1990-10-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10520090U JPH0466625U (en) 1990-10-08 1990-10-08

Publications (1)

Publication Number Publication Date
JPH0466625U true JPH0466625U (en) 1992-06-12

Family

ID=31850809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10520090U Pending JPH0466625U (en) 1990-10-08 1990-10-08

Country Status (1)

Country Link
JP (1) JPH0466625U (en)

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