JPH0467200B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to speech processing, and more particularly to speech signal encoding devices. BACKGROUND OF THE INVENTION As is known, normal speech includes silent periods that constitute part of the intelligence being conveyed. Silent periods occur between sentences, clauses, words, and words. Originally, silent periods are accepted by listeners as a natural attribute of speech. However, silence represents an important part of the speech pattern. When a speech signal is encoded for transmission over a communication channel or for storage in a storage device, the code sequences corresponding to the unvoiced portions may be removed for use for other purposes. It occupies a fragment of the encoded signal that can be used for other purposes. Of course, in order to understand the message, it is necessary to reproduce the unvoiced signal at an appropriate position in the speech pattern. However, the stored digital signal,
Alternatively, the encoding for silence can be simplified so that the transmitted digital signal can be created much more easily. In this way, the efficiency of the communication system is improved. Many methods are possible when digitally encoding speech signals. Converting sampled speech directly to binary form can be performed by pulse code modulation. The conversion process includes quantizing each speech sample into a separate set of levels and encoding the selected quantization level. In adaptive pulse modulation, where the quantization of the speech signal samples is adaptive to the input signal level, this form of pulse modulation uses significantly fewer bits per digital sample, resulting in improved performance. In such an adaptive system, the step size in the quantizer can be varied to match the statistical characteristics of the input signal. Differential pulse modulation systems encode the differences between input signal samples rather than sampling the input signal itself to improve encoding efficiency. However, these encoding devices do not accurately distinguish between active parts and inactive parts of an input signal. As a result, the silent period of the signal has an adverse effect on the intelligence transmission efficiency. U.S. Pat. No. 4,280,192 discloses an arrangement for minimizing space for digitally storing analog information, in which an analog input signal, such as speech, is stored in the form of a continuously varying ramp rate. It converts to a stream of delta modulation (ADM) symbols. A voice activated switch detects the start of a pause period when the analog signal falls below a predetermined level. The pause time is determined by a counter that stops operation when the speech signal rises above a predetermined level. A special pause code containing timing information is then inserted into the digital code stream. The combination of a voice activated switch and a timing device is intended to eliminate repetitive symbols during idle periods of the analog signal. As is known, voice-activated switches are designed to operate at low speeds to prevent interphrase clipping, and include a device for inhibiting the detection of short silent periods. As a result, the system described in US Pat. No. 4,280,192 utilizes compensated delays to facilitate insertion of pause codes at appropriate locations in the data stream. However, because of the inherent delay in voice-activated switches, it is difficult to detect short periods of silence that occur at speeds higher than the speed of speech. U.S. Pat. No. 4,053,712 discloses an adaptive digital encoding and decoding device,
To reduce the overall bit rate, a special encoding bit pattern is replaced by an idle pattern in the CVSD output bit stream. Idle pattern detection is performed by converting the CVSD output to an analog signal and comparing the analog signal to a fixed amplitude threshold. Regeneration of analog speech signals for detection of silence requires additional decoding equipment, which increases the cost of encoding. Although the existence of a direct amplitude threshold is relatively insensitive to speed limitations in silent detection, it increases sensitivity to noise. As a result, it is difficult to distinguish between silence and speech, making the device more susceptible to speech clipping. SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved digital encoding device for economically removing silent periods without imposing speed limitations. SUMMARY OF THE INVENTION The problems of prior art silence cancellation schemes are solved by the present invention by using step size related signals already generated in an adaptive pulse modulation method for detecting silent periods. be able to. These step size related signals are representative of the energy content of the applied speech signal, but are not affected by the delay devices present in the voice activated switch. the result,
Although analog signal processing steps are eliminated, detection of silent periods is not limited to a predetermined rate and no equipment is needed to properly place silent period symbols. The present invention is directed to a speech processing device for converting speech patterns into adaptive digital code sequences. It detects the silent periods of the pattern and generates a digital code representing each silent period. The adaptive digital code and the silent period code are combined to form a digital signal representative of the speech pattern. The process of converting the patterns into adaptive digital codes includes forming a signal corresponding to the adaptive step size for each digital code. There, first and second threshold signals are generated. Detecting a silent period involves two steps: generating a silent period signal when the signal corresponding to the adaptive step size disappears below a first threshold value, and generating a silent period signal when the adaptive step size related signal increases to a value greater than a second threshold during the silent period. and terminating the period signal. DETAILED DESCRIPTION FIG. 1 is a diagram illustrating a digital voice communication device according to the present invention. Referring to FIG. 1, a speech pattern is applied to microphone 101 and the speech signal obtained from microphone 101 is applied to attenuator and sampling circuit 103. Referring to FIG. According to the circuit 103, the applied speech signal is attenuated in a known manner and the clock signal generator 10 is
7 allows the signal to be sampled at a predetermined rate. For example, if the cutoff frequency of the low frequency filter is 3.2kHz, the sampling speed is
For example, it can be 8kHz. circuit 103
An example of a speech sample from is representative of the waveform of a speech signal. Analog-to-digital converter 105 is circuit 103
and converting each speech sample into a digitally encoded signal having a value corresponding to the amplitude of the speech sample. converter 105
The digitally encoded signal from is applied to the input of an adaptive encoder 110. As is known from the prior art, an adaptive encoder is capable of converting the digital signal from the converter 105 into a more efficiently encoded signal with a good signal-to-noise ratio than before. An adaptive encoder that can be used in the circuit of FIG. 1 is shown in the logic diagram of FIG. Figure 2 shows adaptive differential pulse code modulation (adaptive differential pulse code modulation).
differential pulse code modulation (ADPCM)
Although the diagram shows a coding device for use in the present invention, it should be understood that other types of adaptive code modulators can also be used. In differential pulse code modulation, each sample
The difference between Xn and the predicted value of said sample Xn) based on past samples lies in the quantization and encoding for transmission. Depending on the number of levels of the quantizer, a step-wave approximation signal to the speech signal is generated. Differential encoding can take advantage of a lower bit rate of 2 bits per sample than traditional PCM encoding by not adding too much redundancy to the signal. . Generally, differential encoding uses a quantizer with a fixed step size. The adaptive device includes a device for monitoring the digital output from the encoding device. The effective step size can be varied in the quantizer so that it is responsive to the differential signal amplitude at the output. In this method, the quantization of the input signal is optimized. Referring to FIG. 2, the sequence of digital signals Xn of analog-to-digital converter circuit 105 is applied to one input terminal of adder 201. Referring to FIG. At the other input of adder 201, the previous signal sequence
Current digital signal based on Xn _-1 , Xn _-2 ,…
Receive the predicted value of Xn. The difference between the current signal Xn and the predicted signal Xn appears at the output of adder 201,
This is fed to a quantizer 203. The quantizer compares the differential signal from adder 201 with a preset set of quantizer levels and generates a signal corresponding to the nearest quantizer level. The quantized difference signal present at the output of the quantizer 203 is applied to an encoder 207, which operates adaptively to form a digital code Cn corresponding to the applied quantized signal level. The output of encoder 207 is a sequence of digital symbols representing the quantized difference between the speech signal sample and its predicted value. The quantized difference signal at the output of the quantizer 203 is also applied to one input terminal of the adder 209, which
Adder 209 uses the predicted sample value obtained from 5.
are added at . The sum signal from adder circuit 209 is provided to an input terminal of prediction device 205 .
As a result, the output of prediction device 205 is updated to represent the predicted value of the next speech sample signal Xn ₊₁ . Step size generator circuit 210 receives encoder output code Cn. Further, a step size generating circuit 210 responsive to the code Cn samples the step size signal Δn in order to adjust the level in the quantizer 203 according to the relative amplitude of Cn. When Cn is large, the step size signal Δn is effective for expanding the step size in the quantizer 203, thereby making the quantizer more compatible with high amplitude signals. For small values of Cn, the quantizer matches the step size to accommodate low amplitude signals. In this method, a quantizer is used to adapt the input signal to the expected level. The use of adaptive encoders and differential encoders in combination is described in the book “Digital Processing of Speech Signals,” co-authored by LLR Rabiner and RWSchafer.
"Speech Signals" (1978, published by Prentice Hall, copyright: Bell Telephone Laboratories). Next, the adaptive encoder 110 was published in the MC68000 Design Module User Guide published by Motorola in 1980.
Module Use's Guide, Motorola Inc., 1980)
It is based on Motorola's 68000 type microprocessor, which is described in . The microprocessor operates according to a predetermined series of instructions stored in read-only storage. Appendix A lists the permanent storage instructions required for the ADPCM encoded signal from the A/D converter 105 in the FORTRAN language. In FIG. 2, the step size generator 210 operates according to d _o =βd _o-1 +mC _o (1), and the above equation is expressed by the encoder 2
This is to form a signal d _o corresponding to the logarithm of the step size responsive to the last output (C _o-1 ) of the 07. β is a constant related to the disappearance of the error, and is, for example, β=1−2 ⁻⁶ (2). d _o-1 is the previous logarithmic step size signal, and m is a scaling factor for adjusting the magnitude of the step size in relation to the expected value of the dynamic range of the signal and the number of levels of the quantizer. . In FIG. 2, the digitally encoded signal Cn is applied to the address input terminal of the multiplication factor generator 211;
Multiplier generator 211 is a programmable read-only storage device employed in a conventional and known manner so that for each digital code input Cn applied to its address input, a preassigned output mCn is obtained. It is established from (PROM). m is m=log _Q M (3) where, for the lowest 4 levels, m is 0.85
and 1.2 for the fifth and sixth levels
It is. Also, M=1.6 (seventh level) 2.4 (eighth level) Q=D ^1/S . D is the dynamic range of the input signal Xn, and S is the number of step sizes. The delay register 215 holds the previous logarithmic step size signal do _-1 . In response to clock signal CLT from clock signal generator 107 for the nth input, signal do _-1 is output to shifter 217.
and one input terminal of the subtractor 219. Shifter 217 is a coded signal
A wiring configuration can be used to shift d _o-1 to the right by six places to form signal 2 ^-6 d _o-1 and reallocate the encoded signal bits. The subtracter 219 receives the signal d _o-1 from the register 215 and further receives the signal 2 ^-6 d _o-1 from the shifter 217 and operates to generate a differential signal (1-2 ⁶ ) d _o-1. It is something to do. The output of subtracter 219 is added to signal mC _o in adder 212, and the resulting _do signal is placed in register 215 by clock pulse CLT. The signal d _o in register 215 represents the logarithm of the encoder step size Δn supplied to quantizer 203 . To form the Δn signal, the digital code d _o
is applied to the address input terminal of the step size signal forming device 221. Forming device 221 is a programmable read-only memory (PROM);
A list of relationships between d _o and Δn is stored in the PROM. For each d _o address input, a corresponding Δn step size signal is output from the PROM. The logarithmic step size signal d _o is the speech sample Xn
represents the energy of a sequence of , and can be used to determine silent periods in a speech signal. In contrast to real voice motion switches and other speech extant signal detectors, logarithmic steps can be performed at speeds much faster than the speed of phrases without noise or speech clipping being introduced into the resulting encoded speech signal. The size signal changes.
As a result, silent period detection responsive to changes in the logarithmic step size signal is performed by the present invention with virtually no speed limitations. Detection of silent periods is performed in silence detector 115, which is shown in more detail in FIG. Third
Referring to the figure, signal _do from adaptive encoder 110 is applied to the a input terminal of amplitude comparator 301 and the c input terminal of amplitude comparator 305. Comparator 305 is enabled when the signal at d _o disappears to a value less than threshold level signal TH1. The enabled output from comparator 305 is applied to flip-flop 320 via OR gate 315 to set the flip-flop. When set, flip-flop 320 enables SF to indicate that a silent period has begun.
Output a signal. The output of comparator 301 is applied to AND gate 310, while signal SF is applied to AND gate 310.
Alert gate 310. B of comparator 301
The threshold signal TH2 applied to the input terminal corresponds to the onset level of speech. signal
When d _o is greater than the threshold signal TH2, comparator 3
01 is enabled. During the silent period,
Only when the logarithmic step size signal _do increases by more than the threshold TH2 does the flip-flop 3
20 is reset via AND gate 310 and OR gate 315. The dynamic range of the input speech signal is the first
If preset by a signal compression device connected between microphone 101 and filtered sampling circuit 103 in the figure, the threshold signal
TH1 and TH2 can be at fixed voltage levels. However, such compression devices send out speech signals as warnings and the characteristics of the speaker's voice become unnatural. As a result, the reproduced speech pattern may not sound like the speaker. In accordance with the present invention, speech signal compression devices, as commonly employed, are eliminated through the use of adaptive threshold generator 112 of FIG. The adaptive threshold generator changes the threshold signals TH1, TH2. The threshold signals TH1, TH2 can be varied by logarithmic step size signals, so that the characteristics of the speaker's voice are not changed by the equipment required for devoicing. Adaptive threshold generator 112 is shown in more detail in FIG. Referring to FIG. 4, level signal generator 401 generates a preset limit signal L corresponding to the expected value of the lowest logarithmic step size signal consistent with the active speech signal input to the circuit of FIG.
d A preset level signal HW1, HW corresponding to the amount of difference normally expected between _nax and the silent threshold.
2. Generally, d _nax is the maximum value of the d _o signal sequence from adaptive encoder 110 . Register 427 is initially set to L and the sample
Store the maximum value of the logarithmic step size signal up to X _o-1 . The d _nax signal from register 427 is compared in amplitude comparator 403 with the current logarithmic step size signal _do . If d _o is greater than d _nax , the comparator is enabled. Comparator 4
The enable signal from 03 is a three-value switch 409
is opened and the three-value switch 405 is closed, whereby a signal representing d _o which is greater than d _nax is transmitted to the a input terminal of the subtracter 415 and the shifter 41.
2. If signal d _nax is greater than signal d _o , comparator 403 remains disabled and the d _nax signal from register 427 is passed through ternary switch 409 to the a input of subtractor 415 and shifter 412. is supplied to the input of Shifter 412 shifts the input 10 digits to the right,
The subtracter 415 sends the signal d _nax ( ^1-2-10 ) to the b input of the comparator 418 and the three-way switch 42.
5 input. If the L limit signal applied to comparator 418 is greater than the output of subtractor 415, comparator 418 is enabled. In that case, the three-value switch 420 turns on,
Limit signal L is placed in register 427. If the output of subtractor 415 is less than limit signal L, comparator 418 remains disabled. Three-way switch 425 turns on and the contents of register 427 receive the largest logarithmic step size signal that is less than _or equal to logarithmic step size signal do. The signal d _nax from register 427 is sent to subtracter 430
subtractor 430 operates to form a signal d _nax -HW1. This threshold level varies with the maximum logarithmic step size signal d _nax and the silent threshold changes adaptively. Subtractor 440 forms the signal TH2=d _nax -HW2, and the speech onset threshold can be adaptively varied by the maximum logarithmic step size signal. In this way, silent periods of the speech signal are detected without changing the characteristics of the speaker. The SF output of silence detector 115 is provided to silence counter 120, as shown in more detail in FIG. Referring to FIG. 5, the SF signal is applied to one input terminal of AND gate 505, and
It is also added to the input terminal of the inverter 507. During normal speech, signal SF is disabled and the output of inverter 507 presets counter 510 to its zero position. At the beginning of a silent period, signal SF is enabled and code clock signal CLT is input to counter 510 through AND gate 505. The contents of counter 510 increment until the end of the silent period is detected. Latch 515 is enabled at the end of a silent period, thereby transferring the silent period count signal from counter 510 to latch 515. Silent period count signal from latch 515
SCT is provided to the input of code processing unit 125;
The code processing unit 125 is an adaptive encoder 110.
The C _o code generated in
Receive SF signals together. The code processing unit 125 forms a message consisting of the combination of the output code C _o and the silent period code,
It is adapted to provide messages to communication network 140 as needed. The processing device 125 is as described above.
Published by Motorola in 1980
MC68000 Design Module User's Guide
Motorola, Inc., 1980). The code combinations are stored in read-only memory (ROM) of processing unit 125 and executed by a fixed set of instructions. These instructions are in Appendix B
It is expressed in the FORTRAN language (FORTRAN). The silent periods removed from the speech signal are represented by a special silent symbol SC appearing ahead of the silent count signal SCT from the silent counter 120. In the circuit of FIG. 1, the unvoiced code is selected as the maximum amplitude output of the adaptive encoder. For a 4-bit ADPCM code structure, the maximum amplitude output combinations are ₈₇₁₆ . This code was chosen because its probability of occurrence is low. To avoid false detection of silent periods, the maximum amplitude output symbol occurring in C _o must be replaced. 1st
The sign change circuit shown operates to replace 87 sign combinations by 96 ₁₆ combinations, minimizing signal distortion. The sign change circuit is shown in more detail in FIG. Referring to FIG. 6, the output of adaptive encoder 110 is output to register 6 at each clock pulse CLT.
10. C _o in register 610
The code is typically transferred sequentially through ternary switch 615 to register 625, and the C _o-1 code in register 625 appears at the output of ternary switch 601. The outputs of registers 610 and 625 representing the current pair of encoder signals are output to comparator 63.
5 is compared with the code combination 87 ₁₆ . These codes are provided by signal generator 632, as is known in the art. register 61
Upon detection of the 87 ₁₆ column at 0,625, the output of comparator 635 is enabled and the output of inverter 637 is disabled. In response to the disabled signal CC, the ternary switches 601 and 615 are disabled while the ternary switches 605 and 620 are enabled by the signal CC. from generator 632
9 ₁₆ signals are thereby inserted into register 625,
The 6 ₁₆ signals from the generator 632 are sent to the three-way switch 60.
5 into the data stream. The output of sign changer 130 can then be changed as required. The flow diagram of FIG. 7 represents the sequence of operations performed in FIG. 1, and the waveforms shown in FIG. 8 illustrate the signals and symbols at various points in the circuit of FIG. Prior to reception of a speech signal at microphone 101, silent counter 120 is reset to a zero state. Signal SF from silence detector 115 is disabled and threshold generator 11
The maximum logarithmic step size signal d _nax stored at step 2 is set to zero. These operations are directed to index process 701. The speech signal displayed between time t ₀ and time t ₁ on waveform 801 does not correspond to a silent period. As a result, the logarithmic step size _signal do obtained from the speech waveform (shown on waveform 805) is greater than the threshold signal TH1 of waveform 809. Silence detector 115
The unvoiced flag signal SF from is reset and the output code C _o is provided to code processor 125 via code changer circuit 130 . These codes C ₁ ,
C ₂ ,...C _o corresponds to normal speech, and the waveform 81
3. Referring to FIG. 7, each code clock pulse
Upon creation of a CLT, a queuing process 708 is activated. In response to the code clock pulse CLT, adaptive encoder 110 generates the next adaptive encoder output signal C _o as shown in step 710.
form. Logarithmic step size signal _do and step size signal Δn are formed in the adaptive encoder by step 712, and the _do and d _nax signals are compared in adaptive threshold generator 112 by decision step 715. If the logarithmic step size signal _do is greater than d _nax , then the d _nax signal is replaced with the current _do signal (step 718). The _do signal is then tested in silence detector 115 to determine whether it is less than the lower threshold signal from threshold generator 112 or whether _they are equal. (See decision step 720.) Between time t ₀ and time t ₁ in FIG.
(waveform 809) and if the silent flag signal SF is set, the decision process 723 begins to make a decision. Since the SF signal is not enabled between time t ₀ and time t ₁ , each
Step 725 is entered for the CLT crop pulse. The decision process 725 determines that the sign changer 13
At 0 the current coded signal C _o is tested as a silent code SC. The coded signal C _o is an inverse unvoiced code SC
, then C _o is varied by the modifier logic of circuit 130 . (See step 729.) Otherwise, the unmodified C _o code is placed in code processing unit 125 for transmission or storage. When time t ₁ is reached, the operation of the encoding device changes. The encoded signals C _o , d _o , Δ _o are in boxes 710,
The d _nax and d _o signals generated as shown at 712 and stored in the adaptive threshold circuit 112 are compared. (See step 715.) However, the value of the signal d _o at time t ₁ is the adaptive threshold signal TH
Since it is less than 1, the silent flag setting process 735 is entered via the decision process 720. signal
SF is enabled in silence detector 115 and the contents of silence counter 120 are
Increment by. A wait step 708 is entered to detect the crop pulse signal CL for the next speech signal symbol. Between times _t1 and _t2 , the value of the logarithmic step size signal _do is smaller than the value of the threshold signal TH2. Consequently, since the silent counter increment step 738 is entered via the silent flag setting step 735 or the determining step 723, the silent period is determined by step 73.
I am continuing to keep track of time as instructed by 8. When time t ₂ is reached, the value of logarithmic step size signal d _o is greater than the value of speech onset threshold TH 2 in decision step 740 .
The silent flag reset process 742 is the determination process 72.
0,723,740. Therefore, the silent period signal at the detector 115
SF is reset and the silent period ends. The unvoiced leading signal (SC=87 ₁₆ ) and the unvoiced count signal (SCT) are formed in a code processing device 125 that is responsive to resetting of the signal SF. The contents of the silent counter are then cleared to zero by step 746. After unvoiced code testing and reordering by steps 725 and 729 in code change circuit 130, the current C _o code is placed in code processing unit 125. The unvoiced code SC and the unvoiced count SCT are the time t ₂
and time t ₃ in the data stream stored in code processor 125, as shown in waveform 813 between time t3 and time t3. As a result, the C _o code from code changer 130 has been added to the data stream since no more silent periods are detected. The symbols of the data stream handled by processor 125, including the silent and silent count symbols, are illustrated in waveform 815. The circuit shown in FIG.
A digital processing device having an arrangement for storing silent edit codes received from a computer. waveform 80
1, a digital code string shown at 815 is placed in the processing unit of circuitry 140. As shown in waveform 815, the silent period between time t ₁ and time t ₂ is replaced by a silent code SC placed before the silent count SCT. In this way,
Storage requirements on circuitry 140 are effectively reduced. The digital code from network 140 is sent to decoder 15.
Decoder 150 operates to create a replica of the speech pattern originally supplied to microphone 101, including silent periods. In the decoder 150, the adaptively digitally encoded signal is passed through a silent code detector and a counter 152.
and the selector circuit 160, a first-in/first-out shift register 150
It has been added via. clock pulse CLR from generator 153 for applying a digitally encoded signal sequence to detector 152 and selector 160;
The shift register 151 can respond to this and operate accordingly. The selector 1 passes the code C _o directly to an adaptive decoder 165 for conversion into speech samples.
60 can be operated normally. Bell System Technical Magazine by JRBoddie et al.
Adaptive Differential Pulse Code Modulation
The decoder 165 is constituted by an ADPCM decoder of the type described in the paper entitled "Modulation Coding"). Alternatively, the decoder can be constructed using the Motorola 6800 microprocessor described above, which operates according to instructions stored in read-only storage. Appendix C lists the permanently stored instructions required to decode an ADPCM signal encoded in the FORTRAN language. Upon detection of unvoiced codes in detection circuit 152, selector 160 connects code generator 155 to adaptive decoder 165. For the time interval set in the silent count code SCT,
Generator 155 generates a C _o code equivalent to a silent period. Silence periods are clocked and determined by silence counter 152. In this method, silent periods are reinserted into the codestream. The sampled signal sequence from the adaptive decoder 165 was originally
This corresponds to the original encoded speech waveform including silent periods. The sampled speech signal is converted to an analog format signal via a D/A converter 170 and a low frequency converter 175, and a speech pattern is generated in a converter 180. The unvoiced code detector and counter circuit 152,
This is shown in more detail in FIG. Referring to Figure 9,
The adaptively encoded signal sequence sent out from network 140 is applied to the input terminal of multi-stage shift register 905 . The codes from register 905 are provided to the input terminals of comparator 915 where they are compared with the 87 ₁₆ silent codes generated in code generator 920.
Upon detection of the code ₈₇₁₆ from shift register 905, comparator 915 is enabled. The enabled signal SL from comparator 915 is
AND gate 930 is alerted to preset counter 940 to the silent count symbol on line 927. The enabled signal SL causes flip-flop 925 to be set, and the signal SL1 from flip-flop 925 is set on line 181.
is separated from the input of the adaptive decoder 165, and the unvoiced code generator 155 is connected to the input terminal of the adaptive decoder. Signal SL1 can also be inhibited from outputting from AND gate 156, in which case FIFO shift register 151 will not provide an encoded signal throughout the silent countdown period.
Subsequent clock pulses CLR are applied via AND gate 935 to decrement the count of the contents of counter 940 until a zero count is reached. At that time, the borrow output of counter 940 resets silent period flip-flop 925 and signal SL1 is disabled. Selector 160
connects line 181 to adaptive decoder 165;
The adaptive code stream sent out from the FIFO register 151 is supplied to the decoder 165. The operating sequence of decoding circuit 150 is shown in the flow diagram of FIG. 10, and the waveforms associated with this operation are shown in FIG. Waveform 1101 in FIG.
shows an adaptively encoded signal sequence transmitted and received from network 140. Between time t ₀ and time t ₁ , adaptive digital codes C ₁ -C _o are sequentially applied to decoder 150 . A silent code SC placed after the code C _o and before the silent count code SCT
appears in the data stream of waveform 1101. These two
The two symbols represent silent periods in the speech signal. Following the silent period, an adaptive digital code sequence appears starting from code C _o+1 . In FIG. 10, the registers, flip-flops, and latches of the decoder 150 are shown in operation step 1.
It is initially reset by 001. Process 10
07 is entered via the clock wait process 1005 when the next clock pulse CLR is issued. Between time t ₀ and time t ₁ in FIG. 1, speech codes C ₁ , C ₂ . . . C _o are received from network 140 . For each received pulse, an output sample is formed in decoder 165 by operation 1007. In decision step 1009, the SL1 signal from flip-flop 925 is examined.
(See decision step 1009.) During the speech period from time _t0 to time _t1 , signal SL1 is not set and the next input symbol from FIFO 150 is received. (See step 1020.) Since the input code is not an unvoiced code, step 1029 is replaced by decision step 1025.
is entered through the input sample and decodes the input sample. When time t ₁ is reached, the input code is a silent code
It is SC. The SC code is detected in comparator 915 and step 1034 is entered via decision step 1025. Step 1034 extracts the silent count M from shift register 905 (waveform 110
7) is sent, counter 940 is loaded. Silent code generator 155 is connected to decoder 165 by enabled signal SL1 (waveform 1105). Upon the occurrence of the next clock pulse CL, step 1040 is entered via decision step 1009;
The contents of the silent counter are decremented in step 1040. The content of the silent counter remains greater than zero until time _t2 . Consequently, step 1036 can be performed via step 1042, with the unvoiced code string from generator 155 being applied to decoder 165. At time t ₂ , the silent count decrements to zero (see waveform 1107), and flip-flop 925 passes through step 1042 to step 104.
4 can be reset. After time t ₂ , the normal operation on the input code is steps 1005, 1007, 1
009, 1020, 1025, 1029. The inputs to the decoder 165 as shown in waveform 1109 are time t ₁ and time
It includes a silent period between t ₂ and waveform 11.
It can be reconfigured to respond to SC and silent count codes at 01. Although the invention has been described herein with reference to specific embodiments, it will be apparent to those skilled in the art that various changes can be made without departing from the spirit and scope of the invention. For example, the ADPCM type encoder and decoder described in this specification are:
Other forms of adaptive digital encoder and decoder devices can be replaced by methods such as adaptive PCM. [Table] [Table] [Table]

[Brief explanation of the drawing]

1 is a block diagram of a digital voice communication circuit according to the present invention; FIG. 2 is a detailed block diagram of an adaptive encoder useful in the circuit of FIG. 1; and FIG. 3 is a detailed block diagram of an adaptive encoder useful in the circuit of FIG. FIG. 4 is a detailed block diagram of an adaptive threshold generator useful in the circuit of FIG. 1; FIG. 5 is a detailed block diagram of a silence counter device useful in the circuit of FIG. 6 is a detailed block diagram of a sign change circuit useful in the circuit of FIG. 1; FIGS. 7 and 10 are flowcharts illustrating the operation of the circuit of FIG. 1; FIGS. 11 is a waveform diagram showing the operation of the circuit of FIG. 1, and FIG. 9 is a detailed block diagram of an unvoiced code detector and counter device useful in the circuit of FIG. [Description of symbols of main parts], 103...Low frequency generator and sampling device, 105, 170...A/D converter, 110...Encoder, 112...Threshold generator, 115...Silence detector , 120... Silent counter, 125... Code processing device, 130... Code changing device, 140... Circuit network, 150, 165...
...Decoder, 151...Shift register, 152...
...Unvoiced code detector and counter, 155...Unvoiced code generator, 160...Selector, 107, 153...
...Clock signal generator, 210...Step size generator.

Claims (1)

[Scope of Claims] 1. In a speech processing system having means for converting a speech pattern into an adaptively digitally encoded signal sequence and means for detecting a silent period in the speech pattern, means for generating a digitally encoded signal representative of a silent period in response to a period; and combining the adaptive digitally encoded signal and the digitally encoded signal representative of the silent period to form a digital signal corresponding to the pattern. means for forming a signal corresponding to an adaptive step size, the converting means comprising means for forming a signal representing the logarithm of the adaptive step size for each adaptively digitally encoded signal; means for generating a first threshold signal and a second threshold signal greater than the first threshold signal; means for generating a signal representative of a silent period in response to a size equivalent signal; and means for terminating the silent period signal in response to the silent period signal and the adaptive step size equivalent signal increasing by a greater amount than the second threshold signal. means for generating a third signal in response to the first threshold signal having a value larger than the step size equivalent signal; means for initializing the silent period signal in response to a third signal; means for generating a fourth signal in response to the step size equivalent signal greater than the second threshold signal; A speech processing system comprising means for terminating the silent period signal in response to both a period signal and the fourth signal. 2. The speech processing system according to claim 1, wherein the threshold signal generating means includes means for generating signals at first and second predetermined levels;
means for generating a signal representing a maximum step size equivalent signal in the train of step size equivalent signals in response to the train of step size equivalent signals; and means for generating a signal representing a maximum step size equivalent signal in the train of step size equivalent signals; means for generating an adaptive first threshold level signal both responsive to said maximum step size level signal and said second predetermined level signal; and means for generating a two-threshold level signal. 3. The speech processing system according to claim 1 or 2, wherein a digitally encoded signal sequence representing the speech is stored in response to the adaptive digitally encoded signal and the silent period encoded signal. A speech processing system comprising means for: 4. A speech processing system according to claim 3, further comprising means for configuring the speech pattern corresponding to the speech in response to a stored digital code string. 5. A method for processing speech comprising the steps of: converting a speech pattern into a sequence of adaptively digitally encoded signals; and detecting silent periods in said speech pattern, each detected silent period representing generating a digitally encoded signal and combining the adaptive digitally encoded signal and the silent period indicating encoded signal to form a digital signal representative of the speech pattern; and converting the speech pattern. a step of forming a signal representing the logarithm of the adaptive step size for each adaptive digital encoded signal; and a step of forming a signal corresponding to the adaptive step size; a second threshold signal that is greater than the first threshold signal; generating a signal indicative of the silent period in response to the silent period; and terminating the silent period signal in response to the silent threshold signal and the adaptive step size equivalent signal increasing greater than the second threshold signal. The step of generating the silent period signal is a step of generating a third signal in response to the first threshold signal which is larger than the step size equivalent signal, and the step of generating the third signal. a step for initializing the silent period in response to the signal; a step for generating a fourth signal in response to the step size equivalent signal greater than the second threshold signal; and terminating the silent period signal in response to the fourth signal. 6. The method according to claim 5, wherein the step of generating the threshold signal includes a step of generating signals of first and second predetermined levels, and a step of generating the step size equivalent signal. a step for generating a signal representative of said maximum step size equivalent signal in a column; and an adaptive first level signal responsive together to said maximum step size equivalent signal and said predetermined first level signal. and generating an adaptive second level threshold signal in response to the maximum step size equivalent signal and the second predetermined level threshold signal. A method characterized by comprising a process.