JPH0467632A - Multilayer wiring formation in semiconductor device - Google Patents
Multilayer wiring formation in semiconductor deviceInfo
- Publication number
- JPH0467632A JPH0467632A JP18122490A JP18122490A JPH0467632A JP H0467632 A JPH0467632 A JP H0467632A JP 18122490 A JP18122490 A JP 18122490A JP 18122490 A JP18122490 A JP 18122490A JP H0467632 A JPH0467632 A JP H0467632A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- semiconductor device
- interlayer insulating
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 230000015572 biosynthetic process Effects 0.000 title abstract description 7
- 239000010410 layer Substances 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 38
- 239000011229 interlayer Substances 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 238000009751 slip forming Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 1
- 238000002161 passivation Methods 0.000 abstract description 9
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- 230000004888 barrier function Effects 0.000 abstract description 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- UPSOBXZLFLJAKK-UHFFFAOYSA-N ozone;tetraethyl silicate Chemical compound [O-][O+]=O.CCO[Si](OCC)(OCC)OCC UPSOBXZLFLJAKK-UHFFFAOYSA-N 0.000 abstract 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 1
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 239000011574 phosphorus Substances 0.000 abstract 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 18
- 230000006866 deterioration Effects 0.000 description 9
- 238000005755 formation reaction Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000005587 bubbling Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の多層配線の形成方法に係り、特
に下層配線層により生じる段差を緩和するため、層間絶
縁膜を平坦に形成し、かつ、長寿命で信頼性の高い半導
体装置の多層配線の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for forming multilayer wiring in a semiconductor device, and in particular, in order to alleviate steps caused by lower wiring layers, an interlayer insulating film is formed flat, The present invention also relates to a method for forming multilayer wiring for a semiconductor device that has a long life and is highly reliable.
従来の半導体装置、例えばバイポーラ集積回路。 Conventional semiconductor devices, such as bipolar integrated circuits.
ＭＯ３集積回路では、高集積密度化のため多層配線が施
されている。このような半導体装置では、下層Ａ２配線
層は、基板のＡ！配線が施されていない部分に対して段
差形状となる。従って、層間絶縁膜を介して上層Ａ！配
線層にもこの段差形状が転写される。するとこの段差部
に応じて上層へ！配線層の厚みが薄くなる部分が生じ、
その結果へ！配線の断線が生じる虞れがあった。In MO3 integrated circuits, multilayer wiring is used to achieve high integration density. In such a semiconductor device, the lower A2 wiring layer is connected to A! of the substrate. It has a stepped shape with respect to the part where wiring is not applied. Therefore, the upper layer A! This step shape is also transferred to the wiring layer. Then, go to the upper layer according to this step! There are parts where the thickness of the wiring layer becomes thinner,
To the result! There was a risk that the wiring would break.
そこで、段差の溝内に絶縁膜を埋め込んで層間絶縁膜を
平坦化し、かつ、基板及びＡＩ！、配線層に損傷を与え
ないように低温下で層間絶縁膜を形成する方法としてＳ
ＯＧ法（スピンオングラス法）が知られている。Therefore, an insulating film is buried in the groove of the step to flatten the interlayer insulating film, and the substrate and AI! , S is a method for forming an interlayer insulating film at low temperatures so as not to damage the wiring layer.
The OG method (spin-on-glass method) is known.
しかしながら、ＳＯＧ法では平坦な５ｉｎ２膜（ＳＯＣ
膜）を形成する際、無機系Ｓｉ化合物溶液を用いており
、険しい段差を平坦化するためＳＯＧ膜の膜厚が厚（な
るに従い、加熱の際に溶剤が蒸発してＳＯＧ膜の体積変
化（凝固）が生じるため、ＳＯＧ膜のエツジ部にクラッ
クが生じて半導体装置の電気的特性の著しい劣化を生じ
ることになる。このため、クランクを発生することなく
ＳＯＧ法によって緩和できる段差は、４０００人程度変
則度であることが知られていた。However, in the SOG method, a flat 5in2 film (SOC
When forming the SOG film, an inorganic Si compound solution is used to flatten the steep steps. This causes cracks to occur at the edges of the SOG film, resulting in significant deterioration of the electrical characteristics of the semiconductor device.For this reason, the difference in level that can be alleviated by the SOG method without producing a crank is 4,000 people. It was known to have a degree of irregularity.
そこで、４０００人を大幅に越えるような険しい段差が
生じても、クランクを発生することなく層間絶縁膜の平
坦化を行うことができる従来例として、有機系Ｓｉ化合
物である。テトラエトキシシラン−０３（以下、ノンド
ープオゾンＴＥＯ３゜と称する）からなるガス系をソー
スガスとして用い、常圧、低温下のＣＶＤによる成膜反
応を行い、分解の結果生じるＳｉｎ、のりフロー性によ
り段差部の平坦化を行う従来例が知られている（例えば
、セミコンニューズ、１９８８．１）。Therefore, an organic Si compound is used as a conventional example that can flatten the interlayer insulating film without causing cranking even if there is a steep step difference that greatly exceeds 4,000 people. Using a gas system consisting of tetraethoxysilane-03 (hereinafter referred to as non-doped ozone TEO3°) as a source gas, a film formation reaction is performed by CVD at normal pressure and low temperature. A conventional example of flattening the area is known (for example, Semicon News, 1988.1).
そして、通常、半導体装置は、湿度等の外気による素子
特性の劣化を防ぐため、半導体装置の表面にパッシベー
ション膜（最終保護膜）を有している。このパッシベー
ション膜として一般的に用いられる窒化シリコン膜は、
プラズマＣＶＤ法により半導体装置表面に形成する際、
モア゛ノラン（ＳｉＨ４）−アンモニア（ＮＨ，）系が
多く用いられ、２００〜４００°Ｃで次式の反応が利用
される。Generally, a semiconductor device has a passivation film (final protective film) on the surface of the semiconductor device in order to prevent deterioration of device characteristics due to outside air such as humidity. The silicon nitride film commonly used as this passivation film is
When forming on the surface of a semiconductor device by plasma CVD method,
The monoalane (SiH4)-ammonia (NH,) system is often used, and the reaction of the following formula is used at 200 to 400°C.
３Ｓ ｉＨ４＋４ＮＨ：Ｉ→Ｓ ｉ＊Ｎａ ＋ １２
Ｈｚ〔発明が解決しようとする課題〕
しかしながら、前記従来例では、半導体装置の平坦化は
達成されたが、前記パッシベーション膜を形成する反応
の際に生じるＨ２がホットキャリア現象を引き起こす主
原因となっていた。このホットキャリヤ現象により生じ
た電子の一部が層間絶縁膜に飛び込み捕獲され、しきい
電圧が変わる。3S iH4+4NH: I→S i*Na + 12
Hz [Problem to be solved by the invention] However, in the conventional example, although flattening of the semiconductor device was achieved, H2 generated during the reaction to form the passivation film was the main cause of the hot carrier phenomenon. was. Some of the electrons generated by this hot carrier phenomenon fly into the interlayer insulating film and are captured, changing the threshold voltage.
この現象は、半導体装置の動作に伴って生じるため、回
路の誤動作が生じ易くなり、半導体装置の信転性をなく
し、さらに、寿命劣化を引き起こし易いという課題があ
った。Since this phenomenon occurs along with the operation of the semiconductor device, there are problems in that the circuit is likely to malfunction, the reliability of the semiconductor device is lost, and the life of the device is likely to be deteriorated.
そこで、このような課題を解決するために本発明は、半
導体装置の多層配線の形成方法において、層間絶縁膜の
平坦化を行い、かつ、耐ホツトキャリア性に優れ、半導
体装置特性の変動、劣化をきたすことなく多層配線を形
成可能な、半導体装置の多層配線の形成方法を提供する
ことを目的とする。Therefore, in order to solve these problems, the present invention provides a method for forming multilayer wiring in a semiconductor device, in which the interlayer insulating film is flattened, has excellent hot carrier resistance, and is free from fluctuations and deterioration of the characteristics of the semiconductor device. It is an object of the present invention to provide a method for forming multilayer wiring for a semiconductor device, which can form multilayer wiring without causing problems.
〔課題を解決するための手段］
この目的を達成するために本発明は、下層配線層上に層
間絶縁膜を形成し、前記層間絶縁膜上に上層配線層を形
成する半導体装置の多層配線の形成方法において、前記
下層配線上にリフロー性を有する絶縁膜を形成する第一
工程と、当該第一工程の膜上に不純物をドープした絶縁
膜を連続して形成し水素を固定できる第二工程と、を備
えてなり、第一工程の膜と第二工程の膜とで層間絶縁膜
を形成する半導体装置の多層配線の形成方法であること
を特徴とするものである。[Means for Solving the Problems] In order to achieve this object, the present invention provides a multilayer wiring structure for a semiconductor device in which an interlayer insulating film is formed on a lower wiring layer, and an upper wiring layer is formed on the interlayer insulating film. The formation method includes a first step of forming an insulating film with reflow properties on the lower wiring, and a second step of continuously forming an insulating film doped with impurities on the film of the first step to fix hydrogen. The present invention is characterized in that it is a method for forming a multilayer wiring of a semiconductor device, comprising the following steps, and an interlayer insulating film is formed by a film in a first step and a film in a second step.
〔作用］
この発明に係る半導体装置の多層配線の形成方法によれ
ば、下層配線層上に層間絶縁膜を形成し、前記層間絶縁
膜上に上層配線層を形成する半導体装置の多層配線の形
成方法において、段差のある前記下層配線上に、リフロ
ー性を有する絶縁膜を形成する第一工程を有することで
、前記段差を緩和し、当該絶縁膜を平坦に形成すること
ができる。[Function] According to the method for forming a multilayer wiring for a semiconductor device according to the present invention, an interlayer insulating film is formed on a lower wiring layer, and an upper wiring layer is formed on the interlayer insulating film. The method includes a first step of forming an insulating film having reflow properties on the lower layer wiring having a step, thereby making it possible to alleviate the step and form the insulating film flat.
そして、第一工程で得た膜上に、さらに連続して不純物
をドープした絶縁膜を形成し水素を固定できる第二工程
を有することで、前記半導体装置のパッシベーション膜
の形成過程で生じる、ホットキャリヤ現象の主原因であ
るＨ２を当該絶縁膜が固定し、Ｈ２に対する障壁層とし
て作用して、ホットキャリア現象を引き起こすことを防
ぐことができる。Then, by having a second step in which an insulating film doped with impurities is continuously formed on the film obtained in the first step to fix hydrogen, hot spots generated in the process of forming the passivation film of the semiconductor device can be removed. The insulating film fixes H2, which is the main cause of the carrier phenomenon, and acts as a barrier layer against H2, thereby preventing the hot carrier phenomenon from occurring.
このため、第一工程の絶縁膜と第二工程の絶縁膜とで層
間絶縁膜を形成することで、当該層間絶縁膜は平坦化さ
れ、かつ、耐ホツトキャリア性に優れ、半導体装置特性
の変動、劣化をきたすことなく多層配線を形成可能な、
半導体装置の多層配線の形成方法を提供することができ
る。Therefore, by forming an interlayer insulating film with an insulating film in the first step and an insulating film in the second step, the interlayer insulating film can be flattened, has excellent hot carrier resistance, and changes in semiconductor device characteristics. , it is possible to form multilayer wiring without causing deterioration,
A method for forming multilayer wiring in a semiconductor device can be provided.
次に本発明の実施例について、図面に基づいて説明する
。Next, embodiments of the present invention will be described based on the drawings.
第１図ないし第４図は、本発明の一実施例に係る多層配
線の形成方法を示す断面構成図である。1 to 4 are cross-sectional configuration diagrams showing a method of forming a multilayer wiring according to an embodiment of the present invention.
第１図の工程では、Ｓｉ基板１上に、所定のパターンに
従い下層Ａ！配線層２を形成する。In the process shown in FIG. 1, lower layers A! A wiring layer 2 is formed.
次に、第２図の工程で、第１図の工程で得た全面に常圧
ＣＶＤ装置により絶縁膜として、ノンドープオゾンＴＥ
Ｏ３膜３を形成する。常圧ＣＶＤ装置に導入されるソー
スガスとしては、Ｓ １ ； ２０％、０．；７５％、
Ｎｚ；６０％を導入する。Next, in the step shown in FIG. 2, an insulating film is formed on the entire surface obtained in the step shown in FIG.
An O3 film 3 is formed. The source gases introduced into the atmospheric pressure CVD apparatus include S 1 ; 20%, 0. ;75%;
Nz: 60% is introduced.
処理温度は３８０°Ｃとし、５〜８分間行い、ノンドー
プオゾンＴＥＯ３膜３の厚さを４０００〜６０００人程
度に形成する変
則Ｅ０１は蒸気圧が低い気体状の有機Ｓｉ化合物である
ので、常圧ＣＶＤ装置への導入に際しては、数１０℃の
加熱を行い窒素によるバブリングを必要とする。The treatment temperature is 380°C, the process is carried out for 5 to 8 minutes, and the thickness of the non-doped ozone TEO3 film 3 is approximately 4000 to 6000 mm.Since the anomaly E01 is a gaseous organic Si compound with a low vapor pressure, the treatment is carried out at normal pressure. When introducing into a CVD apparatus, heating to several tens of degrees Celsius and bubbling with nitrogen are required.
一方オシンはＴＥ０１の酸化３分解を促進してＳｉｎ、
を形成するために、反応ガス中に添加されるものであり
、反応ガス中に１８０００ｐｐｍ含有される。オゾンの
導入については、放電を利用して、酸素の分解を行う。On the other hand, osin promotes the oxidative 3-decomposition of TE01 to form Sin,
It is added to the reaction gas to form 18,000 ppm of the reaction gas. Regarding the introduction of ozone, oxygen is decomposed using electric discharge.
この常圧ＣＶＤに際しては、オゾンがＴＥ０１の分解を
促進するため、低温（３５０°Ｃ）下においても大きな
成長速度（成膜温度３８０°Ｃ前後において１００〜５
０００人／分で制御可能）でノンドープオゾンＴＥＯ３
膜３の形成が可能である。During this atmospheric pressure CVD, ozone promotes the decomposition of TE01, so even at low temperatures (350°C), the growth rate is high (100 to 50% at a film forming temperature of around 380°C).
000 people/min) non-doped ozone TEO3
Formation of membrane 3 is possible.
従って、下層Ａｊ２配線層２に損傷を与える虞れがない
。このノンドープオゾンＴ Ｅ’ ＯＳ膜３は絶縁膜で
あると共に、下層Ａ２配線２同士の間に存在する溝（下
層Ａ１配線２とＳｉ基板１との段差）に埋め込まれて、
下層Ａ！配線２によって生した段差を緩和して平坦化す
る。Therefore, there is no risk of damaging the lower Aj2 wiring layer 2. This non-doped ozone T E' OS film 3 is an insulating film, and is embedded in the groove (step difference between the lower layer A1 wiring 2 and the Si substrate 1) existing between the lower layer A2 wirings 2.
Lower layer A! The step created by the wiring 2 is alleviated and flattened.
また、ノンドープオゾンＴＥＯ３膜３は、ＴＥＯＳガス
から形成されるため、凝固の際の収縮の影響がない結果
、ノンドープオゾンＴＥＯ３膜３を厚く形成してもクラ
ンク発生の問題もない。また、ノンドープオゾンＴＥＯ
３膜の厚さは、下層Ａｌ・配線２の厚さ（高さ）により
任意に決定し、常圧ＣＶＤの処理時間により所望の厚さ
に調整することができる。Furthermore, since the non-doped ozone TEO3 film 3 is formed from TEOS gas, it is not affected by shrinkage during solidification, so there is no problem of cranking even if the non-doped ozone TEO3 film 3 is formed thick. In addition, non-doped ozone TEO
The thickness of the three films can be arbitrarily determined depending on the thickness (height) of the lower Al layer and the wiring 2, and can be adjusted to a desired thickness by the normal pressure CVD processing time.
次に、第３図の工程では、第２図の工程に連続して、第
２図の工程で形成した、平坦化されたノンドープオゾン
ＴＥＯ３膜３上に絶縁膜として、リンドープオゾンＴＥ
Ｏ３膜４を常圧ＣＶＤ装置にて形成する。この時、第２
図の工程で常圧ＣＶＤ装置に導入したソースガスとして
、Ｓｉ；３０％、Ｏ＋；７５％、Ｎ、；６０％、Ｐ、３
０％を導入する。その他の処理条件は第２図の工程と同
様に行い、厚さ２０００〜４０００人のリンドープオゾ
ンＴＥＯ３膜４を形成する。Next, in the process shown in FIG. 3, following the process shown in FIG.
The O3 film 4 is formed using an atmospheric pressure CVD apparatus. At this time, the second
The source gases introduced into the atmospheric pressure CVD apparatus in the process shown in the figure are Si: 30%, O+: 75%, N: 60%, P, 3
Introduce 0%. Other processing conditions are the same as in the process shown in FIG. 2, and a phosphorus-doped ozone TEO3 film 4 having a thickness of 2,000 to 4,000 thick is formed.
このリンドープオゾンＴＥＯ３膜４は、パッシベーショ
ン膜を形成する際に発生するホットキャリヤ現象の主原
因であるＨ２を固定し、Ｈ２に対する障壁層として作用
する。このため、ホットキャリヤ現象を防ぐことができ
る。This phosphorus-doped ozone TEO3 film 4 fixes H2, which is the main cause of the hot carrier phenomenon that occurs when forming a passivation film, and acts as a barrier layer against H2. Therefore, the hot carrier phenomenon can be prevented.
前記ノンドープオゾンＴＥＯ３膜３と前記リンドープオ
ゾンＴＥＯ３膜４とで、層間絶縁膜を形成する。The non-doped ozone TEO3 film 3 and the phosphorus-doped ozone TEO3 film 4 form an interlayer insulating film.
そして、第４図の工程では、第３図の工程で得た平坦化
されたリンドープオゾンＴＥＯ３膜４の上に上層ＡＩ２
配線層５を形成する。In the step shown in FIG. 4, an upper layer of AI2 is placed on the flattened phosphorus-doped ozone TEO3 film 4 obtained in the step shown in FIG.
A wiring layer 5 is formed.
第４図の工程後、第２図以降の工程を繰り返すことで、
所望の多層配線を有する半導体装置を製造することがで
きる。After the process shown in Figure 4, by repeating the process from Figure 2 onwards,
A semiconductor device having desired multilayer wiring can be manufactured.
最後に、半導体装置の表面にパッシベーション膜を形成
する。Finally, a passivation film is formed on the surface of the semiconductor device.
以上の工程により、平坦化され、かつ、耐ホツトキャリ
ア性に優れ、半導体装置特性の変動、劣化をきたすこと
なく多層配線を形成することができた。Through the above steps, it was possible to form a multilayer interconnection that was planarized, had excellent hot carrier resistance, and did not cause any fluctuation or deterioration of the characteristics of the semiconductor device.
そして、配線層ごとにリンドープオゾンＴＥＯ３膜４を
形成するので、前記Ｈ２を各ＴＥ０１膜４で固定するこ
とができるため、耐ホツトキャリア性をより確実にする
。Since the phosphorus-doped ozone TEO3 film 4 is formed for each wiring layer, the H2 can be fixed in each TE01 film 4, thereby making the hot carrier resistance more reliable.
次に、本実施例により製造した半導体装置（発明品）と
従来の製造方法で製造した層間絶縁膜に不純物をドープ
していない半導体装置（従来品）との寿命劣化を比較し
た。比較方法は、半導体装置に最大電圧（５，５Ｖ）を
かけ、その時のｇｍ（しきい電圧）の低下が１０％とな
った時を寿命劣化とした。なお、発明品と従来品との間
で配線層の数、配線の厚さ（高さ）、トータルの層間絶
縁膜の厚さは同一とした。Next, the life deterioration was compared between the semiconductor device manufactured according to this example (invention product) and the semiconductor device manufactured by the conventional manufacturing method in which the interlayer insulating film was not doped with impurities (conventional product). In the comparison method, the maximum voltage (5.5 V) was applied to the semiconductor device, and life deterioration was determined when the gm (threshold voltage) decreased by 10%. Note that the number of wiring layers, the thickness (height) of wiring, and the total thickness of the interlayer insulating film were the same between the invention product and the conventional product.
この結果、発明品は従来品に比べ、１０倍寿命劣化が向
上していることが確認された。As a result, it was confirmed that the invented product had 10 times better life deterioration than the conventional product.
また、第３図の工程では、不純物としてＰを用いたリン
ドープオゾンＴＥＯ３膜を形成したが、これに限らない
。Further, in the process shown in FIG. 3, a phosphorus-doped ozone TEO3 film using P as an impurity was formed, but the present invention is not limited thereto.
そして、配線としてＡＰを用いたが、／１−Ｃｕ、Ａｆ
−３ｔ、Ａｆ−Ｔａ等各種導伝性物質を用いることもで
きる。AP was used as the wiring, but /1-Cu, Af
Various conductive materials such as -3t and Af-Ta can also be used.
本実施例では、多層配線の形成方法について説明したが
、単層配線の形成方法に用いることを妨げるものではな
い。In this embodiment, a method for forming multilayer wiring has been described, but this does not preclude use in a method for forming single layer wiring.
以上説明したように本発明に係わる半導体装置の多層配
線の形成方法によれば、第一工程を有することで、絶縁
膜を平坦に形成でき、さらに、第二工程を有することで
、パッシベーション膜の形成過程で発生するＨ２を固定
することができる。As explained above, according to the method for forming multilayer wiring of a semiconductor device according to the present invention, the first step allows the insulating film to be formed flat, and the second step allows the formation of a passivation film. H2 generated during the formation process can be fixed.
この結果、当該層間絶縁膜は平坦化され、かつ、耐ホー
／ ）キャリア性に優れ、半導体装置特性の変動、劣化
をきたすことなく多層配線を形成可能な、半導体装置の
多層配線の形成方法をを提供することができる。As a result, the interlayer insulating film is planarized and has excellent carrier resistance, and a method for forming multilayer interconnections for semiconductor devices has been developed, which enables the formation of multilayer interconnections without causing fluctuation or deterioration of semiconductor device characteristics. can be provided.
第１図ないし第４図は、本発明の一実施例に係る多層配
線の形成方法を示す断面構成図である。
図中、１はＳｉ基板、２は下層Ａ２配線層、３はノンド
ープオゾンＴＥＯ３膜、４はリンドープオゾンＴＥＯ３
膜、５は上層ＡＩ！、配線層を示す。1 to 4 are cross-sectional configuration diagrams showing a method of forming a multilayer wiring according to an embodiment of the present invention. In the figure, 1 is a Si substrate, 2 is a lower A2 wiring layer, 3 is a non-doped ozone TEO3 film, and 4 is a phosphorus-doped ozone TEO3 film.
Membrane, 5 is upper layer AI! , indicates the wiring layer.
Claims (1)
縁膜上に上層配線層を形成する半導体装置の多層配線の
形成方法において、前記下層配線上にリフロー性を有す
る絶縁膜を形成する第一工程と、当該第一工程の膜上に
不純物をドープした絶縁膜を連続して形成し水素を固定
できる第二工程と、を備えてなり、第一工程の膜と第二
工程の膜とで層間絶縁膜を形成することを特徴とする半
導体装置の多層配線の形成方法。(1) In a method for forming a multilayer wiring of a semiconductor device, in which an interlayer insulating film is formed on a lower wiring layer, and an upper wiring layer is formed on the interlayer insulation film, an insulating film having reflow properties is formed on the lower wiring layer. a first step in which an insulating film doped with impurities is continuously formed on the film in the first step to fix hydrogen; 1. A method for forming multilayer wiring for a semiconductor device, the method comprising forming an interlayer insulating film with a film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18122490A JPH0467632A (en) | 1990-07-09 | 1990-07-09 | Multilayer wiring formation in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18122490A JPH0467632A (en) | 1990-07-09 | 1990-07-09 | Multilayer wiring formation in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0467632A true JPH0467632A (en) | 1992-03-03 |
Family
ID=16096985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18122490A Pending JPH0467632A (en) | 1990-07-09 | 1990-07-09 | Multilayer wiring formation in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0467632A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6462394B1 (en) | 1995-12-26 | 2002-10-08 | Micron Technology, Inc. | Device configured to avoid threshold voltage shift in a dielectric film |
| US7067442B1 (en) | 1995-12-26 | 2006-06-27 | Micron Technology, Inc. | Method to avoid threshold voltage shift in thicker dielectric films |
-
1990
- 1990-07-09 JP JP18122490A patent/JPH0467632A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6462394B1 (en) | 1995-12-26 | 2002-10-08 | Micron Technology, Inc. | Device configured to avoid threshold voltage shift in a dielectric film |
| US7067442B1 (en) | 1995-12-26 | 2006-06-27 | Micron Technology, Inc. | Method to avoid threshold voltage shift in thicker dielectric films |
| US8202806B2 (en) | 1995-12-26 | 2012-06-19 | Micron Technology, Inc. | Method to avoid threshold voltage shift in thicker dielectric films |
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