JPH0467687A - Diode - Google Patents
DiodeInfo
- Publication number
- JPH0467687A JPH0467687A JP2181152A JP18115290A JPH0467687A JP H0467687 A JPH0467687 A JP H0467687A JP 2181152 A JP2181152 A JP 2181152A JP 18115290 A JP18115290 A JP 18115290A JP H0467687 A JPH0467687 A JP H0467687A
- Authority
- JP
- Japan
- Prior art keywords
- impurity concentration
- conductivity type
- diode
- layer
- type layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/411—PN diodes having planar bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/60—Impurity distributions or concentrations
Landscapes
- Bipolar Transistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、低不純物濃度の第一導電形層の一側にＰＮ接
合を形成する第二導電形層が、他側に高不純物濃度の第
一導電形層が設けられるダイオードに関する。Detailed Description of the Invention [Industrial Field of Application] The present invention provides a first conductivity type layer having a low impurity concentration and a second conductivity type layer forming a PN junction on one side and a high impurity concentration layer on the other side. The present invention relates to a diode provided with a first conductivity type layer.
ダイオードＰＮ接合を有する半導体素体においては、必
要な逆耐圧を得るために接合の一方の側の層の不純物濃
度を低くする。しかし、半導体素体への電気的な接続の
ために素体表面に被着する電極のオーム性接触を可能に
するためには、不純物濃度の高い層が必要であるため、
低不純物濃度の層に接して同一導電形の高不純物濃度の
層が設けられる。第２図はそのようなダイオードの一側
を示し、Ｎ゛層１上に積層されたＮ層２の表面層に酸化
膜４をマスクとしての選択的不純物拡散により２層３が
形成されている。In a semiconductor element having a diode PN junction, the impurity concentration of a layer on one side of the junction is lowered to obtain the necessary reverse breakdown voltage. However, in order to enable ohmic contact of the electrode deposited on the surface of the element for electrical connection to the semiconductor element, a layer with a high impurity concentration is required.
A high impurity concentration layer of the same conductivity type is provided in contact with the low impurity concentration layer. Figure 2 shows one side of such a diode, in which a second layer 3 is formed on the surface layer of an N layer 2 stacked on an N layer 1 by selective impurity diffusion using an oxide film 4 as a mask. .
第２図に示すような断面構造をもつダイオードの作製に
は、Ｎ“母板１の上にＮ層２をエピタキシャル成長させ
た、第３図（ａｌに示すようなシリコン基板が用いられ
る。その不純物濃度は第３図伽）に示すような階段状の
分布をもっている。In order to manufacture a diode having a cross-sectional structure as shown in FIG. 2, a silicon substrate as shown in FIG. The concentration has a step-like distribution as shown in Figure 3).
高周波領域で用いられる高速ダイオードあるいは超高速
ダイオードでは、逆回復時間（！ｒｒ）を短くするため
、公知のようにシリコン基板に金あるいは白金等のライ
フタイムキラーを導入することが行われる。第４図はダ
イオードの高電流領域における逆回復波形を示し、線４
１はｊ ｒｒｌｏｏｎｓｅｃの一般的なソフトリカバリ
ーダイオードの逆回復電流１ｍの波形、＠４２は従来の
ｊ ｒｒ３０〜４０ｎｓｅｃの超高速ダイオードの逆回
復波形である。従来の超高速ダイオードでは、逆電流１
１の波形が急激に回復するため、実使用回路においてノ
イズ発生の原因となっていた。In high-speed diodes or ultra-high-speed diodes used in a high frequency region, in order to shorten the reverse recovery time (!rr), a lifetime killer such as gold or platinum is introduced into the silicon substrate, as is known. Figure 4 shows the reverse recovery waveform in the high current region of the diode, and line 4
1 is a waveform of a reverse recovery current of 1 m of a general soft recovery diode of j rrloon sec, and @42 is a reverse recovery waveform of a conventional ultrafast diode of j rr of 30 to 40 nsec. In conventional ultrafast diodes, reverse current 1
Since the waveform of 1 suddenly recovers, it causes noise generation in the circuit actually used.
本発明の目的は、高周波領域で使用できかつノイズ発生
のないダイオードを提供することにある。An object of the present invention is to provide a diode that can be used in a high frequency region and does not generate noise.
〔１１１題を解決するための手段〕
上記の目的を達成するために、本発明は、低不純物濃度
の第一導電形層の一側にＰＮ接合を形成する第二導電形
層が、他側に高不純物濃度の第一導電形層が設けられる
ダイオードにおいて、低不純物濃度の第一導電形層と高
不純物濃度の第−導電形の境界に厚さ４〜１０Ｊｌｓの
不純物濃度遷移領域が介在するものとする。[Means for Solving Problem 111] In order to achieve the above object, the present invention provides a first conductivity type layer having a low impurity concentration, which forms a PN junction on one side of the first conductivity type layer, and a second conductivity type layer forming a PN junction on the other side. In a diode in which a first conductivity type layer with a high impurity concentration is provided in the diode, an impurity concentration transition region with a thickness of 4 to 10 Jls is interposed at the boundary between the first conductivity type layer with a low impurity concentration and the second conductivity type layer with a high impurity concentration. shall be taken as a thing.
〔作用〕
第１図は、高不純物濃度層と低不純物濃度層の境界の濃
度分布を示し、図において、両者の間の濃度分布曲線に
引いた切線１０の高不純物濃度Ｎ、と交る点Ｘ＋および
低不純物濃度Ｎ２と交る点×２の間の幅を４層以上にす
ると、ＰＮ接合に対する順バイアスから逆バイアスに切
換わるときの空乏層内のキャリア蓄積量が制御され、逆
回復波形がソフトになってノイズが発生しなくなる。し
かし、Ｘｌ〜ｘ２を１０−以上にするとｔい、が長くな
りすぎて高周波領域で使用できなくなる。[Operation] Figure 1 shows the concentration distribution at the boundary between the high impurity concentration layer and the low impurity concentration layer, and in the figure, the point where the line 10 intersects with the high impurity concentration N drawn on the concentration distribution curve between the two. If the width between X+ and the point x2 where it intersects with low impurity concentration N2 is 4 or more layers, the amount of carrier accumulation in the depletion layer when switching from forward bias to reverse bias to the PN junction is controlled, and the reverse recovery waveform is becomes soft and no noise occurs. However, if Xl to x2 are set to 10- or more, t becomes too long and cannot be used in a high frequency region.
以下、図を引用して本発明の実施例について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第３図ｆａ）に示した断面構造をもち、０．００３Ω１
以下の比抵抗で約４５０−の厚さのＮ゛シリコン母板１
の上に５〜８Ω備の比抵抗で約２５−の厚さのＮ９９３
７層２をエピタキシャル成長させるとき、ドーピングガ
スを制御して第１図のような濃度分布をもち、Ｘ、〜ｘ
２が４〜１（ｂｒ＋ｓになるようにした。このようなシ
リコン基板に不純物拡散により第２図に示すような２層
３を形成し、さらにライフタイムキラーとしての金ある
いは白金を導入した。これによって第５図に示すような
不純物濃度をもつダイオードが作製された。このダイオ
ードの逆回復波形は第４図の線４３で、線４２に比して
ソフトになり、実使用回路においてノイズの発生を抑え
ることができた。It has the cross-sectional structure shown in Figure 3 fa), and has a 0.003Ω1
N゛ silicon mother plate 1 with a thickness of about 450- with the following specific resistance:
N993 of about 25-mm thickness with a resistivity of 5-8 ohms on top.
7 When layer 2 is epitaxially grown, the doping gas is controlled to have a concentration distribution as shown in Figure 1, and X, ~ x
2 was made to be 4 to 1 (br+s). Two layers 3 as shown in FIG. 2 were formed on such a silicon substrate by impurity diffusion, and gold or platinum was further introduced as a lifetime killer. A diode with an impurity concentration as shown in Fig. 5 was fabricated by using the method shown in Fig. 5.The reverse recovery waveform of this diode is line 43 in Fig. 4, which is softer than line 42, and is likely to cause noise in actual circuits. was able to suppress it.
本発明によれば、ダイオードのＰＮ接合を形成する低不
純物濃度の層と同−導電形の高不純物濃度の層との境界
に所定の厚さの不純物濃度遷移領域を設けて適切な濃度
勾配をつけることにより、順バイアスから逆バイアスへ
の切換え時の空乏層内のキャリア蓄積量をｍｉｉするこ
とができ、逆回復波形がソフトになってノイズの発生を
阻止することができるようになった。According to the present invention, an impurity concentration transition region of a predetermined thickness is provided at the boundary between a low impurity concentration layer forming a PN junction of a diode and a high impurity concentration layer of the same conductivity type to create an appropriate concentration gradient. By adding this, the amount of carriers accumulated in the depletion layer at the time of switching from forward bias to reverse bias can be reduced to mii, and the reverse recovery waveform becomes softer, making it possible to prevent the generation of noise.
第１図は本発明の実施例に用いるシリコン基板の不純物
濃度分布図、第２図は本発明の実施されるダイオードの
断面図、第３図は第２図のダイオードの作製に用いるシ
リコン基板を示し、ｉａ）は断面図、（ｂｌは従来の不
純物濃度分布図、第４図は本発明の実施例および従来例
のダイオードの逆回復波形図、第５図は本発明の実施例
の不純物濃度分布図である。
１：Ｎ”層 （Ｎ”基板）
２：Ｎ層、３：２層。
代Ｊ１人、［１１七 山 口 巌
第５図FIG. 1 is an impurity concentration distribution diagram of a silicon substrate used in an example of the present invention, FIG. 2 is a cross-sectional view of a diode in which the present invention is implemented, and FIG. 3 is a diagram of a silicon substrate used for manufacturing the diode of FIG. ia) is a cross-sectional view, (bl is a conventional impurity concentration distribution diagram, FIG. 4 is a reverse recovery waveform diagram of the diode of the embodiment of the present invention and the conventional example, and FIG. 5 is the impurity concentration of the embodiment of the present invention. This is a distribution diagram. 1: N'' layer (N'' substrate) 2: N layer, 3: 2 layers.
Claims (1)
成する第二導電形層が、他側に高不純物濃度の第一導電
形層が設けられるものにおいて、低不純物濃度の第一導
電形層と高不純物濃度の第一導電形の境界に厚さ４〜１
０μｍの不純物濃度遷移領域が介在することを特徴とす
るダイオード。1) A second conductivity type layer forming a PN junction on one side of the first conductivity type layer with a low impurity concentration and a first conductivity type layer with a high impurity concentration on the other side, the second conductivity type layer with a low impurity concentration The thickness is 4 to 1 at the boundary between the first conductivity type layer and the first conductivity type layer with high impurity concentration.
A diode characterized in that an impurity concentration transition region of 0 μm exists.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2181152A JPH0467687A (en) | 1990-07-09 | 1990-07-09 | Diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2181152A JPH0467687A (en) | 1990-07-09 | 1990-07-09 | Diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0467687A true JPH0467687A (en) | 1992-03-03 |
Family
ID=16095797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2181152A Pending JPH0467687A (en) | 1990-07-09 | 1990-07-09 | Diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0467687A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0932205A1 (en) * | 1998-01-21 | 1999-07-28 | GENERAL SEMICONDUCTOR, Inc. | PN junction semiconductor device having an epitaxial layer with graded resistivity |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62115880A (en) * | 1985-11-15 | 1987-05-27 | Shindengen Electric Mfg Co Ltd | P-n junction element |
-
1990
- 1990-07-09 JP JP2181152A patent/JPH0467687A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62115880A (en) * | 1985-11-15 | 1987-05-27 | Shindengen Electric Mfg Co Ltd | P-n junction element |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0932205A1 (en) * | 1998-01-21 | 1999-07-28 | GENERAL SEMICONDUCTOR, Inc. | PN junction semiconductor device having an epitaxial layer with graded resistivity |
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