JPH0467752U - - Google Patents
Info
- Publication number
- JPH0467752U JPH0467752U JP11203290U JP11203290U JPH0467752U JP H0467752 U JPH0467752 U JP H0467752U JP 11203290 U JP11203290 U JP 11203290U JP 11203290 U JP11203290 U JP 11203290U JP H0467752 U JPH0467752 U JP H0467752U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- backup
- writing
- control device
- storing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002093 peripheral effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は本考案の具体的な一実施例に係る制御
装置のメモリバツクアツプ装置を示したブロツク
ダイヤグラム。第２図及び第３図は同実施例装置
で使用されているＣＰＵの処理手順を示したフロ
ーチヤート。第４図は従来の制御装置のメモリバ
ツクアツプ装置を示したブロツクダイヤグラムで
ある。
１０……マイクロコンピユータ、１１……ＣＰ
Ｕ、１２……ＲＯＭ（システム用メモリ）、１３
……ＲＡＭ（システム用メモリ）、２０……ＲＡ
Ｍ（運転用メモリ）、３０……ＥＥＰＲＯＭ（バ
ツクアツプ用メモリ）、４０……スイツチ、１０
０……制御装置、２００……プログラム装置。
FIG. 1 is a block diagram showing a memory backup device for a control device according to a specific embodiment of the present invention. 2 and 3 are flowcharts showing the processing procedure of the CPU used in the device of the embodiment. FIG. 4 is a block diagram showing a conventional memory backup device for a control device. 10...Microcomputer, 11...CP
U, 12...ROM (system memory), 13
...RAM (system memory), 20...RA
M (operating memory), 30... EEPROM (backup memory), 40... switch, 10
0...Control device, 200...Program device.
Claims (1)
データ等を記憶するメモリを有する制御装置にお
いて、 前記制御装置には前記メモリと並列に接続され
たバツクアツプ用メモリと、 周辺機器から前記マイクロコンピユータを介し
て前記メモリにプログラムやデータ等を書き込み
記憶させる際に、前記バツクアツプ用メモリにも
同じ内容を書き込み記憶させるバツクアツプ書き
込み手段と、 前記メモリの記憶内容が損なわれた際に操作さ
れるスイツチ手段と、 前記スイツチ手段の操作により前記バツクアツ
プ用メモリの記憶内容を前記メモリに転送して書
き込み記憶させるバツクアツプメモリ転送手段と を備えたことを特徴とする制御装置のメモリバツ
クアツプ装置。[Claims for Utility Model Registration] A control device that is connected to a microcomputer and has a memory for storing programs, data, etc., wherein the control device includes a backup memory connected in parallel with the memory, and a memory that is connected to the memory from a peripheral device to the microcomputer. Backup writing means for writing and storing the same contents in the backup memory when writing and storing programs, data, etc. in the memory via a computer; and a switch that is operated when the stored contents of the memory are damaged. 1. A memory backup device for a control device, comprising: means; and backup memory transfer means for transferring the storage contents of the backup memory to the memory and writing and storing them in the memory by operating the switch means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11203290U JPH0467752U (en) | 1990-10-24 | 1990-10-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11203290U JPH0467752U (en) | 1990-10-24 | 1990-10-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0467752U true JPH0467752U (en) | 1992-06-16 |
Family
ID=31859532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11203290U Pending JPH0467752U (en) | 1990-10-24 | 1990-10-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0467752U (en) |
-
1990
- 1990-10-24 JP JP11203290U patent/JPH0467752U/ja active Pending
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